IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 1

Integrated AHB to APB Bridge Using Raspberry Pi

and Artix-7 FPGA
Gopi Chand Ananthu, Riadul Islam, Senior Member, IEEE

Abstract—This project focuses on the design and implemen- The AHB and APB are core components of ARM’s Ad-
tation of an AHB to APB Bridge for efficient communication vanced Microcontroller Bus Architecture (AMBA) standard,
in System-on-Chip (SoC) architectures. The Advanced High- which optimizes communication within SoC designs [1], [2].
performance Bus (AHB) is used for high-speed operations,
typically connecting processors and memory, while the Advanced AHB supports high-speed, high-performance communication
arXiv:2501.01147v1 [cs.AR] 2 Jan 2025

Peripheral Bus (APB) is optimized for low-power, low-speed between CPUs, memory [6], and other high-speed peripher-
peripheral devices. The AHB to APB Bridge serves as an als [1]. APB, on the other hand, is designed for lower-speed,
interface that converts complex, high-speed AHB transactions simpler peripherals, focusing on low-power data transfers
into simpler, single-cycle APB transactions, enabling seamless [2]. The AHB to APB Bridge enables these two buses to
data transfer between fast components and slower peripherals.
The bridge manages clock domain synchronization, transaction work in tandem by translating AHB’s burst-mode transac-
conversion, and flow control, ensuring compatibility between tions into APB’s single-cycle, non-pipelined transactions [3].
AHB’s burst transfers and APB’s non-pipelined protocol. Imple- This ensures efficient data exchange between these disparate
mented in Verilog and simulated on FPGA using Xilinx Vivado, components, balancing the system’s performance and energy
this bridge design provides a robust solution for integrating efficiency [7].
high-performance and low-power components within a single
SoC. This project also evaluates the bridge’s functionality and The AHB to APB Bridge offers significant benefits in
performance through testbenches covering various operational SoC designs. It enables seamless communication between
scenarios, validating its efficiency in handling diverse system high-speed AHB components and low-speed APB peripher-
requirements. als by converting burst-mode AHB transactions into simpler
Index Terms—AHB to APB Bridge, System-on-Chip (SoC), APB transactions [1], [2]. The bridge ensures synchronization
Advanced High-performance Bus (AHB), Advanced Peripheral across different clock domains, preventing timing issues and
Bus (APB), Clock Domain Synchronization, Transaction Conver- ensuring reliable data transfer [8]. By facilitating integration
sion, Data Transfer, Flow Control, Verilog, Xilinx Vivado, FPGA
with low-power APB peripherals, it supports efficient power
Simulation, Burst Transfers, Non-Pipelined Protocol, High-Speed
Communication, Low-Power Peripherals, Interface Design, Bus management, making it ideal for energy-sensitive applications
Protocol Integration, Functional Verification, Performance Eval- [5], [7]. Additionally, the bridge manages control signals
uation, Embedded System for flow control and error handling, ensuring data integrity
and preventing communication errors [4], [9]. This capability
I. I NTRODUCTION allows for a mix of high-performance and low-power com-
The AHB to APB Bridge is a vital element in System-on- ponents to coexist, supporting scalable, flexible designs for
Chip (SoC) architectures, facilitating efficient communication a wide range of applications, from consumer electronics to
between high-performance and low-power components. In automotive and industrial systems.
modern SoCs, the Advanced High-performance Bus (AHB)
is used for high-speed communication, connecting processors A. Motivation
and memory, while the Advanced Peripheral Bus (APB) caters
In modern SoC designs, the integration of high-performance
to lower-speed peripherals like timers, GPIOs, and UARTs.
processors and low-power peripheral devices is critical for
The AHB to APB Bridge ensures seamless integration by
achieving optimal performance and energy efficiency. Unlike
converting AHB’s complex, high-speed burst transactions into
conventional signaling techniques [10]–[17], AHB and APB
APB’s simpler, single-cycle transactions [1], [2].This bridge
operate on different protocols and speed requirements, which
also handles synchronization across clock domains and man-
can create challenges for direct communication [1], [2]. The
ages transaction flow, which is critical for bridging fast AHB
AHB to APB Bridge provides a solution by enabling seamless
masters with slower APB slaves [3]. By supporting this trans-
communication between these components without compro-
action flow and ensuring correct handshaking mechanisms,
mising data integrity or overall system performance [3].The
the AHB to APB bridge becomes indispensable for designing
development of this bridge facilitates flexible and scalable
scalable and power-efficient SoCs that balance performance
SoC designs, catering to applications ranging from mobile
and energy efficiency [4], [5].
devices to industrial systems [4], [7]. The motivation behind
G. Ananthu and R. Islam are with the Department of Computer Science this project is to bridge the communication gap between high-
and Electrical Engineering, University of Maryland, Baltimore County, MD speed and low-power components, thereby advancing efficient
21250, USA e-mail: [email protected].
and versatile SoC designs [8], [18]–[24]. Building this design
on the reconfigurable design can help the researchers to use
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 2

this design in there research to communicate between the Integrated AHB to APB Bridge using the Raspberry pi and Artix-7 FPGA

components. Reset_n

Hclk

Hreadyout
Prdata [31:0]

B. Contributions SCLK
cs_n
data_from_slave
haddr [31:0]
Hresp[1:0]

Penableout
data_to_slave
mosi Pwriteout
hwdata[31:0] Mapper2
Raspberry Pi SPI_Slave Mapper1 Bridge_top

This project employs an efficient design to transmit input miso htrans[1:0]

Pselxout[2:0]

Paddrout[31:0]
start_transaction data_from_mapper
Text

signals from a Raspberry Pi to an Artix-7 FPGA using an SPI hreadyin

hwrite
Pwdataout[31:0]

Hrdata[31:0]

interface. The Raspberry Pi sequentially sends serialized input Text

signals bit by bit over SPI, which are then decoded into parallel Fig. 1. Integrated AHB to APB Bridge using the Raspberry pi and Artix-7.
inputs by the FPGA [25]. A Finite State Machine (FSM) gen-
erates control signals for multiplexers and demultiplexers on
the FPGA to ensure proper routing and synchronization of data [5]. Additionally, in networking, the bridge connects pro-
[3]. The multiplexer directs SPI Slave outputs to the FPGA’s cessors with Ethernet controllers and management interfaces,
processing modules, while the demultiplexer gathers inputs for ensuring data flow in routers and switches [29]. Overall, the
hardware logic [9]. The processed outputs from the FPGA are bridge is fundamental to integrating high-performance proces-
sent back through the SPI interface to the Raspberry Pi for sors with diverse peripherals, supporting efficient, scalable,
validation and visualization. Python scripts on the Raspberry and power-optimized designs.
Pi manage SPI communication, data encoding, and output The AHB to APB Bridge plays a critical role in proto-
analysis, ensuring seamless integration [26]. This methodology col translation, converting AHB’s complex burst-mode and
optimizes pin usage on the FPGA through serialization and pipelined operations into APB’s non-pipelined, single-cycle
provides robust synchronization, enabling efficient processing transactions [3]. This bridge also resolves clock domain
and communication [8]. mismatches since the AHB operates at higher frequencies
for performance-critical tasks, while the APB runs at lower
II. BACKGROUND frequencies to save power [5]. By handling address decoding,
The AHB to APB Bridge is a component in SoC archi- control signal generation, and transaction synchronization, the
tectures that enables communication between the high-speed bridge enables the smooth integration of low-speed peripher-
[27]AHB and the low-speed APB . It acts as an interface, als with high-speed AHB components [29]. This integration
converting complex AHB transactions into simpler APB trans- ensures power efficiency, scalability, and modularity in SoC
actions, allowing high-performance components like CPUs designs, making the AHB to APB Bridge a critical enabler
and memory to interact seamlessly with low-power peripheral for applications ranging from embedded systems and mobile
devices, such as UARTs and GPIOs, within a single SoC devices to industrial automation and automotive electronics
The AHB to APB Bridge is a fundamental component in
modern SoC architectures, enabling seamless communication III. P ROPOSED M ETHODOLOGY
between high-performance and low-power subsystems [1], [2]. The AHB to APB Bridge using the Raspberry Pi and Artix-
The AMBA standard, developed by ARM, defines both AHB 7 FPGA is designed to facilitate seamless communication
and APB protocols to address the growing demands for high- between high-speed AHB components and low-power APB
speed processing and efficient peripheral management. The peripherals. The project integrates data transfer, processing,
AHB, as a high-bandwidth bus, supports burst-mode transfers, and protocol conversion using various functional modules. The
pipelined operations, and multi-cycle data processing, making system uses SPI communication for data transmission between
it ideal for connecting high-speed components such as proces- the Raspberry Pi and FPGA. The following subsections de-
sors, memory controllers, and DMA engines [4]. Conversely, scribe the architecture and the signals involved in this design
the APB is designed for simplicity, offering single-cycle, low- [8].
power transactions to efficiently interface with peripherals
such as GPIOs, timers, UARTs, and sensors [26].
The AHB to APB Bridge is widely deployed in diverse A. System Architecture and Module Breakdown
applications requiring efficient communication between high- Figure 1(a) The figure illustrates the architecture of the
speed processors and low-speed peripherals in SoCs. In em- AHB to APB Bridge, showcasing the flow of signals between
bedded systems, it supports communication between process- the Raspberry Pi, SPI Slave module, Mapper modules, and
ing cores and peripherals like sensors and timers, making it the Bridge top. The design highlights the systematic protocol
essential for microcontrollers and development boards . In conversion process for seamless communication between high-
consumer electronics, the bridge connects fast processors to speed and low-power components.
audio controllers, display drivers, and I/O interfaces, enabling The project architecture consists of five key modules: Rasp-
efficient operation in devices like smartphones and smart berry Pi(Master Device), SPI Slave(Data Reception Module),
home systems . In automotive systems, it facilitates interaction Mapper1(Signal Mapping Module), BridgeTop(AHB to APB
between CPUs and control units, powering applications like Conversion Module).
infotainment and engine management [7], [28]. In industrial 1) Raspberry Pi: The Raspberry Pi acts as the master de-
automation, it links high-speed controllers with sensors and ac- vice, generating the 100-bit wide input data.The input signals
tuators, ensuring precise control in manufacturing and robotics are serialized and sent to the FPGA via the MOSI line using
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 3

SPI communication.The Raspberry Pi also receives processed to be used by the subsequent module. [40]It also pipelines
output data bit by bit through the MISO line for validation AHB addresses and data to ensure smooth handling of read
and visualization. and write operations [1].
2) SPI slave: This module receives serialized data (100 2) APB FSM Controller: The APB FSM Controller is
bits) from the Raspberry Pi over the SPI [30] interface. [31]It responsible for managing APB transactions. It receives control
handles data reception, synchronization and outputs a start signals like Hwritereg and Valid from the AHB Slave Interface
transaction signal to trigger further processing. [32] [30] [33] and generates APB control signals such as Pwrite, Penable,
It sends the received 1 bit data sequentially to Mapper1 and and Pselx. Using a FSM, it orchestrates the flow of read and
outputs control signals such as start transaction to indicate write operations, ensuring proper handshaking between the
valid data reception [25] [34]. AHB and APB domains [2].
3) Mapper1: The Mapper1 module takes the 1-bit input 3) APB Interface: The APB Interface generates APB-
from the SPI Slave and assembles it into parallel 100-bit data. compatible signals required to communicate with APB periph-
[35] It maps sections of this 100-bit data to specific AHB- erals. It outputs Pwriteout, Penableout, Pselxout, Pwdataout,
compatible signals: prdata, haddr, hwdata, htrans, hreadyin, and Paddrout, which are sent to the selected APB peripheral.
and hwrite. These outputs are sent to the Bridge top module Additionally, it manages transaction completion using Hready-
for further processing [8]. out and generates response signals like Hresp to communicate
4) Bridge Top: This module forms the core of the project back with the AHB master [26].
and handles protocol conversion between AHB and APB. It
processes the AHB-compatible signals from Mapper1, con-
C. Signal Description and Operations
verts them into APB-compatible control signals, and man-
ages read/write operations. Outputs include APB signals like Each module in the system communicates using well-
Pwriteout, Penableout, Pselxout, Pwdataout, and Paddrout [8]. defined signals to ensure synchronized and robust operation.
5) Mapper2: The Mapper2 module gathers outputs from Below is a detailed explanation of the signals and their roles:
the Bridge top module, including APB signals, response flags,
and status bits. These signals are aggregated into a 104-bit data 1) SPI slave signals: Inputs for the SPI Slave are clk,
output and sent back to the Raspberry Pi, one bit at a time, resetn, mosi, sclk, and csn. Outputs from the SPI Slave
using the MISO line. This output ensures that the Raspberry include miso, starttransaction, and data to Mapper1. The SPI
Pi receives all processed information for verification Slave uses the SPI clock (sclk) to sample input data (mosi)
bit by bit. [41] Once the 100 bits are received, it triggers
the starttransaction signal and sends the data sequentially to
B. AHB to APB Bridge Architecture
Mapper1 [25].
The Bridge Top Architecture serves as the core module for 2) Mapper1 Signals: Inputs for Mapper1 are clk, resetn,
converting AHB signals into APB-compatible signals. [36] and data from Slave. Outputs from Mapper1 include Prdata,
[37] It consists of three key interconnected modules: AHB Haddr, Hwdata, Htrans, Hreadyin, and Hwrite. The Mapper1
Slave Interface, APB FSM Controller, and APB Interface. module accumulates 100-bit data from the SPI Slave and
[38]The architecture ensures protocol conversion, [39] control maps sections of this data into AHB-compatible signals. These
signal management, and proper synchronization between high- signals are sent to the Bridge Top module to initiate AHB
speed AHB and low-power APB domains [1], [2]. transactions [3].
The Bridge Top Architecture consists of three key modules. 3) BridgeTopSignals: Inputs of BridgeTopSignals are
They are AHB slave Interface , APB FSM Controller,APB Haddr, Hwdata, Htrans, Hreadyin, Hwrite.And the outputs of
Interface the Bridge is Pwriteout, Penableout, Pselxout, Pwdataout, Pad-
CLK
drout.The Bridge top module converts AHB protocol signals
reset
into APB protocol signals. It generates the necessary control
Hwrite
signals (Pwriteout, Penableout) and routes the address/data to
Hwrite
[31:0] Haddr1
Pwriteout
the appropriate APB peripheral. [1].
Hreadyin

[1:0] Htrans
[31:0] Haddr2

[31:0] Hwdata1
Pwrite

Penable
Penableout
4) Mapper2Signals: Inputs of Mapper2 are Pwriteout, Pen-
APB_Interface

[31:0] Haddr
AHB_Slave_Interface [31:0] Hwdata2

Hwritereg
APB_FSM_Controller
[2:0] Pselx

[31:0] Paddr
Pselxout[2:0]

ableout, Pselxout, Pwdataout, Paddrout. Outputs of the module

[31:0] Hwdata
[31:0] Prdata [2:0] tempselx
Valid
[31:0] Pwdata
Pwdataout[31:0]

Paddrout[31:0]
is data to slave.Mapper2 combines APB outputs into a 104-
Hreadyout bit data structure. This data is serialized and sent bit by bit to
[1:0] Hresp
the Raspberry Pi via the MISO line. [9]
5) AHB Slave Interface Signals: Inputs of the AHB Slave
Fig. 2. AHB to APB Bridge. Interface are clk, reset, Haddr, Hwdata, Htrans, Hwrite,
Hreadyin, and Prdata. Outputs of the module include Haddr1,
1) AHB Slave Interface: The AHB Slave Interface acts Haddr2, Hwdata1, Hwdata2, Hwritereg, and tempselx [1].
as the AHB slave module. It receives AHB signals such as 6) APB FSM Controller Signals: Inputs of the APB FSM
Haddr, Hwrite, Hreadyin, Htrans, and Hwdata from the AHB Controller are Hwritereg, Valid, Haddr1, Hwdata1, Haddr2,
master. It processes these inputs, validates the transaction, and Hwdata2, and tempselx. Outputs of the module include Pwrite,
generates control signals like Hwritereg, Valid, and tempselx Penable, Pselx, Paddr, and Pwdata [2].
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 4

[2]. Initially, the system is in an idle state, with clk running

Hreset_n Valid = 1 and
Hwrite = 1 continuously and reset de-asserted. The AHB interface begins
Valid = 0
a transaction when Htrans transitions to Non-sequential (value
ST_IDLE ST_WWAIT

Valid = 1 and
3), indicating a valid transfer. During this phase, the AHB
HWRITE = 1

Valid = 1 and
HWRITE = 0
Valid = 0 Valid = 1
address (Haddr) is updated to 0x8000000C and 0x80000008,
Valid = 0
ST_WRITE
ST_WRITEP
and write data (Hwdata) holds values like 0xFFFFFFFF.
ST_READ Valid = 1
Fig.4 presents the simulation results of the Finite State
Valid = 0
Valid = 0
and
HwriteReg = 1
Valid = 1 and
HwiteReg = 1 Machine (FSM) for the BridgeTop module, demonstrating
Valid = 1 and
HWRITE = 0
Valid = 1 and
WRITE = 0
Valid = 1 and
HWRITE = 1
signal transitions during its functional operation. The clock
HwriteReg = 0
ST_WENABLEP
signal (Hclk) serves as the timing reference, generating a
ST_RENABLE ST_WENABLE
stable periodic waveform that drives synchronous events. At
the start of the simulation, the reset signal (Hresetn) is asserted
low and later de-asserted high, releasing the FSM from reset
and initiating its normal operation. The valid signal asserts
high, indicating that valid data is being transmitted. The
input address bus (Haddr[31:0]) transitions to 0x12345678
Fig. 3. Finite State Machine. and 0x56781234, denoting address values sent during specific
clock cycles, while the write data bus (Hwdata[31:0]) carries
7) APB Interface Signals: Inputs of the APB Interface are the value 0x87654321 during write operations. The Hwrite
Pwrite, Penable, Pselx, Paddr, and Pwdata. Outputs of the signal, initially low, toggles high to indicate an active write
module include Pwriteout, Penableout, Pselxout, Pwdataout, operation. Similarly, the tempselx[2:0] signal transitions from
Paddrout, Hreadyout, and Hresp. [2] 0 to 1 and later to 2, showcasing the selection of different
states or modules during the FSM operation. The Pwrite and
IV. E XPERIMENTS AND R ESULTS Penable signals are asserted high, signaling the enablement
A. Experimental Setup of peripheral write operations in the APB interface. The
simulation results validate the proper operation of the FSM,
The experimental setup for the implementation of the AHB including synchronized state transitions, address decoding, and
to APB bridge consists of the Artix-7 100TCSG324 FPGA data transfer between the AHB and APB [40] domains. The
[29] and Raspberry Pi 4 Model B [42]. Similar to conventional waveforms confirm accurate signal generation and control,
approaches [43]–[45], the FPGA serves as the processing ensuring seamless communication between the system com-
platform for the implementation of the bridge, hosting Ver- ponents.
ilog modules for SPI communication, data mapping, protocol
Fig.5 presents the simulation results for the AHB to APB
conversion, and signal aggregation. The Raspberry Pi acts as
Bridge, demonstrating the correct operation of the bridge dur-
the master device, transmitting serialized 100-bit input data
ing read and write transactions. The clock signal (clk) remains
to the FPGA [34] via the SPI interface and receiving the
stable with a periodic waveform, ensuring synchronization
processed 104-bit output bit by bit. The design is developed,
across the design. The reset signal (resetn) is asserted initially
simulated, and implemented using the Xilinx Vivado Design
and de-asserted after stabilization, enabling normal operation
Suite [5], which facilitates RTL coding, behavioral simulation,
of the system. The Hwrite signal is set to 1, indicating a write
and hardware synthesis. Additionally, Python scripts running
operation, while Hreadyin remains asserted, signaling that the
on the Raspberry Pi manage SPI communication, including
AHB master is ready to initiate transactions. The Htrans[1:0]
data serialization, transmission, and output validation.To op-
value changes to 3 during the valid phase, representing a
timize and evaluate the design for area, power, and timing,
non-sequential transfer. The Haddr[31:0] signal outputs the
the Synopsys Design Compiler (DC) is utilized for synthesis,
address 0x8000000C, which is captured and routed through the
providing detailed reports on gate-level netlist area, power
AHB interface. Concurrently, Hwdata[31:0] carries the data
consumption, and timing delays. Post-synthesis analysis en-
sures that the bridge meets the required timing constraints
and achieves efficient resource utilization. The Synopsys IC
Compiler II (ICC2) is used for physical implementation,
enabling place-and-route operations while refining the design
for reduced power and optimized area. Together, the Vivado,
Design Compiler, and ICC2 tool chains provide a comprehen-
sive framework for RTL-to-GDSII implementation, ensuring
synchronized communication, efficient hardware processing,
and accurate verification of bridge functionality.

B. Experimental Results
The waveform for the Bridge Top module illustrates the Fig. 4. Simulation result for APB FSM Controller shows the output signals
communication between the AHB and APB interfaces [1], Pwrite,Penable high after the Hwrite and Valid goes high.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 5

firming the translation of the AHB signals into the APB

domain. Penableout is asserted, enabling the APB transfer,
while Pwriteout remains 1, indicating a write operation. The
Prdata[31:0] signal outputs the value 56781234 at a later stage,
signifying the readback or response data from the peripheral.
The data transfer completes successfully with synchronization
between the AHB and APB signals, as indicated by the stable
Hresp[1:0] signal. Figure 7 presents the simulation waveform
of the top module interfacing an SPI master and FPGA
hardware. The clk remains low initially, transitioning to an
Fig. 5. Simulation result for AHB to APB. active state as the simulation progresses. The mosi (Master Out
Slave In) and miso (Master In Slave Out) signals demonstrate
the serialized SPI communication, where the sclk (SPI clock)
0xFFFFFFFF, representing the write data being transmitted to ensures proper synchronization. The csn (chip select) signal
the APB slave. The APB side reflects this transaction with the toggles appropriately to enable data transfer. The test data
Paddrout[31:0] showing the address 0x8000000C, confirming input (testdata[99:0]) is transmitted in multiple chunks, starting
correct address decoding. Additionally, the Pwriteout signal with the 100-bit value 48000000CFFFFFFFFF56781234. The
asserts 1, validating the ongoing write transaction, and Pen- corresponding 32-bit index (I[31:0]) increments and outputs
ableout is asserted, completing the APB transfer phase. During 00000064, validating the received data. The successful hand-
the read cycle, Prdata[31:0] carries the data 0x56781234, shake between the SPI master and the FPGA [30], [33] is
signifying successful data retrieval from the APB slave. The evident from the signal transitions, with the startt action
Hresp[1:0] signal remains 0, indicating no errors occurred signal indicating the initiation of data capture and processing.
during the communication. The Pselxout[2:0] [40] reflects These results confirm the correct functionality of the AHB
appropriate slave selection values as 1, ensuring correct routing to APB Bridge and SPI interface, demonstrating reliable data
to the intended APB peripheral. This simulation waveform transfer, signal routing, and synchronization across different
confirms the bridge’s proper operation, including accurate pro- domains. This verification ensures the design’s robustness for
tocol conversion, address mapping, and data transfer between practical implementation.
the AHB master and APB slave. Both read and write trans-
actions are successfully synchronized, validating the seamless TABLE I
communication enabled by the bridge. R ASPBERRY PI I NPUT AND FPGA O UTPUT

Input to FPGA (From Raspberry Pi) Output From FPGA

Prdata (Hex, 31:0): 0x12345678 Hrdata (31:0): 0x12345678
Haddr (Hex, e.g., 0x8C000000): 0x8C000000 Paddr (31:0): 0x8C000000
Hwdata (Hex, 0x87654321): 0x87654321 Pwdata (31:0): 0x87654321
Htrans[1:0] (Binary, e.g., 10): 10 Pselx (2:0): 0101
Hreadyin[0] (Binary, e.g., 1): 1 Hresp (1:0): 0b10
Hwrite[1] (Binary, e.g., 1): 1 Hreadyout: 1
- Pwrite: 1
- Penable: 1

Table I illustrates the interaction between the Raspberry

Pi and FPGA by detailing the input signals sent to the
FPGA and the corresponding output signals generated. On
the input side, the Raspberry Pi sends the Prdata value of
0x12345678, representing the read data, and an Haddr sig-
Fig. 6. Simulation result for Integrated AHB to APB Bridge
nal of 0x8C000000, which specifies the AHB bus address.
Additionally, Hwdata (0x87654321) is provided as write data.
Figure 6 illustrates the simulation results for the AHB to The Htrans[1:0] signal is set to 10, indicating a non-sequential
APB Bridge, showcasing signal transitions and the interaction transfer, while Hreadyin[0] is asserted as 1, confirming the
between AHB and APB buses. The clock (clk) remains active slave’s readiness. The Hwrite[1] signal, also set to 1, specifies
throughout the simulation, ensuring synchronous operation. that a write operation is occurring. [46] On the output side,
The reset signal (resetn) is asserted initially to initialize the FPGA responds with Hrdata (0x12345678), matching the
the system and is subsequently deasserted to begin normal expected read data. The Paddr signal is output as 0x8C000000,
operation. The Hwrite signal indicates a write operation, while representing the address sent to the APB bus. Similarly, the
the Hreadyin signal is asserted, enabling the transfer process. Pwdata value of 0x87654321 is forwarded as the write data to
The AHB transaction begins with the Haddr signal set to the APB peripheral. The Pselx[2:0] signal is asserted as 0101,
8000000C and Hwdata carrying the value FFFFFFFF. Concur- indicating the active APB peripheral, while Hresp[1:0] is set
rently, Htrans[1:0] is toggled to 3, signaling a non-sequential to 0b10, signaling an error response condition. Additionally,
transfer. The Paddrout[31:0] and Pselxout[2:0] signals reflect the Pwrite signal is asserted as 1, confirming the APB write
the APB address and selection outputs, respectively, con- operation, and the Penable signal is activated as 1, enabling
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 6

TABLE II
S YNTHESIS A REA R EPORT FOR B R I D G E _T O P DESIGN .

Parameter Value
Number of ports 206
Number of nets 453
Number of cells 352
Number of combinational cells 114
Number of sequential cells 238
Number of macros/black boxes 0
Number of buf/inv 26
Number of references 19
Combinational area (units) 54.612001
Buf/Inv area (units) 6.482400
Noncombinational area (units) 253.612809
Macro/Black Box area (units) 0.000000
Net Interconnect area (units) 477.019164
Total cell area (units) 308.224810
Total area (units) 785.243974

TABLE III
P OWER A NALYSIS R EPORT FOR B R I D G E _T O P DESIGN .

Power Group Internal Power (uW) Switching Power (uW) Leakage Power (pW) Total Power (uW) % Contribution
io pad 0.0000 0.0000 0.0000 0.0000 0.00%
memory 0.0000 0.0000 0.0000 0.0000 0.00%
black box 0.0000 0.0000 0.0000 0.0000 0.00%
clock network 0.0000 0.0000 0.0000 0.0000 0.00%
register 334.8159 1.8795 7.1027e+04 336.7664 97.70%
sequential 0.0000 0.0000 0.0000 0.0000 0.00%
combinational 0.8345 7.0921 1.4948e+04 7.9415 2.30%
Total 335.6504 8.9716 8.5975e+04 344.7079 100.00%

the peripheral transaction. consume an additional 6.482400 units, showcasing their [38]
The Synthesis Area Report [47] for the BridgeTop design role in enhancing signal strength and stability.A significant
in Table II provides a detailed breakdown of resource uti- portion of the design area, 477.019164 units, is allocated to net
lization post-synthesis and place-and-route, highlighting the interconnects, emphasizing the complexity of routing signals
area contributions of combinational, sequential, and inter- between the logic components. Efficient routing strategies
connect components. The design, synthesized using Design are critical to reducing delay and ensuring optimal design
Compiler (DC) and implemented with IC Compiler II (ICC2), performance.The total cell area sums up to 308.224810 units,
achieves optimized area usage while maintaining a balance representing the combined space consumed by all active logic
between logic and routing resources.The BridgeTop module and sequential [46] components. The overall total area of the
consists of 206 ports serving as input and output connections, design, including interconnects and cell resources, amounts
enabling seamless interfacing with external components or to 785.243974 units, reflecting the final physical footprint
systems. A total of 453 nets provide interconnections be- of the BridgeTop module.This area distribution highlights an
tween logic elements, ensuring efficient signal flow across efficient and balanced design, where interconnect routing and
the design. The design incorporates 352 cells, which include sequential components [49]contribute significantly to the over-
both combinational and sequential elements.Out of the total all area. Such optimization is crucial for achieving scalability
cells, 114 combinational cells are dedicated to implementing and integration in modern SoC architectures, particularly in
purely logical operations such as AND, OR, and XOR gates. applications requiring a mix of high-performance and low-
These cells perform critical combinational tasks without any power operations. This breakdown ensures that the BridgeTop
memory elements. The design also [48] integrates 238 se- module is area-efficient and ready for further implementation
quential cells, including flip-flops and registers, which serve in advanced hardware systems.
to store and synchronize data with the clock signal, making Table III in the report presents the Power Analysis Re-
them vital for maintaining state and timing consistency in port for the BridgeTop design, detailing the contributions
the module.The 26 buffers/inverters included in the design of internal, switching, and leakage power across various
help maintain signal integrity by amplifying signals over power groups. The register group dominates the total power
[49] long interconnects and inverting signals where necessary. consumption, accounting for 97.70 of the total power with
These components ensure reliable data propagation across the 334.8159 µW of internal power and a minimal switching
module.The Combinational area occupies 54.612001 units, power of 1.8795 µW. Leakage power within registers con-
reflecting the space utilized by purely logical gates. In contrast, tributes 7.1027e+04 pW (approximately 71.027 nW), indi-
the Noncombinational area contributes a larger footprint of cating the importance of optimizing register usage [38] to
253.612809 units, highlighting the area occupied by sequential minimize power dissipation. The combinational group con-
elements such as flip-flops and registers. Buffers and inverters tributes a total of 7.9415 µW, which is 2.30 of the overall
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 7

TABLE IV
T IMING R EPORT FOR B R I D G E _T O P D ESIGN .

Parameter Description Incremental Delay (ns) Total Delay (ns)

Startpoint reset_n (input port) - -
Endpoint FSM_PRESENT_STATE_reg_1_ - -
Clock Source clk 0.00 0.00
Clock Network Delay (ideal) Ideal 0.00 0.00
Input External Delay Input Delay 0.10 0.10
U97/X Buffer (SAEDRVT14_BUF_S_0P75) 0.04 0.14
U127/X AND Gate (SAEDRVT14_AN3_0P5) 0.03 0.17
U130/X AND Gate (SAEDRVT14_AN3_0P5) 0.02 0.19
U102/X AND Gate (SAEDRVT14_AN3_0P5) 0.04 0.23
U202/X Inverter (SAEDRVT14_INV_0P5) 0.03 0.26
U206/X Complex Gate (SAEDRVT14_OAI22_0P5) 0.02 0.28
U207/X Complex Gate (SAEDRVT14_AO221_0P5) 0.02 0.30
Data Arrival Time From Start to Endpoint - 0.30
Clock Period Clock Cycle - 0.72
Clock Uncertainty Delay Variation -0.07 0.65
Library Setup Time Setup Margin -0.01 0.64
Data Required Time Total Required Time - 0.64
Slack (MET) Timing Margin - 0.34

power, comprising 0.8345 µW of internal power, 7.0921 µW the timing constraints without violations, ensuring reliable
of switching power, and 1.4948e+04 pW of leakage power. operation within the defined clock cycle. This analysis high-
Notably, power contributions from the iopad, memory, black- lights the incremental contributions of various components, the
box, clocknetwork, and sequential groups remain 0.00 µW, total delay accumulation, and the robustness of the design in
reflecting no activity or negligible power consumption for achieving the required timing performance.
these components in the analyzed scenario. The combined
switching power of 8.9716 µW highlights dynamic activ- V. C ONCLUSION
ity within combinational and register components, whereas
leakage power across all components totals 8.5975e+04 pW The implementation of the AHB to APB Bridge using
(approximately 85.975 nW). The total power dissipation for the Artix-7 FPGA [50] and Raspberry Pi 4 Model B [46]
the BridgeTop design is 344.7079 µW, with internal power successfully demonstrates seamless communication between
being the dominant factor, followed by smaller contributions high-speed AHB components and low-power APB peripherals.
from switching and leakage power. This analysis highlights The system leverages SPI communication for data transfer and
the significant role of registers and combinational logic in the employs Verilog modules for protocol conversion, enabling
design’s overall energy profile. efficient mapping of AHB signals to APB-compatible outputs.
The Xilinx Vivado Design Suite facilitates design, behavioral
The Timing Report for the BridgeTop Design (Table IV) simulation, and initial synthesis, ensuring functional correct-
provides a detailed breakdown of the signal propagation ness and optimization for FPGA hardware. Additionally, the
from the startpoint resetn (input port) to the endpoint FSM Synopsys DC Compiler is utilized for gate-level synthesis,
PRESENT STATE reg1 (a flip-flop). The timing path is driven providing detailed analysis and optimization of area, power,
by the clk clock source, with the clock network delay treated as [39] and timing. This step ensures that the design adheres
ideal (0.00 ns). An input external delay of 0.10 ns is introduced to timing constraints while achieving resource-efficient imple-
for resetn, modeling the signal arrival relative to the clock mentation. Python scripts running on the Raspberry Pi manage
edge. The path includes incremental delays contributed by the SPI interface for reliable data serialization, transmission,
various gates, starting with a buffer (U97/X) that adds 0.04 and validation, ensuring synchronization with the FPGA.
ns, followed by AND gates (U127/X, U130/X, and U102/X) Overall, the combined use of Vivado, Design Compiler, and
with delays ranging from 0.03 ns to 0.04 ns, and an inverter SPI-based communication establishes a robust, scalable, and
(U202/X) contributing 0.03 ns. Two complex gates, U206/X power-efficient solution for bridging high-performance AHB
(OAI22) and U207/X (AO221), add incremental delays of 0.02 subsystems with low-power APB peripherals, showcasing its
ns each, bringing the total data arrival time to 0.30 ns.The practicality and relevance in modern SoC designs.
clock period is 0.72 ns, and a clock uncertainty of -0.07 ns
accounts for variations such as jitter or skew, reducing the R EFERENCES
available timing margin. Additionally, a library setup time of
-0.01 ns is defined for the flip-flop. As a result, the data [1] A. Limited, “AMBA 3 AHB-Lite Protocol Specification,” 2010, online.
Available: www.developer.arm.com.
required time is calculated as 0.64 ns, with a final slack of [2] ——, “AMBA APB Protocol Specification,” 2010, online. Available:
0.34 ns. The positive slack confirms that the design meets www.developer.arm.com.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I 8

[3] B. Wolf and J. Scheffler, “Efficient Communication Bridge Between [30] A. Das and S. Chatterjee, “SPI-Based Data Communication Between
AMBA Buses in SoC Design,” IEEE Transactions on Circuits and Raspberry Pi and FPGA,” in 2021 IEEE International Conference on
Systems I, vol. 62, no. 3, pp. 123–135, March 2015. Advances in Computing, Communication, and Control (ICAC3), 2021,
[4] D. A. Patterson and J. L. Hennessy, Computer Organization and Design: pp. 351–356.
The Hardware/Software Interface, 5th ed. Morgan Kaufmann, 2014. [31] K. Reddy and H. Rao, “FPGA-Based Implementation of AHB to
[5] Xilinx, “Vivado Design Suite User Guide,” 2022, uG910 (v2022.2), APB Bridge Using Verilog HDL,” International Journal of Advanced
Online. Available: https://www.xilinx.com. Research in Electronics and Communication Engineering, vol. 12, no. 6,
[6] R. Islam, B. Saha, and I. Bezzam, “Resonant energy recycling sram pp. 290–295, 2023.
architecture,” IEEE Transactions on Circuits and Systems II: Express [32] A. Nayak and D. Prasad, “FPGA Implementation of AHB to APB
Briefs, vol. 68, no. 4, pp. 1383–1387, 2020. Bridge for Low Power SoCs,” in 2019 IEEE International Conference on
[7] Xilinx, “7 Series FPGAs Overview,” 2020, xilinx Datasheet, DS180 Electronics, Communication and Aerospace Technology (ICECA), 2019,
(v2.6). pp. 1169–1173.
[8] R. Saini and R. Islam, “Reconfigurable CAN Intrusion Detection and [33] L. Chen and Q. Liu, “Raspberry Pi to FPGA Communication Using
Response System,” MDPI Electronics, vol. 13, no. 13, p. 2672, 2024. SPI for Data Transfer Applications,” Journal of Embedded Systems and
[9] D. Harris and S. Harris, Digital Design and Computer Architecture, Applications, vol. 17, no. 3, pp. 123–129, 2023.
2nd ed. Morgan Kaufmann, 2012. [34] V. Sharma and R. Kumar, “Signal Processing and Timing Optimization
[10] R. Islam and M. R. Guthaus, “HCDN: Hybrid-mode clock distribution of AHB to APB Bridge on Artix-7 FPGA,” International Journal of
networks,” IEEE Transactions on Circuits and Systems I: Regular Engineering and Technology Innovation, vol. 14, no. 1, pp. 45–53, 2022.
Papers, vol. 66, no. 1, pp. 251–262, 2018. [35] A. Saxena and H. Kumar, “Low-Power AHB to APB Bridge Design for
[11] R. Islam, “High-speed energy-efficient soft error tolerant flip-flops,” FPGA Applications,” in 2022 IEEE International Symposium on Circuits
Ph.D. dissertation, Concordia University, 2011. and Systems (ISCAS), 2022, pp. 1–4.
[12] R. Islam and M. R. Guthaus, “CMCS: Current-mode clock synthesis,” [36] Y. Gandhi, N. Patel, and M. Chauhan, “Design and Analysis of AMBA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, AHB to APB Bridge Using SystemVerilog,” in 2020 International
vol. 25, no. 3, pp. 1054–1062, 2016. Conference on Smart Electronics and Communication (ICOSEC), 2020,
[13] R. Islam, “High-speed on-chip signaling: Voltage or current-mode?” pp. 1050–1054.
IETE Journal of Research, vol. 67, no. 2, pp. 217–226, 2021. [37] R. Prasad and S. Kumar, “Efficient Power and Timing Optimization for
[14] R. Islam, H. A. Fahmy, P. Y. Lin, and M. R. Guthaus, “DCMCS: Highly AMBA AHB to APB Bridge,” Journal of Engineering Research and
robust low-power differential current-mode clocking and synthesis,” Applications, vol. 12, no. 4, pp. 15–19, 2021.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, [38] R. Mehta and K. Patel, “Area, Timing, and Power Optimization of
vol. 26, no. 10, pp. 2108–2117, 2018. AMBA AHB to APB Bridge Using Synopsys Tools,” Journal of VLSI
and Embedded Systems, vol. 15, no. 2, pp. 92–100, 2023.
[15] M. Guthaus and R. Islam, “Current-mode clock distribution,” Oct. 10
[39] M. Joshi and R. Verma, “ICC2-Based Physical Implementation and
2017, uS Patent 9,787,293.
Power Analysis of AHB to APB Bridge,” Journal of Semiconductor
[16] R. Islam, “Negative Capacitance Clock Distribution,” IEEE Transactions
Technology and Science, vol. 16, no. 4, pp. 45–52, 2021.
on Emerging Topics in Computing, vol. 9, no. 1, pp. 547–553, 2018.
[40] A. Kumar and A. Kumar, “Design and Implementation of AMBA AHB
[17] ——, “Low-power resonant clocking using soft error robust energy
to APB Bridge,” International Journal of VLSI Design & Communica-
recovery flip-flops,” Journal of Electronic Testing, vol. 34, no. 4, pp.
tion Systems, vol. 9, no. 1, pp. 11–21, 2018.
471–485, 2018.
[41] F. Khan and S. Ahmed, “AHB to APB Bridge Design with SPI Interface
[18] S. B. Rahi, “System-on-Chip Design with State-of-Art Transistors,” for Real-Time Applications,” in 2022 IEEE International Conference on
Handbook of Emerging Materials for Semiconductor Industry, p. 823, Embedded Systems and VLSI Design (ESVD), 2022, pp. 187–191.
2024. [42] Raspberry Pi Foundation, “Raspberry Pi 4 Model B Datasheet,”
[19] R. Islam, “Early Stage DRC Prediction Using Ensemble Machine Learn- 2023, Available: https://datasheets.raspberrypi.com/rpi4/
ing Algorithms,” IEEE Canadian Journal of Electrical and Computer raspberry-pi-4-datasheet.pdf.
Engineering, vol. 45, no. 4, pp. 354–364, 2022. [43] R. Saini and R. Islam, “Reconfigurable can intrusion detection and
[20] L. Guo, A. Weiße, S. M. A. Zeinolabedin, F. M. Schüffny, M. Stolba, response system,” Electronics, vol. 13, no. 13, p. 2672, 2024.
Q. Ma, Z. Wang, S. Scholze, A. Dixius, M. Berthel et al., “68- [44] B. Croteau, K. Kiriakidis, T. A. Severson, R. Robucci, S. Rahman, and
channel neural signal processing system-on-chip with integrated feature R. Islam, “State estimation adaptable to cyberattack using a hardware
extraction, compression, and hardware accelerators for neuroprosthetics programmable bank of kalman filters,” IEEE Transactions on Control
in 22 nm FDSOI,” Frontiers in Neuroscience, vol. 18, p. 1432750, 2024. Systems Technology, vol. 32, no. 5, pp. 1730–1742, 2024.
[21] J. Qiu, Z. Zhou, Y. Li, Z. Li, F. Qian, H. Lin, D. Gao, H. Su, X. Miao, [45] K. Kiriakidis, B. Croteau, T. Severson, E. Rodriguez-Seda, R. Robucci,
Y. Liu et al., “vSoC: Efficient Virtual System-on-Chip on Heterogeneous R. Islam, and S. Rahman, “Degradable tracking system based on
Hardware,” in Proceedings of the ACM SIGOPS 30th Symposium on hardware multi-model estimators,” in 2022 Resilience Week (RWS),
Operating Systems Principles, 2024, pp. 558–573. 2022, pp. 1–6.
[22] J. P. Smith, J. I. Bailey, A. Cuda, N. Zobrist, and B. A. Mazin, [46] A. Narasimha and M. Patel, “Efficient Signal Transfer Between Rasp-
“MKIDGen3: Energy-resolving, single-photon-counting microwave ki- berry Pi and Artix-7 FPGA Using SPI and AHB/APB Bridge,” Interna-
netic inductance detector readout on a radio frequency system-on-chip,” tional Journal of Computer and Communication Systems, vol. 19, no. 4,
Review of Scientific Instruments, vol. 95, no. 11, 2024. pp. 134–141, 2023.
[23] R. Islam, “Low-power highly reliable SET-induced dual-node upset- [47] S. Mahesh and P. Rao, “Area and Power Optimization of AMBA AHB
hardened latch and flip-flop,” Canadian Journal of Electrical and to APB Bridge Using Synopsys DC Compiler,” International Journal of
Computer Engineering, vol. 42, no. 2, pp. 93–101, 2019. VLSI Design, vol. 8, no. 2, pp. 40–47, 2023.
[24] ——, “Feasibility prediction for rapid IC design space exploration,” [48] A. Raj and N. Iyer, “Area and Power Optimized AMBA AHB to APB
Electronics, vol. 11, no. 7, p. 1161, 2022. Bridge Implementation on FPGA,” International Journal of VLSI Design
[25] M. S. Hossain and A. H. Alam, “Design and Implementation of SPI Pro- and Technology, vol. 20, no. 3, pp. 157–162, 2023.
tocol in FPGA,” International Journal of Engineering and Technology, [49] R. Sahoo and D. Patel, “Performance Evaluation of AMBA AHB to APB
vol. 3, no. 2, pp. 230–234, 2015. Bridge with Timing Optimization,” Journal of System Architecture, vol.
[26] R. P. Jain, Digital Electronics: Principles, Devices, and Applications, 126, p. 102537, 2022.
3rd ed. McGraw-Hill Education, 2010. [50] A. Shukla and R. Singh, “Efficient SPI Communication Between Rasp-
[27] M. Ali and A. Thomas, “Design and Implementation of AHB to berry Pi and Artix-7 FPGA for Real-Time Data Transfer,” International
APB Bridge with SPI Communication Using Raspberry Pi and Artix-7 Journal of Embedded Systems, vol. 18, no. 2, pp. 89–95, 2022.
FPGA,” in 2021 International Conference on Automation and Comput-
ing (ICAC), 2021, pp. 145–150.
[28] R. Tessier and W. Burleson, “Reconfigurable Computing for Digital
Signal Processing,” Proceedings of the IEEE, vol. 86, no. 4, pp. 723–
738, April 1998.
[29] S. M. Trimberger and J. J. Moore, “FPGA Technology for Digital
Systems Integration,” Proceedings of the IEEE, vol. 103, no. 12, pp.
1938–1954, December 2015.