CSE 350
Digital Electronics and Pulse Techniques
Analog to Digital Converter (ADC)
Course Instructor: Shomen Kundu (SDU) Mail: [email protected]
Desk: 4N166
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Analog to Digital Converter (ADC)
Signal can be classified into two broad categories.
i. Analog Signal ii. Digital Signal
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CSE 350
Analog to Digital Converter (ADC)
Physical world’s information are mostly analog. Analog means data could take
any real value at each instant of time.
In order to store/process we use digital data in our computers and
microprocessor
Digital data means binary bit of strings.
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4
A/D conversion process
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Sample and Hold Circuit
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Quantization:
Quantization is a process by which we assign sampled and hold signal sata to
some fixed preassigned values.
i. Midrise Quantization
ii. Midtread Quantization
𝑁 = 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑏𝑖𝑡𝑠
2𝑁 = 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑙𝑒𝑣𝑒𝑙𝑠
Vmax − 𝑉𝑚𝑖𝑛
Δ = resolution =
2𝑁
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Midrise Quantization:
Quantization Range Quantization Level
(−4∆, −3∆) −3.5 ∆
(−3∆, −2∆) −2.5 ∆
(−2∆, −∆) −1.5 ∆
(−∆, 0) −0.5 ∆
(0, ∆) 0.5 ∆
(∆, 2∆) 1.5 ∆
(2∆, 3∆) 2.5 ∆
(3∆, 4∆) 3.5 ∆
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Mid tread Quantization
( Not symmetrical and Equally Spaced)
Quantization Range Quantization Level
(−4∆, −2.5∆) −3 ∆
(−2.5∆, −1.5∆) −2 ∆
(−1.5∆, −0.5∆) −∆
(−0.5∆, 0.5Δ) 0
(0.5Δ, 1.5∆) ∆
(1.5∆, 2.5∆) 2∆
(2.5∆, 3.5∆) 3∆
(3.5∆, 4.5∆) 4∆
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Encoding
We can choose binary values for each of the level.
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑏𝑖𝑡𝑠 = 𝐶𝑒𝑖𝑙 (𝑙𝑜𝑔2 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑙𝑒𝑣𝑒𝑙𝑠 )
Assign lower Q level to 0
Then increase one for each next level
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Quantization Range, Level, code
Ex: Identify which one is Mid rise and Mid tread.
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Quantization Range, Level, code
Here,
𝑉𝑚𝑎𝑥 + 𝑉𝑚𝑖𝑛 8+0
= =4𝑉
2 2
As 4 V is a Quantization level. So it is a
mid tread quantization
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Quantization Range, Level, code
Ex: Identify which one is Mid rise and Mid tread.
Here,
𝑉𝑚𝑎𝑥 + 𝑉𝑚𝑖𝑛 10 + 0
= =5𝑉
2 2
As 5 V is a Quantization level. So it is a
mid rise quantization
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Flash A/D converter
Features of the Flash A/D converter
✓ This converter is very fast.
✓ It requires one clock cycle to convert the analog to digital data.
✓ It requires a lot components.
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Op-Amp
For open loop configuration
𝐼𝑓 𝑉+ > 𝑉− , 𝑉𝑜𝑢𝑡 = 𝐻𝑖𝑔ℎ (𝑙𝑜𝑔𝑖𝑐 1 )
𝐼𝑓 𝑉+ < 𝑉− , 𝑉𝑜𝑢𝑡 = 𝐿𝑜𝑤 (𝑙𝑜𝑔𝑖𝑐 0 )
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Flash ADC design
Suppose you have a signal with Vmax = 10 V and Vmin = 0V. Design a simple
flash ADC converter. Use 3 bits for designing.
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Flash ADC design
Suppose you have a signal with Vmax = 10 V and Vmin = 0V. Design a simple
flash ADC converter. Use 3 bits for designing. Provide your encoder truth
table.
Design:
Here,
𝑁=3
#𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑟𝑒𝑔𝑖𝑠𝑡𝑜𝑟 = 23 = 8
#𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑐𝑜𝑚𝑝𝑎𝑟𝑎𝑡𝑜𝑟 = 23 − 1 = 7
𝑉+𝑟𝑒𝑓 = 𝑉𝑚𝑎𝑥 = 10 𝑉
𝑉−𝑟𝑒𝑓 = 𝑉𝑚𝑖𝑛 = 0 𝑉
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Circuit
The following is the Circuit of a
3 bits Flash ADC,
V+ of the comparator is
connected to the input.
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Circuit Analysis
The following is the Circuit of a 3 bits Flash
ADC,
10 − 0 10
𝐼= =
8𝑅 8𝑅
𝑉1 − 𝑉−𝑟𝑒𝑓
𝐼=
𝑅
10
𝑉1 = 𝑉−𝑟𝑒𝑓 + 𝐼𝑅 = 0 + ∗ 𝑅 = 1.25 𝑉
8𝑅
𝑉2 −𝑉1
Similarly, 𝐼 = ⇒ 𝑉2 = 𝑉1 + 𝐼𝑅
𝑅
10
⇒ 𝑉2 = 1.25 + ∗ 𝑅 = 2.5 𝑉
8𝑅
You can find other voltage in this way.
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Circuit Analysis
Summary table:
Q Range Q level I7I6I5I4I3I2I1 Binary (B2B1B0)
0 - 1.25 0.675 000 000 0
1.25 - 2.5 1.875 000 000 1
2.5 - 3.75 3.125 000 001 1
3.75 – 5 4.375 000 011 1
5 – 6.25 5.625 000 111 1
6.25 – 7.5 6.875 001 111 1
7.5 – 8.75 8.125 011 111 1
8.75 - 10 9.375 111 111 1
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Circuit Analysis
Encoder Truth Table:
I7I6I5I4I3I2I1 Binary (B2B1B0)
( V+ of the comparator is connected to
the Input ) 000 000 0 000
000 000 1 001
Encoder can be implemented using
000 001 1 010
the combinational network. 000 011 1 011
000 111 1 100
001 111 1 101
011 111 1 110
111 111 1 111
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Circuit Analysis
Encoder Truth Table:
I7I6I5I4I3I2I1 Binary (B2B1B0)
( V- of the comparator is
connected to the Input ) 111 111 1 000
111 111 0 001
Encoder can be implemented using
111 110 0 010
the combinational network. 111 100 0 011
111 000 0 100
110 000 0 101
1 000 000 110
000 000 0 111
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Problem:
Make a table with Quantization
Range, Quantization Level and
Binary values for the given ADC
circuit.
What will be the final output if the
input voltage 𝑉𝐴 = 2.125 𝑉.
[ VREF = 12 V ]
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