COURSEPACK

FRAMEWORK

The Course Pack is a comprehensive and complete pedagogical guideline document that describes the components
of instruction delivery by a faculty member. It consists of the scheme of the course, Course Overview, Course
Objectives, Prerequisite course, Program-specific Outcomes (PSOs), Course outcomes (COs), Bloom’s taxonomy
(Knowledge Levels), Types of Courses, Course articulation matrix, Course assessment patterns, Course content,
Lesson Plan, Bibliography, Problem-based learning/case-studies/clinical, and Student-Centered learning (self-
learning towards life-long-learning). It not only provides a uniform design of Course delivery across the University
but also ensures freedom and flexibility to introduce innovations in learning and teaching and create vivid kinds of
assessment tools (alternate assessment tools) by a faculty member.
The course pack is developed by the faculty member teaching a course. If more than one faculty teaches the same
course, all the faculty members teaching the course shall be formed as a cluster, and a senior faculty member (Course-
lead) lead the Course delivery design in a team effort. The Course Pack provides ample scope and opportunity to
bring innovations in teaching pedagogies in a school/department.
Hence, the Course pack is a comprehensive learning-teaching strategy framework to be followed by all the faculty
members in schools/departments in the university. It is not only a tool for measuring the learning of a class but also
analyses the achievement levels (learning outcomes of the course) of all the students in a class in a continuous manner.

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1. THE SCHEME
The scheme is an overview of work-integrated learning opportunities and gets students out into the real world. This
will give what a course entails.
Course Title Computer Organization and Course Type Theory
Architecture
Course Code Class B.Tech. III Sem
E2UC301T Core and All
specialization
Activity Credit Credit Total Number of Assessmen
s Hours
Classes per t in
Lecture 4 4 Semester Weightage
Instruction

Tutorial
Theory
Tutorial 0 0

Practical
delivery

CIE
Practical 0 0

E
E
S
Self-Learning 0 0
Total 4 4 45 0 0 50% 50%
Course Lead: Dr. Brijesh Kumar Singh
Names of
Course Lead, Course
Course Coordinator: Mr. Dhirendra Siddharth
Instructors Theory Practical
Aanjey Mani Tripathi NA
Arun Kumar Rai
Balbindar Kaur
Brijesh Kumar Singh
Damodharan D.
Dhirendra Siddharth
Gurmeet Singh
Isha Chopra
Manish Verma
Minal Tandekar
Mukesh Kumar
Mullapudi Navyasri
Pragya Srivastava
Rajeev Kumar
Rati Bhan
Ruby Dahiya
Sandeep Bhatia
Savita Kumari
Sunil Kumar Chowdhary
Tarun Maini
Trapti Shrivastava
Vimal Singh

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 COURSEPACK
FRAMEWORK

2. COURSE OVERVIEW
Computer Organization and Architecture is a foundational course in computer science and engineering that explores
the internal structure and operational principles of computer systems. The course covers the key concepts and
components that make up a computer system, including hardware design, instruction set architecture, memory
hierarchy, input/output mechanisms, and performance optimization. Students will gain an understanding of how
software interacts with hardware to perform computations and execute programs efficiently

3. COURSE OBJECTIVES

This course aims to provide a comprehensive understanding of the fundamental principles of computer organization
and architecture. Students will learn about the design and function of major computer system components, such as
the CPU, memory, and I/O systems, and analyze system performance to explore optimization techniques. The course
also emphasizes the interaction between hardware and software in executing instructions, offering practical
experience with assembly language programming and hardware simulation tools. This knowledge equips students
with the skills needed for advanced studies and careers in hardware and software development.

4. PREREQUISITE COURSE

PREREQUISITE COURSE REQUIRED Yes

If, yes please fill in the details

Prerequisite course code Prerequisite course name

G2UC101B Introduction to Digital Systems

5. PROGRAM OUTCOMES (POs):

In general, the Program Outcomes are defined by the respective apex body or council. In the event the POs are not
prescribed by a Council, then the concerned school offering the program to design and develop the POs based on the
PEOs. This has to be approved by the concerned BOS and submitted to the Academic Council for approval. After
the completion of the course, the student will be able to:

PO Description of the Program Outcome

No.
PO1 Computing Science knowledge: Apply the knowledge of mathematics, statistics, computing science and
information science fundamentals to the solution of complex computer application problems.

PO2 Problem analysis: Identify, formulate, review research literature, and analyze complex computing science
problems reaching substantiated conclusions using first principles of mathematics, natural sciences, and
computer sciences.

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 PO3 Design/development of solutions: Design solutions for complex computing problems and design system
components or processes that meet the specified needs with appropriate consideration for the public health
and safety, and the cultural, societal, and environmental considerations.

PO4 Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to
provide valid conclusions.

PO5 Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern computing
science and IT tools including prediction and modeling to complex computing activities with an
understanding of the limitations.

PO6 IT specialist and society: Apply reasoning informed by the contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional
computing science and information science practice.

PO7 Environment and sustainability: Understand the impact of the professional computing science solutions
in societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable
development.

PO8 Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
computing science practice.

PO9 Individual and team work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.

PO10 Communication: Communicate effectively on complex engineering activities with the IT analyst
community and with society at large, such as, being able to comprehend and write effective reports and
design documentation, make effective presentations, and give and receive clear instructions.

PO11 Project management and finance: Demonstrate knowledge and understanding of the computing science
and management principles and apply these to one’s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.

PO12 Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent
and life-long learning in the broadest context of technological change.

6. PROGRAM SPECIFIC OUTCOMES (PSOs):

Program Specific Outcomes (PSO) are statements that describe what the graduates of a discipline-specific program should be
able to do. Two to Three PSOs per program should be designed.

PSO No. Description of the Program-Specific Outcome

PSO1 Have the ability to work with emerging technologies in computing requisite to Industry 4.0.

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PSO2 Demonstrate Engineering Practice learned through industry internship and research project to solve live problems
in various domains.

7. COURSE CONTENT (THEORY)

(Syllabus)

Module-1 Register Transfer and Micro-operations

Register Transfer Language, Register Transfer, Bus and Memory Transfers, Arithmetic Micro-operations, Logic
Micro-operations, Shift Micro-operations, Arithmetic logic shift unit
Module -2 Basic Computer Organizations and Design and CPU Organizations
Instruction Cycle, Memory-Reference Instructions, Register reference instructions, and Input - Output Instructions
Central Processing Unit: General Register Organization, Stack Organization, Instruction Formats, and Addressing
Modes
Module-3 Computer Arithmetic
Addition and Subtraction (Signed Magnitude and Signed 2’s Complement) , Multiplication Algorithms (Binary
Multiplication for Signed Magnitude and Booth’s Algorithm) , Division Algorithms (Restoring and Non-Restoring).
Module-4 Memory Organization
Memory Hierarchy, Main Memory, Auxiliary Memory, Associative Memory, Cache Memory, Virtual Memory,
Memory Management Hardware
Module-5 Input-Output Organization
Peripheral Devices, Input-Output Interfaces, Asynchronous Data Transfer, Modes of Transfer, Priority Interrupt, and
Direct Memory Access (DMA)

TEXT BOOKS:
1. Morris Mano, Computer System Architecture, 3rd Edition, Prentice-Hall of India Private Limited, 1999.

REFERENCE BOOKS:
1. Hayes, John P. Computer architecture and organization. McGraw-Hill, Inc., 2002.
2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky Computer Organization, McGraw-Hill, Fifth Edition,
Reprint 2012
3. William Stallings, Computer Organization and Architecture-Designing for Performance, Pearson
Education, Seventh edition, 2006

SWAYAM/NPTEL/MOOCs Certification
1. https://www.coursera.org/learn/comparch
2. https://nptel.ac.in/courses/106105163
3. https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/

: for internal circulation only : 6

8. COURSE OUTCOMES (COs)

After the completion of the course, the student will be able:

E2UC301T.1 To explain and classify the different types of register transfer and micro-operations.

E2UC301T.2 To analyze and compare different computer organizations and CPU components, including
instruction formats and addressing modes.

E2UC301T.3 To apply various computer arithmetic algorithms to solve complex problems.

To assess and design strategies for memory organization, including cache and virtual memory
E2UC301T.4 management.

E2UC301T.5 To evaluate and interpret the principles of input-output organization.

9. TAXONOMY LEVEL OF THE COURSE OUTCOMES

Bloom’s taxonomy is a set of hierarchical models used for the classification of educational learning objectives into
levels of complexity and specificity. The learning domains are cognitive, affective, and psychomotor.

Mapping of COs with Bloom’s Level

Remember Understand Apply Analyze Evaluate Create

CO No.
BTL1 BTL2 BTL3 BTL4 BTL5 BTL6
E2UC301T.1 √ √
E2UC301T.2 √ √ √
E2UC301T.3 √ √ √ √
E2UC301T.4 √ √ √ √ √
E2UC301T.5 √ √ √

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10. COURSE ARTICULATION MATRIX

The Course articulation matrix indicates the correlation between Course Outcomes and Program Outcomes and their
expected strength of mapping in three levels (low, medium and high).

PSO1

PSO2
PO10

PO11

PO12
PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9
COs/Pos

E2UC301T.1 3 3 2 - 2 - - 1 - - - - - -

E2UC301T.2 3 3 2 - - 2 - - - 1 - - - -

E2UC301T.3 3 3 2 - 2 - - 1 - - - - - -

E2UC301T.4 3 3 3 3 3 - 1 - 1 - - 2 - -

E2UC301T.5 3 3 3 3 3 2 2 - 1 1 - 2 - -

Note: 1-Low, 2-Medium, 3-High \ *first semester first course and first Course Outcome

11. TYPICAL EXAMPLE OF COURSES, CREDIT HOURS AND TEACHING HOURS

Credits Hours Hours of engagement/ 15 weeks/
Week semester
Total

Total

Type of Course Remarks

Theory

Theory
Tutorial

Tutorial
Practical

Practical
Self-study

Self-study

Total no.
of classes

Theory Course 3 0 0 0 3 3 0 0 0 3 45 45 classes for theory

Theory Course 45 classes for theory and

3 1 0 0 4 3 1 0 0 4 60
with Tutorial 15 for tutorial
Lab Course 0 0 1 0 1 0 0 2 0 2 30 30 hours lab sessions

45 classes for theory and

Integrated Course 3 0 1 0 4 3 0 2 0 5 75
30 hours of lab sessions
Comprehensive 45 classes for theory &
3 0 1 1 5 3 0 2 3 5+3* 75
Course 30 hours of lab sessions
Seminar/Project/
0 0 0 0 1 0 0 0 0 0 0 -
Internship Course

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LESSON PLAN

L. No T/L Topics Skills Competency

1 L Introduction of COA
2 L Register Transfer Language Comprehension inter-register
3 L Register Transfer transfer using RTL and performing
4 L Bus and Memory Transfers basic operations such as
5 L Arithmetic Micro-operations arithmetic, logic, and shifts. CO1
6 L Logic Micro-operations
7 L Shift Micro-operations
8 L Arithmetic logic shift unit
9 L Arithmetic logic shift unit continued
10 L Instruction Cycle
Memory-Reference Instructions Analysis and comparison of
11 L
different types of computer
12 L Register reference instructions organizations on the basis of
13 L Input - Output Instructions instruction formats and
14 L General Register Organization addressing modes.
15 L CO2
Stack Organization
16 L Stack Organization Continued
17 L Instruction Formats
18 L Addressing Modes
19 L Addressing Modes Continued
Addition and Subtraction (Signed
20 L Magnitude and Signed 2’s Complement)
Multiplication Algorithms (Binary
21 L Multiplication for Signed Magnitude Application of computer
arithmetic algorithms to
22 L Booth’s Algorithm solve problems CO3
23 L Booth’s Algorithm Continued
24 L Numerical Based on Booth’s Algorithm
Division Algorithms (Restoring and Non-
25 L Restoring)

Numerical Based on Division Algorithms

26 L (Restoring and Non-Restoring) Continued

27 L Memory Hierarchy
28 L Main Memory Designing of various
29 L Auxiliary Memory memory system for the
30 L Associative Memory computer for provided CO4
31 L Cache Memory specifications and
Virtual Memory requirements
32 L
33 L Memory Management Hardware

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COURSEPACK
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Memory Management Hardware

34 L
Continued
35 L Peripheral Devices
36 L Input-Output Interfaces
37 L Asynchronous Data Transfer
38 L Modes of Transfer
39 L Priority Interrupt Evaluation of interpretation
40 L Direct Memory Access (DMA) the principles of input- CO5
41 L Revision / Backup output organization
42 L Revision / Backup
43 L Revision / Backup
44 L Revision / Backup
45 L Revision / Backup

12. BIBLIOGRAPHY

TEXT BOOKS:
2. Morris Mano, Computer System Architecture, 3rd Edition, Prentice-Hall of India Private Limited, 1999.

REFERENCE BOOKS:
4. Hayes, John P. Computer architecture and organization. McGraw-Hill, Inc., 2002.
5. Carl Hamacher, Zvonko Vranesic, Safwat Zaky Computer Organization, McGraw-Hill, Fifth Edition,
Reprint 2012
6. William Stallings, Computer Organization and Architecture-Designing for Performance, Pearson
Education, Seventh edition, 2006

SWAYAM/NPTEL/MOOCs Certification

4. https://www.coursera.org/learn/comparch

5. https://nptel.ac.in/courses/106105163

https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/

13. COURSE ASSESSMENT

Assessment forms an integral part of curriculum design. A learning-teaching system can only be effective if the
student’s learning is measured at various stages which means while the student processes learning (Assessment for
Learning) a given content and after completely learning a defined content (Assessment of Learning). Assessment for
learning is referred to as formative assessment, that is, an assessment designed to inform instruction.
The ability to use and apply the knowledge in different ways may not be the focus of the assessment. With regard to
designing assessments, the faculty members must be willing to put in the time required to create a valid, reliable
assessment, that ideally would allow students to demonstrate their understanding of the information while remaining.
The following are the five main areas that assessment reporting should cover.

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1. Learning Outcomes: At the completion of a program, students are expected to know their knowledge, skills,
and attitude. Depending on whether it is a UG or PG program, the level of sophistication may be different. There
should be no strict rule on the number of outcomes to be achieved, but the list should be reasonable, and well-
organized.
2. Assessable Outcomes: After a given learning activity, the statements should specify what students can do to
demonstrate. Criteria for demonstration are usually addressed in rubrics and there should be specific examples
of work that doesn’t meet expectations, meets expectations, and exceeds expectations. One of the main
challenges is faculty communication whether all faculty agreed on explicit criteria for assessing each outcome.
This can be a difficult accomplishment when multiple sections of a course are taught or different faculty
members. Hence there is a need for common understanding among the faculty on what is assessed and how it is
assessed.
3. Assessment Alignment: This design of an assessment is sometimes in the form of a curriculum map, which can
be created in something as easy as an Excel spreadsheet. Courses should be examined to see which program
outcomes they support, and if the outcome is assessed within the course. After completion, program outcomes
should be mapped to multiple courses within the program.
4. Assessment Planning: Faculty members need to have a specific plan in place for assessing each outcome.
Outcomes don’t need to be assessed every year, but faculty should plan to review the assessment data over a
reasonable period of time and develop a course of action if the outcome is not being met.
5. Student Experience: Students in a program should be fully aware of the expectations of the program. The
program outcomes are aligned on the syllabus so that students are aware of what course outcomes they are
required to meet, and how the program outcomes are supported. Assessment documents should clearly
communicate what is being done with the data results and how it is contributing to the improvement of the
program and curriculum.
Designing quality assessment tools or tasks involves multiple considerations if it is to be fit for purpose. The set of
assessments in a course should be planned to provide students with the opportunity to learn as they engage with
formative tasks as well as the opportunity to demonstrate their learning through summative tasks. Encouraging
the student through the use of realistic, authentic experiences is an exciting challenge for the course faculty team,
who are responsible for the review and quality enhancements to assessment practices.

14. DIFFERENCE BETWEEN FORMATIVE AND SUMMATIVE ASSESSMENT

a) Formative Assessment
The goal of formative assessment is to monitor student learning to provide ongoing feedback that can be used by
Course Faculty to improve their teaching and by students to improve their learning. More specifically, formative
assessments help students identify their strengths and weaknesses and target areas that need work, and faculty
members recognize where students are struggling and address problems immediately. Examples of formative
assessments include Mid Term Exam (MTE) as well as asking students to:
 Draw a concept map in class to represent their understanding of a topic
 Submit one or two sentences identifying the main point of a lecture
 Turn in a research proposal for early feedback

b) Summative assessment
The goal of summative assessment is to evaluate student learning at the end of a Course by comparing it against some
standard or benchmark. Examples of summative assessments include:
 a final project
 a paper
 Semester-End Examination (For courses running in Semester mode)
 End-Term Examination (For courses running in Annual Mode)

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Information from summative assessments can be used formatively when students or faculty use it to guide their efforts
and activities in subsequent courses.
c) Weightage
The formative and summative assessments are given 50-50 weightage to ensure proper learning levels among the
students.

14.1 Assessment Pattern for Theory Course:

CIE Total
Type of Course Marks Final Marks
(T) CIE*0.5+SEE*0.5
IA1# MTE IA2# CIE SEE

THEORY 25 50 25 100 100 100

#
Typical Rubric for the Internal Assessments
Type of Assessment Tools QUIZ AAT$/MOOC Certifications

Internal Assessments
$
AAT is Literature survey, Seminar, Assignment, Term Paper, Slip Test (or) MOOC Certificate relevant to the
course
14.2Assessment Pattern for Integrated (Blended) Course:
CIE Total Marks
Type of Course Final Marks
(B) LAB CIE*0.5+SEE*0.5
LAB Work@ + Record MTE CIE SEE
EXAM*
INTEGRATED 25 50 25 100 100 100
@
Lab Work-15 marks + Lab Record-10 marks
*
Passing Criteria-30% of marks to be secured in the lab Exam conducted by two examiners (one internal and one
external)

14.3Assessment Pattern for Comprehensive Course:

CIE Total Marks
Final Marks
Type of Course (C) LAB@(Work+ Course-based CIE*0.5+SEE*0.5
Record) MTE Project^ CIE SEE

COMPREHENSIVE 25 50 25 100 100 100

@
Lab Work-15 marks + Lab Record-10 marks

^Typical Rubric for the Course-based project

Preliminary Project Technical
Type of Assessment Tools Seminar TRL-1 Viva-voce
Plan
Course-based Project Work 05 05 10 05

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 PPP (Preliminary Project Plan): The preliminary project plan (PPP) provides an initial, overview of the project
and all of its known parameters. It outlines the project’s objectives, relevance to the program, merit, and conformity
to current industry/ government policy, proposed methodology, and expected outcomes. It should also include any
known constraints related to the time frame (Gantt Chart), budget, etc.
TRL (Technology Readiness Level)-1: Basic Research: Initial scientific research has been conducted. Principles
are qualitatively postulated and observed. Focus is on new discovery rather than applications.

14.4Assessment Pattern for Two Credit MOOC Courses (Online/Self-Paced Learning)

Type of Course CIE Total Marks
Final Marks
(M)
IA1 IA2 CIE* SEE CIE+SEE

2 CREDIT MOOC
25 25 50 50 100
COURSES
*
from MOOC portal

14.5 Assessment Pattern for Lab Course:

CIE Total Marks
Type of Course Final Marks
(L) LAB Work@ LAB CIE+SEE
+ Record CIE SEE LAB EXAM*
TEST

LABORATORY 25 25 50 50 100
@
Lab Work-15 marks + Lab Record-10 marks
*
Passing Criteria-30% of marks to be secured in the lab Exam conducted by two examiners (one internal and one
external)

14.6Assessment Pattern for Seminar/Minor Project/Internship Course:

Type of Course CIE Total Marks Final Marks
(V) CIE+SEE
IA1@ IA2@ CIE SEE
SEMINAR/PROJECT/INTERNSHIP 25 25 50 50 100
@
Rubric to be specified by the concerned Faculty

14.7Assessment Pattern for Final Year Student Capstone Project:

CIE Total Marks

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COURSEPACK
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Type of Course
(R)

Conclusion/

FinalMarks
Identification

Result Analysis
Methodology
Experimental/

Findings

CIE+SEE
Literature Review/
Problem

Applicability
CIE SEE%

CAPSTONE PROJECT 10 10 10 10 10 50 50 100

%Typical Rubric for SEE

Formulation
of Problem TRL (Technology Readiness Level) Presentation Viva Voce
Statement
20 (TRL-1 to TRL-4)
10 0 marks for 5 marks for 10 marks 15 marks 20 marks 10 10
no TRL TRL-1 for TRL-2 for TRL-3 for TRL-4
TRL 1 Basic Initial scientific research has been conducted. Principles are qualitatively postulated and
Research observed. Focus is on new discovery rather than applications.

TRL 2 Applied Initial practical applications are identified. Potential of material or process to solve a
Research problem, satisfy a need, or find application is confirmed.
TRL 3 Critical Function
Applied research advances and early-stage development begins. Studies and laboratory
or Proof of Concept
measurements validate analytical predictions of separate elements of the technology.
Established
TRL 4 Lab Testing/
Design, development and lab testing of components/processes. Results provide
Validation of Alpha
evidence that performance targets may be attainable based on projected or modelled
Prototype Component/
systems.
Process
Note: Council Driven Programs can follow their own assessment pattern.

15. PASSING STANDARDS

High standards are maintained in all aspects of the examination. The relative grading method is followed. The
minimum standard of passing in respect of CIE and SEE for each course as shown in the table shall be effective from
the academic session 2022-23 onwards.
Note: The programs running with the approval of respective councils shall follow the passing standards as
defined by the respective councils.
Passing Criteria for Different Course Types Effective from AY 2022-23 Onwards
S.No. Course Type Passing Criterion

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 1. Theory Course (T) A student shall secure a minimum of 30% of the maximum marks in
the semester-end examination (SEE/ETE) and 40% of aggregate marks
in the course including Continuous internal examination (CIE) and
SEE/ETE marks. i.e., the minimum Passing Grade is “P”.
2. Integrated course (B) A student shall secure a minimum of 30% of the maximum marks in
the semester-end examination (SEE/ETE), 30% of the maximum
marks in the LAB EXAM, and 40% of aggregate marks in the course
Continuous internal examination (CIE) and SEE/ETE marks i.e.,
minimum Passing Grade in a course is “P”.
3. Comprehensive Course (C) A student shall secure a minimum of 30% of the maximum marks in
the semester-end examination (SEE/ETE) and 40% of aggregate marks
in the course Continuous internal examination (CIE) and SEE/ETE
marks i.e., minimum Passing Grade in a course is “P”.
4. Lab Course (L) A student shall secure a minimum of 30% of the maximum marks in
the SEE LAB EXAM and 40% of aggregate marks in the course
Continuous internal examination (CIE) and SEE/ETE marks i.e.,
minimum Passing Grade in a course is “P”.
5. Seminar/Project/ A student shall secure a minimum of 40% of aggregate marks in the
Internship Course (R) Continuous internal examination (CIE) and SEE/ETE marks i.e.,
minimum Passing Grade in a course is “P”.
Note: Students unable to meet the overall passing criteria as mentioned in Sr. No-1, 2 & 3 shall be eligible for the
following options to clear the course:
Appear in the Back Paper Examinations and have to meet the criteria to score 40% in marks overall
appear in summer examinations (internal +External) to meet the criteria as per Sr. No-1, 2 & 3.

16. PROBLEM-BASED LEARNING/CASE STUDIES/CLINICS

Exercises in Problem-based Learning (Assignments) (Min 54 Problems)

Practice Problems

1.

2.

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3.

4.

5.

6.

7.

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8.

10. Represent 25 H, 42 H and 2000 H into binary numbers.

11. What is difference between following two instructions?

MOV BL, 25 H and MOV BL, [25 H]
In above instruction, BL is register available inside processor.

12. In following assembly language program, identify that which type of addressing mode has been used in
each of the instructions.

MOV BL, [2000 H]

MOV CL, [3000 H]
ADD BL, CL
ADD BL, 55H
MOV [4000], BL

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Here, BL and CL are registers available inside processor.

13. The following memory units are specified by the number of words times the number of bits per word. How
many address lines and input-output data lines are needed in each case?

(a) 2K x 16; (b) 64K x 8; (c) 16M x 32; (d) 4G X 64.

14. How many 128 x 8 memory chips are needed to provide a memory capacity of 4096 x 16?

15. Show the value of all bits of a 12-bit register that hold the number equivalent to decimal 215 in (a) binary;
(b) binary-coded octal; (c) binary-coded hexadecimal; (d) binary-coded decimal (BCD).

16. Perform the arithmetic operations (+42) + (- 13) and (-42) - (- 13) in binary using signed-2's complement
representation for negative numbers.

17. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with
multiplexers.

a. How many selection inputs are there in each multiplexer?

b. What size of multiplexers are needed?

c. How many multiplexers are there in the bus?

18. The 8-bit registers AR, BR, CR and DR initially have the following values:

AR= 11110010, BR= 11111111, CR=10111001 and DR=11101010. Determine the 8-bit values in each
register after execution of the following sequence of micro operations.

AR AR + BR

CR CR ^ DR, BR BR +1

AR AR - CR

19. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one
word in memory. The instruction has four parts: an indirect bit, an operation code, a register code part to
specify one of 64 registers, and an address part.
a. How many bits are there in the operation code, the register code part, and the address part?

b. Draw the instruction word format and indicate the number of bits in each part.

c. How many bits are there in the data and address inputs of the memory?

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20. The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The content of AC is
7EC3. The content of memory at address 3AF is 932E. The content of memory at address 32E is 09AC. The
content of memory at address 9AC is 8B9F. (001 = ADD)

a. What is the instruction that will be fetched and executed next?

b. Show the binary operation that will be performed in the AC when the instruction is executed.

c. Give the contents of registers PC, AR, DR, AC, and IR in hexadecimal and the values of E, I, and the
sequence counter SC in binary at the end of the instruction cycle.

21. A digital computer has a memory unit with a capacity of 16,384 words, 40 bits per word. The instruction
code format consists of six bits for the operation part and 14 bits for the address part (no indirect mode bit).
Two instructions are packed in one memory word and a 40-bit instruction register IR is available in the
control unit. Formulate a procedure for fetching and executing instructions for this computer.

22. The following program is stored in the memory unit of the basic computer. Show contents of the AC and PC,
at the end, after each instruction is executed. All numbers listed below are in hexadecimal.

10 CLA

011 ADD 016

012 BUN 014

013 HLT

014 AND 017

23. Write a program to evaluate the 015 BUN 013 arithmetic statement:

X = (A + B) * (C + 016 C1A5 D)

a) Using a general register computer 017 93C6 with three-address instructions.

b) Using a general register computer with two-address instructions.
c) Using a single-accumulator computer with one-address instructions.
d) Using a stack organized computer with zero-address operation

24. Explain the difference between hardwired control and microprogramed

control. Is it possible to have a hardwired control associated with a control memory?

25. The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format
with four fields: an operation code field, a mode field to specify one of seven addressing modes, a register
address field to specify one of 60 processor registers, and a memory address. Specify the instruction format
and the number of bits in each field if the in instruction is in one memory word.

26. An instruction is stored at location 300 with its address field at location 301. The address field has the value
400. A processor register R 1 contains the number 200. Evaluate the effective address if the addressing mode
of the instruction is (a) direct; (b) immediate; (c) relative; (d) register indirect; (e) index with R1 as the index
register.

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27 Give five examples of external interrupts and five examples of internal interrupts. What is the difference
between a software interrupt and a subroutine call?

28. The two-word instruction at address 200 and 201 is a "load to AC" instruction with an address field equal to
500. The first word of the instruction specifies the operation code and mode, and the second word specifies
the address part. PC has the value 200 for fetching this instruction. The content of processor register R 1 is
400, and the content of an index register XR is 100. AC receives the operand after the instruction is executed.
The figure lists a few pertinent addresses and shows the memory content at each of these addresses. Calculate
the effective address and the operand that must be loaded into AC for (a) Direct, (b) Immediate, (c) Indirect,
(d) Relative, (e) Indexed (f) Register (g) Register Indirect (h) Autoincrement, (i) Autodecrement addressing
mode.

29. In certain scientific computations it is necessary to perform the arithmetic operation (Ai + Bi) (Ci + Di) with
a stream of numbers. Specify a pipeline configuration to carry out this task. List the contents of all registers
in the pipeline for i = 1 through 6.

30. Draw a space-time diagram for a six-segment pipeline showing the time it takes to process eight tasks.

31. Determine the number of dock cycles that it takes to process 200 tasks in a six-segment pipeline.

32. A no pipeline system takes 50 ns to process a task. The same task can be processed in a six-segment pipeline
with a clock cycle of 10 ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the maximum
speedup that can be achieved?

33. A weather forecasting computation requires 250 billion floating-point operations. The problem is processed
in supercomputer that can perform 100 megaflops. How long will it take to do these calculations?

34. Perform the arithmetic operations below with binary numbers and with negative number in signed-2"s
complement representation. Use seven bits to accommodate each number together with its sign. In each case,
determine if there is an overflow by checking the carries into and out of the sign bit position.
(a) (+35) + (+40)

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 (b) (-35) + (- 40)

35. Show the step-by-step multiplication process using Booth algorithm when the following binary numbers are
multiplied. Assume 5-bit registers that hold signed numbers, the multiples and in both cases is + 15.

(a) (+15) X (+13)

(b) (+15) X (-13)

36. Explain the difference between the daisy chaining priority and parallel priority interrupts. Draw the diagrams
to explain their working.

37. A computer uses a memory unit with 256 K words of 32 bits each. A binary instruction code is stored in one
word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to
specify one of 64 registers and an address part. Draw the instruction word format and indicate the number of
bits in each part.

38. A computer uses RAM chips of 1024x1 capacity.

(i) How many chips are needed to provide a memory capacity of 1024 bytes?

(ii) How many chips are needed to provide a memory capacity of 16K bytes?

39. How many characters per second can be transmitted over a 1200-baud line in each of the following modes?
(Assume a character code of eight bits).

a. Synchronous serial transmission.

b. Asynchronous serial transmission with two stop bits.

c. Asynchronous serial transmission with one stop bit.

40. a. How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes?

b. How many lines of the address bus must be used to access 2048 bytes of memory? How many of these
lines will be common to all chips?

c. How many lines must be decoded for chip select? Specify the size of the decoder.

41. The logical address space in a computer system consists of 128 segments. Each segment can have up to 32
pages of 4K words in each. Physical memory consists of 4K block of 4K words in each. Formulate the logical
and physical address formats.
42. Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU
generates 32 bits addresses. Calculate the number of bits needed for cache indexing and the
number of tag bits are respectively.

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17. STUDENT-CENTERED LEARNING (SELF-LEARNING TOWARDS LIFE-LONGLEARNING)

Self-Learning, self-doing, and application of the knowledge acquired through the course after gaining adequate
knowledge
It’s a typical course-based project to be carried out by a whole class in groups of four students each; they should
exhibit higher level Knowledge Levels (Bloom’s Revised Taxonomy). To enhance their skill set in the integrated
course, the students are advised to execute course-based Design projects.
The students, in a group not exceeding 4, are expected to conceive an idea based on the content (objectives/ outcomes)
and apply the suitable knowledge to demonstrate their ability to learn.
A list of 30-40 project statements can be offered to the students to choose or develop their own ideas (teamwork) to
define a problem statement, design and develop a product/ process/service/application, and provide a suitable solution
(design thinking). They may also upload this Idea on the Yukti Portal (contact the University IIC Team) and also
patent the same.

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