Paramount

1111
Analog Electronics

Unique Collection of Questions with

Detailed Solutions
 PREFACE

It is our pleasure, that we insist on presenting “Paramount 1111” authored for

Electronics & Communication Engineering to all of the aspirants and career
seekers. The prime objective of this book is to respond to tremendous amount
of ever growing demand for error free, flawless and succinct but conceptually
empowered solutions to all the questions.
This book serves to the best supplement for GATE 2023 (EC).
Simultaneously having its salient features the book comprises :
 Step by step solution to all questions.
 Complete analysis of questions through concept wise.
 Solutions are presented in simple and easily understandable language.
The authors do not sense any deficit in believing that this title will in many aspects, be different
from the similar titles within the search of student.
In particular, we wish to thank GATE ACADEMY expert team members for their hard work
and consistency while designing the script.
The final manuscript has been prepared with utmost care. However, going a line that, there
is always room for improvement in anything done, we would welcome and greatly appreciate the
suggestions and corrections for further improvement.

Umesh Dhande
Vice President - Academics GATE & ESE
(UNACADEMY)
 5 Analog Electronics

Questions
Q.1 The comparators (Output = ‘1’ When Q.3 Consider the circuit shown in figure. If
V+ > V− and output = '0' when V− > V+ ), the closed loop gain of the circuit is 0.75
For VS = 2sin1000t , the DC component then the open loop gain, of the Op-Amp
‘ AOL ’ is ________. (rounded upto one
of V0 in volt is _______.
+5 V decimal place)

VS +
V0 -
AOL V0
1V – +
− 5V +
: V
- S
Q.2 Consider the schmitt trigger circuit
shown in figure. The following option
is/are correct [MSQ] Q.4 Consider the MOSFET amplifier circuit
shown in given below given. The
V
1 kW voltage gain out is given by.
1 kW +8 V Vin
Vin -
V0 MOSFET : M1 M 2 M 3
+
- 10 V 1 kW Trans conductance : g m1 g m2 g m3
Output impedance : R01 R02 R03
1 kW VDD

m2
(A) It’s a type of inverting Schmitt
trigger Vout
Vin m3
(B) It’s a type of non-inverting Schmitt
trigger m1
(C) The hysteresis voltage is
approximately 18 V C1
(D) Output is always bistable on + 8 V
and –10 V
 5.2 Paramount 1111 [EC] GATE ACADEMY®
− g m1 g m1 Q.6 Consider a shunt regulator circuit using
(A) Av = (B) Av = zener diode and BJT shown in below
g m2 g m2
− g m2 figure. ( β is very high and VBE = 0.7 V).
(C) Av = g m1 × g m2 (D) Av =
g m1
Q.5 The output voltage Vout of the given
circuit, for given signal as shown in the
below figure in steady state.
Vi (t )

2V

t The collector current I C (in mA) is

6 ms 12 ms
_______. (rounded upto one decimal
–2V
places)
Q.7 A voltage (1 + 2sin ωt ) is applied to the
+ + circuit shown below. The capacitor ‘C’
C
and diode are considered as ideal, RL is
Vi (t ) R V0 (t)
the resistance of large value.
– –

(A)

0V
The magnitude of average voltage (in
−4 V volts) across RL is ________. (in integer
only)
(B)
Q.8 M 1 and M 2 in the circuit shown below
+4 V
are N-MOSFET operating in saturation
0V region, forward voltage drop of each
diode is 0.7 V, leakage current is
(C) negligible and the op-amp is ideal.
+2 +5 V 1k

D2
t
1 mA
−2 D1
–

+
(D) M1 M2

−4 V
GATE ACADEMY® Analog Electronics 5.3

W  (A) ( g m1 + g m2 ) (r0 || r02 )

  1

L m2
=3  1 
W  (B)  r0 +  (r01 || r02 )
   2 gm
L m1  2 
Power dissipation at D1 and D2 are :  1 
(C)  g m2 +  (r01 || r02 )
(A) 2.1 mW, 0 mW  r02 

(B) 0 mW, 2.1 mW
(D) (r0 + r02 ) ( g m1 || g m2 )
(C) 0 mW, 0 mW
(D) 0.7 mW, 0 mW Q.11 Consider the circuit shown in figure.
Q.9 Consider the Op-Amp circuit shown in The minimum value of R (in kΩ ), such
figure. The value of common mode that the transistor is biased in saturation
rejection ratio (CMRR) is ________. is _______. (Assume VCEsat = 0.2 V and
80 K VBEsat = 0.8 V ).
1K +15 V
V1 -
V0
V2 +
1K 5K
100 K

+
10 K
(A) 405 (B) 505 b = 50
(C) 605 (D) 805 R V0
+ 8V
Q.10 Consider the MOSFET Amplifier circuit -
- 10 V -
shown in below figure. Small signal +
V
voltage gain 0 is given by
Vout Q.12 The slew rate of Op-amp is 0.5 V μsec
MOSFET : M 1 , M 2 and it is used in an inverting amplifier
Transconductance : g m1 , g m2 with gain = 50. If the sinusoidal input
signal is applied then input signal
Output Resistance : r01 , r02 magnitude (in mV) if its voltage gan is
VDD flat upto 100 kHz is _______. (rounded
opto two decimal places)
Q.13 The Op-Amp shown in the circuit below
M2 has a open loop voltage gain AOL = 10 ,
output impedance R0 = 5 Ω and infinite
Vout
input impedance. If the output voltage
+ V0 = 50 Volts , then the value of current
Vin M1
– (I) passing through 5 Ω resistor (in mA)
is _______. (Correct upto 2 decimal
places)
 5.4 Paramount 1111 [EC] GATE ACADEMY®
VDD
5 kW
– R2
–
Vout

Vb
– 10 V
R1

Vi n
Q.14 A Zener diode in the circuit shown in
 1
below figure, has a knee current of 15 (A)  g m +  ( R1  R2 )
 R1 
mA and a maximum allowed power
dissipated 4 W and breakdown voltage  1 
(B)  g m +  ( R1 || R2 )
of Zener diode is 15.4 V, otherwise  R2 
Zener diode is ideal, the value of the  1
(C)  g m +  ( R1 + R2 )
R   R1 
ratio  L (max)  is ________. (rounded
 RL (min)   1 
(D)  g m +  ( R1 + R2 )
upto two decimal places)  R2 
Ri = 150 Ω
Q.17 If unregulated supply change by 1.5 V,
Ii IZ IL + the corresponding change in output
voltage is 86 mV.
Vi = 60 V +
– VZ RL VL 82 W
+ +
– VS V0
Q.15 Schmitt trigger is shown in the given
– –
below figure. In case, the output rest of
upper threshold voltage. The range of Vi The incremental resistance of zener
diode is _______ Ω .
is
Q.18 Consider cascade amplifier shown in
below figure.

(A) Vi > 2 V (B) Vi < 2 V

(C) Vi > 1V (D) Vi > − 2 V ∂I out
The value of (in mA/V) is
Q.16 Assuming as MOSFET are in saturation ∂Vin
calculate the small-signal voltage gain _______. (rounded opto one decimal
of circuit shown in figure (λ = 0) . places)
GATE ACADEMY® Analog Electronics 5.5

Q.19 An n-p-n BJT has g m = 42 mA / V , I ID

4

M3 M4
Cμ = 3 × 10−13 F , Cπ = 4.8 × 10−13 F and
I ref
DC current gain β = 90 . The value of
unity gain cut-off frequency ( fT ) (in
GHz) is_________. (rounded opto one M1 M2
decimal places)
Q.20 A MOSFET carries a drain current of 1
W  W  W  W 
mA with VDS = 0.5 V in saturation. If   =   = 5 ,   =   = 10
 L 1  L 3  L 2  L 4
VDS rises to 1 V and a constant keeping
and I ref = 2 mA
channel length modulation parameter is
Q.23 In the circuit shown in below figure the
λ = 0.1V −1 , the value of device output
MOSFET parameters are given as
impedance (in kΩ ) is ________.
μ nCox = 100 μA/V 2 , VTH = 0.5V and
(rounded opto one decimal places)
λ = 0 . The value of the current flowing
Q.21 For the circuit shown in the figure
through the drain is
V
below, it is given that VCE = CC . The VDD = 1.8V
2
transistor has β = 49 and VBE = 0.7 V .
1kW
VCC = +12V
20kW
8R
RB æW ö 5
M1 ç ÷ =
C è L ø 0.18

b = 49
B 200 W
E

(A) 2.11 mA (B) 0.556 mA

RB (C) 2.67 mA (D) 0.35 mA
For this circuit, the value of is
R Q.24 Consider the circuit shown in figure
_______. (rounded opto one decimal below, the transistor operate in
places) saturation, μ nCox = 200 μA/V 2 , λ = 0 ,
Q.22 For the given circuit, if all the transistors W 20
are in saturation and channel length = , VTH = 0.4 V. Assuming the
L 0.18
modulation are negligible and threshold
current flowing through R2 is one-tenth
voltage are identical of all transistor the
value of the current ‘ I D 4 ’ (in mA) is of I D . The value of R1 + R2 (in kΩ )
_______. (rounded upto one decimal such that I D = 0.5 mA is ______.
places) (rounded upto one decimal places)
 5.6 Paramount 1111 [EC] GATE ACADEMY®
VDD = 1.8 V
(A) High pass filter
R1 500 W (B) Band pass filter
(C) Integrator
M1 (D) All pass filter
Q.28 Consider the following circuit shown in
R2
below figure, which one of the following
is a correct statement?
200 W 10 kW

+ +
D1
Q.25 The diodes in the circuit shown below Vi
D2
V0
10 kW
have Vγ = 0.7 V then output voltage V0 10 V
(in V) is _______. (rounde upto one – –
decimal places)
(A) D2 does not conduct for any value
9.5 kW
V0 of Vi

10 V D1 D2 D3 (B) V0 = 10V , D2 does not conduct for

0.5kW 5V 5V any value of Vi > 10 V
(C) V0 = 10V , D2 does not conduct for

Q.26 Consider a transistor circuit shown in any value of Vi < 20 V

below figure, if value of β is very high Vi
(D) V0 = , D2 does not conduct for
and VBE = 0.65V. 2
any value of Vi > 15V
Q.29 Consider the give MOSFET amplifier
circuit shown in figure below. Small
signal voltage gain is given by
MOSFET : M1 M 2
Trans conductance : g m1 g m2
Output resistance : ∞ Ω ∞ Ω
The value of the current I (in mA)
VDD
flowing through 2 kΩ resistance is
R1
_______. (rounded upto one decimal
places) M2

Q.27 The op-amp circuit shown below

R2
behaves as a Vout
C
Vs
R + Vin M1
V0
C1
-

C2
GATE ACADEMY® Analog Electronics 5.7

− g m 1 ( R1 + R2 ) (B) A = 25, f L ≈ 40 Hz
(A) AV =
1 + g m2 R2 (C) A = 40, f L ≈ 10 Hz
g m 1 ( R1 + R2 ) (D) A = 25, f L ≈ 10 Hz
(B) AV =
1 + g m2 R2 Q.33 Given figure (a) shows the
characteristics of Zener diode as
− g m 1 ( R1 + R2 )
(C) AV = regulator and figure (b) is the voltage
1 + R2 regulator circuit using the Zener diode of
− g m 1 ( R1 + R2 ) the same characteristics. The value of
(D) AV =
1 + g m2 ΔVL = VL (max) − VL (min) in volts is
Q.30 In the circuit shown in below figure D1 IZ
0.12 V
0
has 10 times the junction area of D2 .
The value of V results is _______ mV. 5 mA
(Take : VT = 25 mV )

I1 35 mA
10 mA
Fig. (a)
I S 1 kW IL
D2 D1 VL
RS IZ
+
20 V VZ RL
+
I2 V
3 mA – VZ = 10 Volts

Fig. (b)
Q.31 The open-loop low-frequency gain of an (A) 0.24 V (B) 0.36 V
amplifier is AOL = 106 and the band- (C) 0.12 V (D) 0.48 V
width of operation is 8 Hz. If the Q.34 Consider diode circuit shown below. All
bandwidth of the system is extended to the diodes are identical in all respects
250 kHz by applying feedback, then the accept for junction area of D1 , D2 and
maximum allowed gain that the D3 are A1 , A2 and A3 respectively
amplifier can have is _____ (dB) Ii n R
Q.32 It is desired to build an audio amplifier
ID ID ID
which has pass band of 20 Hz to 20 kHz 1 2 3

Vin D1 D2 D3
and a mid band gain of 64000. Three
stages are used in cascade and identical
for this purpose. The mid band gain and The expression of I D2 is
lower cut-off frequency ‘ f L ’ of each I in I in
(A) (B)
stage is ______. A A A A
1+ 1 + 1 1+ 3 + 2
(A) A = 40, f L ≈ 40 Hz A2 A3 A2 A1
 5.8 Paramount 1111 [EC] GATE ACADEMY®
VCC
I in I in
(C) (D)
A A A A
1+ 2 + 2 1+ 1 + 3 0.5 mA
A3 A1 A2 A2
5 kΩ
Q.35 In the circuit shown below, I is a dc V0
current and vs is a sinusoidal signal. Cin
30 kΩ
Vi
Capacitors C1 and C2 are very large: Cin
their function is to couple the signal to 0.25 k Ω
and from the diode but block the dc
current from flowing into the signal
source or the load (not shown). Use the
Q.38 An op-amp slew rate = 0.5 V/μsec has a
diode small-signal model. Let Rs =
gain of 20 dB. If this amplifier has to
1 kΩ . The value of I for which V0 faithfully amplify signal at 20 kHz,
become half of Vs _______ μA. (Take without introducing any slew Rate
VT = 25 mV ) induced distortion, then the input signal
level must not exceed ______ mV.
I Q.39 Consider the feedback network shown in
Rs C1 C2 figure,
+ Amplifier
+ Input Output
103 ± 10
vs + –
– v0
– Feedback
factor b
Q.36 Consider the network shown below If feedback factor is 0.4%, then the %
figure having a ideal diode ‘D’. change in gain of feedback amplifier is
D
______. (correct upto two decimal
places)
Vi RB 5Ω V0 Q.40 Consider the circuit shown in figure
having ideal diodes.
1kW
+
Given : Vi = 10sgn[sin πt ] Volts . The
D1 D2
value of ' RB ' in ohm’s such that average Vin + 1 kW V0
1V 2V
output voltage 'V0 ' is 4 volts, is ______.
Q.37 In the following circuit of BJT, a resistor From the transfer characteristics of the
of value ‘5k’ is connected across base given circuit, following data is obtained,
and collector junction. The current
Vin V0
common emtetr gain (β) of transistor is
– 2.5 V V1
V
100. Then the value of voltage gain 0
Vi + 1.5 V V2
is _______. (given VT = 25 mV ) The value of V1 + V2 (in V) is _______.
GATE ACADEMY® Analog Electronics 5.9
Q.41 NMOS and PMOS transistors in the Q.43 Consider the circuit shown below,
18 V
circuit shown are matched with
W  W 
μ nCox   = μ p Cox   = 1 mA/V 2 2 kW
 L n  L p 80 kW 120 kW
V0
R1 R2 VC
V 10 mF
10 mF
Vt = 1 V and I D = 0 mA
10 Vi b = 75
2.5 V
500 W 50 mF
NMOS
(W/L)n

VI V0 The value of DC level of collector

10 kW voltage VC (in volts) is _______.
PMOS
(W/L)p (VBE = 0.7 V)
Q.44 Consider the circuit shown below, if
– 2.5 V
both the MOS transistor are identical
For VI = 2.5V the output V0 is ______. with μ nCox = 30 μA/V 2 ,
(correct upto two decimal places) W 
  = 2 and thersold voltage of
Q.42 In the figure shown below both  L  MT1 , MT2
transistor have same values of g m and both MOS transistor VT = 1V . The value
β. The input impedance of the circuit is of I 0 (in μA) is _______. (correct upto
+5 V
two decimal places)
V0
I0

V0
MT1 MT2

Vin
3V

RE Q.45 The Op-Amp circuit along with its input

voltage 'Vi ' is shown below. If the

β output gets saturated at time t = 150sec,

(A) + RE the value of capacitor ‘C’ (in mF) is
gm
________. (correct upto two decimal
β
(B) + (1 + 2β) RE places)
2 gm
β
(C) + (1 + β) RE
gm
β (1 + β)
(D) + RE t (sec)
2 gm 2
 5.10 Paramount 1111 [EC] GATE ACADEMY®

-
C
+
network ‘N’ is _______. (correct upto
two decimal places)
R = 150 kW + 15 V N
Vi -
V0 I
+ 4W 1W
-15 V +
10sin wt
volts – 5W
8W 2W
Q.46 The value of V0 for the given Op-Amp
circuit is ________. Q.49 A diode circuit and waveform of its
1k
applied input are shown below,
+15 V Vin
1k
2V
Frequency = 1000 Hz
V0
10 V

−15 V
t

1k
–20 V
2k

0.1μF

(A) 6 V (B) 8 V
(C) 10 V (D) ± 15 V D
Vin 1MW V0
Q.47 Consider the oscillator circuit shown in 5V
figure below, if the Op-Amp is ideal,
R 
then the value of ratio  2  is _______. If diode D is ideal, then the sum of
 R1  maximum and minimum output voltages
(correct upto two decimal places) in steady state is _______ V. (correct
upto two decimal places)
R2
R1 Q.50 A bipolar transistor has parameters
-
Vout β = 150, Cπ = 2 pF, Cμ = 0.3pF and is
+

C1 = 2 mF
biased at I CQ = 0.5 mA at room
temperature. The beta cutoff frequency
R3 = 20 kW
(in MHz) is _________. (Assume
C2 = 4 mF R4 = 40 kW
VT = 25mV)
Q.51 The transistor in the circuit shown
below, is specified to have β in the
Q.48 In the circuit shown below, the diode range 50 to 100. What is value of RB
used is an ideal diode. The average value that results in saturation with an
of current I (in amperes) delivered to the overdrive factor of at least 10?
GATE ACADEMY® Analog Electronics 5.11
+ 10 V 2W

+ +
1 kΩ Vin (t ) 2F 1F Vc (t )
– –

RB
+5V
Q.54 In the clipping circuit shown below, the
diode is ideal and Vs (t ) is a triangular
wave with 10 V peak value, zero average
(A) 22 kΩ (B) 11 kΩ value and 10 m sec time period. If
(C) 2.2 kΩ (D) 1.1 kΩ Vb = 2.5 V , the average value (in volts)
Q.52 Consider voltage regulator circuit shown of output voltage V0 (t ) is _______.
below (rounded upto two decimal places)
10 kW IS
+ R +

20 V +
– RL (k W) V s (t ) Vs (t )
Vb
– –
Zener used has the breakdown voltage,
Q.55 An amplifier circuit is shown below,
Vz = 5V , rz = 0 kΩ and it is known that
α = 1, RC = 10 kΩ, I = 1mA, RE = 200 Ω
ratio of power rating to the minimum
power dissipation across Zener diode is and CE = 1μF. Assume rπ = 0, r0 = ∞.
1.4. The lower 3-dB frequency of amplifier
If RL is varied from 10 kΩ to ‘ Rmax ’ (in kHz) is _____. (Assume VT = 25mV)

kΩ, then the value of Rmax to maintain +VCC

the voltage regulation is RC

(A) 15 kΩ (B) 20 kΩ V0
(C) 100 kΩ (D) 50 kΩ
Q.53 In the circuit shown below, the diode is +
ideal and all the capacitors are initially Vs RE
– CE
uncharged. A voltage Vin (t ) is applied as
I
input to the circuit for t ≥ 0 . The voltage
Vin (t ) is a periodic square wave of time
period 2 sec and having amplitude of 4 Q.56 The MOSFET in the amplifier circuit
volts peak to peak. The value of voltage shown below, has trans-conductance
Vc (t ) (in volts) at t = 1.99sec is g m = 1 mA/V. The value of voltage gain
_______. (correct upto two decimal (V0 / Vs ) and input impedance ‘ Rin ’ are
places) respectively
 5.12 Paramount 1111 [EC] GATE ACADEMY®
+VDD Q.59 The Op-Amp shown in the circuit below
is an ideal Op-Amp and is having a slew
RD = 15 kΩ 1
∞
V0 rate of V/μsec . The input signal Vi
6
RL 15 kΩ varies by 0.4 Volts in 12 μsec . If the
value of open loop gain ( AOL ) is 10 and
RS = 2 k Ω ∞
the value of resistor R1 = 5 Ω , then the

vi I
value of feedback resistor RF ,

Rin −VSS
–
(A) 7.5 V / V and 7.5kΩ
(B) 2.5 V / V and 1kΩ
(C) 3.75 V / V and 7.5kΩ – 15 V
(D) 12.5 V / V and 1kΩ (A) 35 Ω (B) 40 Ω
(C) 45 Ω (D) 50 Ω
Q.57 In the circuit shown below the zener
Q.60 The effect of current shunt feedback in
diode has a breakdown voltage of 15
an amplifier
Volts. The value of current I (in mA) at
(A) Increases the input and output
t = 1sec will be _______ (Rounded off
impedances
to 2 decimal places).
(B) Increases the input impedance and
1kΩ
decreases the output impedance
I (C) Decreases the input impedance and
20[1 − e − t ] +
– D 1kΩ
increases the output impedance
(D) Decreases the input output
impedances
Q.58 Consider the Op-Amp circuit shown Q.61 The transistor shown in circuit below
below with open-loop gain is 10 has very high value of β. The zener
otherwise Op-Amp is ideal. diode has a breakdown voltage of 3
10 Ω Volts. If the value of VBE = 0.7 Volts,
10 Ω then the collector current I C (in mA) is
2V
10 Ω ________.
10 Ω
AOL = 10 V0
2V I0

10Ω
10 Ω
1k

1V

The value of current I 0 (in mA)

________. (in integer only).
GATE ACADEMY® Analog Electronics 5.13
Q.62 Assuming that the diodes in the circuits connected in the circuit shown below.
of figure are ideal, which of the The supply voltage Vs = 10 V, the value
following option(s) is/are correct. of voltage ‘ VL ’ (in V) for RL = 2 kΩ is
[MSQ]
________.
+3 V
Vs = 10 V

12 kΩ Rs = 0.5 kΩ

VL

I D1 D2 VZ = 6.8 V
RL
V

Q.64 The full wave rectifier circuit shown

6 kΩ
below, is operating at a frequency of 60
Hz. The rms value of the transformer
−3 V output voltage V1 = 18V and RL = 0.5
(A) The value of output voltage kΩ. The minimum value of C (in mF)
V = −1V required to maintain the ripple voltage
(B) The value of output voltage V = 3V (peak to peak) to less than 0.25 V, is
_______. (Assume diode voltage drop
(C) The value of current through
VDON = 1V)
I D1 = 0 A
V0
(D) The value of current through + D1
I D2 = 0.33A V1
– RL C
Vs
Q.63 A Zener diode specified to have +
V1
VZ = 6.8V at the test current I Z = 5 mA –

incremental (dynamic) resistance rZ = D2

20 Ω and knee current I Z = 0.2 mA, is

Q.65 In the circuit shown below, all the transistor are identical, VBE = 0.6 V and β = 90 . The value of
I C N is _______ mA. (correct upto two decimal places)
Assume : N = 9
9V

2k I C1 I CN -1 I CN

Q1 Q2 QN – 1
Q QN
VB
 5.14 Paramount 1111 [EC] GATE ACADEMY®

Q.66 Find V0 for the given ideal Op-Amp

circuit 1 mA
1k C2
v0
+15 V
1k V −
2V D1 D2
V0 C1
+
V
vi
−15 V
I
2k
1k
Q.69 An operational amplifier circuit is
shown in below figure the transfer
(A) 6 V (B) – 6 V V ( s)
function is given by G ( s ) = 0 then
(C) ± 15 V (D) 10 V Vi ( s )
Q.67 Consider the ideal Op-Amp shown in the frequency in (rad/sec) at which phase
V  angle provides by the transfer function
figure below. The value of  in  is ‘ G(s) ’ is minimum is _______.
 I in 
______ kΩ . (correct upto two decimal (rounded upto one decmal places)
places) 2Ω 1F
3kW Vi -
1Ω 1F V0
Z
+
I in
+
V0
Vin +
– – Q.70 For the circuit shown in the below figure
Op-Amp has a differential gain AV = 10
R1 = 5 kW then, the value of Vout is
R2 30 kW Vin +
AV Vout
–
1kΩ

Q.68 In the capacitor-coupled attenuator

circuit shown in figure, I is a dc current
that varies from 0 mA to 1 mA, and C1 1kΩ 1mA
and C2 are large coupling capacitors.
For very small input signals, so that the
diodes can be represented by their small-
5
signal resistances rd 1 and rd 2 . The value (A) Vout = (2Vin + 1)
6
v0 2
of for I = 500 μA is _______. (B) Vout = Vin
vi 5
GATE ACADEMY® Analog Electronics 5.15
7 Q.73 Consider an Op-Amp circuit shown in
(C) Vout = (3Vin + 8)
5 below figure.
6 R
(D) Vout = Vin − 2
8 R1 C
+
Vin
Q.71 Consider the circuit shown in figure Vout
–
below. C 2R

+15 V
R2
R1

10 V Q1

The function of the above circuit is

R
(A) LPF (B) HPF
V0 = 2 V
(C) BPF (D) BSF
2 kW
Q2 Q.74 Which of the following option(s) is/are
D1 correct for given below circuit [MSQ]
100 W
27 kΩ
D2

+12 V
15 kΩ
+ 27 kΩ
– 15 V

If the output voltage of the circuit is 2 V − +

and VBE1 = VBE2 = VD2 = VD1 = 0.7 V and v0
−
assuming β to be very large. The value
of resistance R (in k Ω ) is _______. 0.033 μ F 51 kΩ

(correct upto two decimal places)

Q.72 Consider the Schmitt trigger circuit
(A) it is a type of as astable multivibrator
shown below,
+15 V (B) it is a type of as monostable
20 Ω multivibrator
Vin
Vout (C) Output frequency is zero hertz
5Ω (D) In steady state output voltage rest at
– 15 V
zero volt
R Q.75 Consider a BJT amplifiers shown below,
assuming CE to be very large, determine
the value of CC1 such that low frequency
If the hysteresis width is 26 V, then
cut-off for the given amplifier is 20 Hz.
value of resistance R (in Ω ) is ______.
(correct upto one decimal place) Assuming VT = 25 mV.
 5.16 Paramount 1111 [EC] GATE ACADEMY®
+3 V

40 kΩ 1.56 kΩ
V0
CC 1
β = 200

0.5 kΩ 0.6 kΩ
+
Vs 25 kΩ
0.15 kΩ CE
−

− 3V

(A) 0.623 μF (B) 0.172 μF

(C) 0.349 μF (D) 0.561 μF

Q.76 Vi is a pulse of 12 V & duration 5μs as shown in the figure (a) is applied to the circuit shown
in the figure (b). Assume that the initial voltage on 0 volt is waveform for V0 will be :
8k

12 V D

Vi 30 k 1000 pF V0
5 μsec
0V
Vi

Fig. (a) Fig. (b)

V0 V0

5.18 V 5.18 V

t (μsec) t (μsec)
(A) 0 5 (B) 0 5

V0 V0
5.18 V

2.18 V
t (μsec) t (μsec)
(C) 0 5 (D) 0 5

Q.77 For the transistor given in the circuit below VBE = 0.6 V , β = 120 and VBC = 0 V. Then the value
of load resistance ‘ RL ’ will be
GATE ACADEMY® Analog Electronics 5.17
15V

+ 8kΩ
5.6V
+

V0
20 kΩ
RL

(A) 12.43 kΩ (B) 13.43 kΩ (C) 4.69 kΩ (D) 8.8 kΩ

Q.78 In the circuit of figure shown below, an input signal Vs (t ) = 1.0sin ωt V is coupled to the BJT
that has β = 100 and VBE = 0.7 V. Assume VT = 0.025 V, the voltage measured between collector
terminal and ground, is
VCC = 12 V

R1 50 kΩ RC 5 kΩ

VC

R2 10 kΩ

RE 1 kΩ
V s (t )

(A) 1.2 + 0.76 sinωt V (B) 1.2 – 0.76 sinωt V

(C) 6 – 3.74 sinωt V (D) 6 + 3.74 sinωt V
Q.79 Consider CE amplifier shown in below figure. Assume β = 50 and rπ = 2 kΩ .

V0
The value of mid-band voltage gain is _______. (rounded opto one decimal places)
Vs
 5.18 Paramount 1111 [EC] GATE ACADEMY®

Q.80 Consider the Wien bridge oscillator Then approximated voltage gain
shown in figure below. To produce V
A = 0 for small signal input of Vin is
sustained oscillation, the value of R2 /R1 Vin
must be equal to ________ (Rounded off _______. (rounded opto one decimal
upto 2 decimal places) places)
4k 5 μF Q.82 In the high pass filter shown in the
figure, for a cut-off frequency of 1.5
kHz, the value of C (in μF ) is ______.
+
V0 R1 = 10 kW R2 = 20 kW
–
10 μF 2k
R2

R1
-
op-amp V0
Vi +
C
R = 1.5 kW
Q.81 Consider an amplifier circuit where all
three BJTs have β = 300 .
Q.83 The current I shown in figure, in mA, is
+ 12 V
close to
2k
4.7 kW
2 kW +15V
Q3
1 kΩ
–
Q2
V0
I
+ +
Vin Q1 10 V
–
−15 V
9 kW
1 kW 2 mA (A) 8.33 (B) 10
(C) 9.99 (D) 15
Q.84 Consider the circuit shown in below figure, the cut-in voltage of each diode are 0.7 V, otherwise
all diode are ideal. The plot of I D2 versus VI over the range 0 ≤ VI ≤ 12 V, for VB = 9 V.

12 V

I = 100 mA
D1 D2
VI
I D2
VB = 9 V
GATE ACADEMY® Analog Electronics 5.19

(A) I D2 (mA) (B) I D2 (mA)

100 100

VI (V) VI (V)
9V

(C) I D2 (mA) (D) I D2 (mA)

100
100

VI (V) VI (V)
–9V 4V

Q.85 Consider the circuit shown in below figure, cut-in voltage of diode is Vγ = 0.7 V, otherwise
diode is ideal. The plot of output voltage V0 versus I over the range 0 ≤ I ≤ 2 mA of the circuit
is

I R1 = 1kΩ V0
+
1V
–
–

(A) V0 (V) (B) V0 (V)

1.7 1.7

I (mA) I (mA)
0 1.7 0 0.7

(C) V0 (V) (D) V0 (V)

0.7 1

I (mA) I (mA)
0 1.7 0 1
 5.20 Paramount 1111 [EC] GATE ACADEMY®

Q.86 Consider the ideal op-amp circuit shown The minimum value of R f (in kΩ ) the
below for t ≥ 0 [MSQ] circuit below to generate oscillation is
4W
________. (rounded upto two decmal
2W – places)
2W Q.88 Consider the amplifier circuit shown
+
+
2V below :
1F Vc (t )

–
R

If the capacitor is initially uncharged, Vin

Vout
then which of the following option(s)
is/are correct.
(A) The value of capacitor voltage at 4 The output voltage Vout is proportional
sec is 5.187 V. to
(B) Current through 4 Ω resistor is fixed (A) ln (Vin ) (B) eVin
to 1 ampear.
(C) Vin (D) ln ( Vin )
(C) The value of capacitor voltage at 4
sec is 2 V. Q.89 As shown in figure, with ideal Op-Amp.
(D) The value of capacitor voltage at The overall system gain approximately
steady state is 6 V.  V0 
Q.87 Consider a RC phase shift oscillator as   :
 Vs 
shown in below figure. 10 k
R
Rf
1k ± 10%
Vs –
R
–
1kW + V0
- 0.1μF 1kW +

+ V0
1kW 0.1μF
(A) 10 ± 10% (B) 10  10%
(C) 10  1% (D) 5  2%

Q.90 Consider the circuit shown in below figure. (Both diodes D1 and D2 are ideal)
R

D1

+ Vsat
R
D2 + Vsat

Vin R V0
- Vsat
- Vsat

R
GATE ACADEMY® Analog Electronics 5.21
The transfer characteristics of the circuit is,
V0 V0

(A) Vin (B) Vin

V0 V0

(C) Vin (D) Vin

Q.91 Consider the circuit shown in below figure, assume diode is ideal ( Vγ = 0 ). The output waveform
of the circuit is
vi

25 +
D1 D2
T + 10 kΩ 20 kΩ
0 t Vi V0
T
– + +
2 2.5 V 10 V
– 25 – – –

(A) v0 (B) v0
25 25

10 10
0 t 0 t
T T T T
2 2

(C) v0 (D) v0
25 25

0 t 0 t
T T T T
2 2
 5.22 Paramount 1111 [EC] GATE ACADEMY®
Q.92 Consider the circuit shown in below figure, the cut-in voltage of diode Vγ = 0.7 V, breakdown
voltage of Zener diode VZ 1 = 2.3 V and VZ 2 = 5.6 V are respectively, otherwise all diode are
ideal. The transfer characteristic of the circuit is when −10 V ≤ Vi ≤ +10 V.
0.5 kΩ
Vi V0

D1 D2

VZ 1 VZ 2

1 kΩ 2kΩ

(A) V0 (B) V0

0.66 0.66
3 3

– 6.3 – 5.7
Vi Vi
3 2.5

– 6.3 – 6.3

0.8 0.8

(C) V0 (D) V0

0.8 0.8
3 3

– 6.3 6.3
Vi Vi
3 –3

– 6.3 – 6.3

0.66 0.66

Q.93 Consider diode circuit shown in below figure.

6 kΩ
+ iD (t ) = I D + ia (t )
9sin wt (mV)
- 3kΩ
9V
GATE ACADEMY® Analog Electronics 5.23

Where, iD (t ) = total instantaneous current, I D = quiescent current, ia (t ) = signal current,

forward voltage drop of each diode is 0.7 V. The signal current ia (t ) is _______. (Take
VT = 25mV)
(A) 1.45sin ωt μA (B) 2.45sin ωt μA (C) 0.8sin ωt μA (D) 1.6sin ωt μA
Q.94 The value of I1 , I 2 and Vx in the circuit shown respectively are. Assume VBE = 0.7 V and
β = ∞. [MSQ]
+10 V +10 V +10 V +10 V +10 V

10 K 8K
R1 = 20 kΩ
I1
I2
5K +5 V
Vx
VB 2
3.6 K

−5 V −5 V

(A) I1 = 0.68 mA (B) I 2 = 1mA (C) I 2 = 0.68mA (D) I 2 = − 3.4 V

Q.95 For the given circuit configuration both of the zener diode operates in break down region and
used operational amplifier is ideal in nature.The output voltage V0 (in volts) is ______.
10 k Ω
V0

2 kΩ 5 kΩ
+15V
V0
5V +

5V

Q.96 In the figure shown below the diode and op-amps are ideal. For an input Vin = sin ωt output
voltage Vout is
 5.24 Paramount 1111 [EC] GATE ACADEMY®
(A) Full wave rectified with a peak value +1V .
(B) Full wave rectified with a peak value −1V .
(C) Half wave rectifier with a peak value −1V .
(D) Half wave rectifier with a peak value + 1V .
Q.97 A cascaded connection of three current amplifiers A1 , A2 and A3 , whose gains are 50, 5 and 16
respectively, along with practical current source are shown in figure. If input and output
resistances of each stage is 40 Ω respectively, then magnitude of I 0 (in ampere) is _______.
(correct upto two decimal places)
I0
+
20 mA 40 A1 A2 A3 V0 0.46 kW
–

Q.98 The circuit shown below consists of an initially uncharged capacitor. The diodes used in the
circuit are ideal diodes and the zener diode has a breakdown voltage of 12 V. The value of
capacitor voltage Vc (t ) (in V) at t = 1.4sec is _______.
+

+
10sin t 2F Vc (t )
volts –

–
Q.99 In the circuit shown in below figure, all diodes are ideal, the plot of I1 versus input voltage (Vi ),
when Vi varies from −10 V ≤ Vi ≤ +10 V is
VZ = 3 V
10 kΩ
Vi V0
I1
D 10 kΩ

(A) I1 (mA)

0.65
0.23
– 10 –5
Vi (V)
3 5 10

–5

– 10
GATE ACADEMY® Analog Electronics 5.25

(B) I1 (mA)

0.35
0.1
– 10 – 5
Vi (V)
3 5 10

– 0.5
–1

(C) I1 (mA)

0.7
0.4
– 10 – 5
Vi (V)
3 5 10

– 0.5
–1

(D) I1 (mA)

0.8
0.3
– 10 – 5
Vi (V)
3 4 10

– 0.5
–1

Q.100 Consider the circuit shown below consisting of matched transistors with β = 100 and
VBE = 0.7 V and an ideal Op-Amp. The value of V0 (in V) is ______.
8V

1 kΩ
5 kΩ 2 kΩ +15 V
+
V0
+ −
10 V
Q1 Q2 2 kΩ –15 V

18 k
6k

Q.101 The circuit shown below, is designed to provide a voltage reference at node VE1 . The transistor
Q1 and Q2 have VBE = 0.7 V and large β. The Zener D1 has breakdown voltage VZ = 4.7V.
 5.26 Paramount 1111 [EC] GATE ACADEMY®

R1 2 kΩ

R3 = 10 kΩ Q1
R2 1 kΩ
VE1

Q2

VZ = 4.7 V D1 RE = 1kΩ
VEE = −12 V
The node voltage VE1 (in volts) is _____.
Q.102 The small signal model of a MOSFET shown in figure 1 is equivalently transformed into another
model shown in figure 2. The notations have usual meaning. The value of λ is
D
G ig = 0 id
id D
+
gmV gs

Vgs gmV gs G ig = 0

+
– V gs λΩ
S –

S
Fig. 1 Fig. 2
(A) g m−1 (B) 2 g m−1 (C) 2 g m (D) g m
Q.103 The straight line approximated frequency magnitude response of an amplifier circuit shown in
figure 1, is shown in figure 2

CE
+
Vi
–

Fig. 1 Fig. 2
The transistor has g m = 5 mA/V. Ignore channel length modulation effects. Then, in close
approximation
(A) G = 10, f1 = 10, f 2 = 100 (B) G = 31.3, f1 = 10, f 2 = 100
(C) G = 10, f1 = 62.8, f 2 = 628 (D) G = 31.3, f1 = 62.8, f 2 = 628
GATE ACADEMY® Analog Electronics 5.27
Q.104 An ideal op-amp is used in an inverting amplifier configuration as shown below. Note that
VPOS ≠ VNEG in the circuit.
R2 = 10 kΩ

R1 = 1 kΩ +15 V
Vin –

Ii Vout
+
R3 = 10 kΩ
−10V

The range of Vin in which the amplifier exhibits the linear operation, is
(A) −1V ≤ Vin ≤ 1.5V (B) −1.5V ≤ Vin ≤ 1V
(C) −1V ≤ Vin ≤ 1V (D) −1.5V ≤ Vin ≤ 1.5V
Q.105 The amplifier circuit shown below uses three op-amps operating in linear region. The input
V1 (t ) = A + B cos ωt V and V2 = 2 V. If the output V0 (t ) is expressed as V0 (t ) = A0 + B0 cos ωt ,
the value of A0 and B0 are
V1 + 20 kΩ 20 kΩ

–
5 kΩ –
V0
+
1 kΩ

– 5 kΩ

+ 20 kΩ
V2 20 kΩ

(A) A0 = 10(2 − A) and B0 = −10 B (B) A0 = −11(2 − A) and B0 = 11B

(C) A0 = −10(2 − A) and B0 = 10 B (D) A0 = 11(2 − A) and B0 = −11B
Q.106 Assume linear operation of op-amp in the circuit shown below. The circuit stays in steady state
with the switch S closed. When switch S is opened at t = 0, the voltage across capacitor, Vc (t )
for t ≥ 0 will be

(A) 4 − 6 e−6.25t (B) 6 − 4 e−6.25t (C) 4 (1 − e−3.125t ) (D) 6(1 − e−3.125t )

 5.28 Paramount 1111 [EC] GATE ACADEMY®
Q.107 The frequency response of an amplifier model with single pole transfer function, is shown below.
A(ω )

40 dB Slop = −20 (dB/dec)

Amplifier
X i ( t) X 0 (t )
A(ω)

0 4
ω
10
If input X i (t ) = 0.05cos (105 t ) V, the output X 0 (t ) is
(A) 0.1cos (105 t − 450 ) (B) 0.1cos (105 t − 84.30 )
(C) 0.5cos (105 t − 84.30 ) (D) 0.5cos (105 t − 450 )
Q.108 Consider the circuit shown in figure below.
10 V

100 Ω
R
4 kΩ
+10 V

6V +
– V0 = 2 V

– 10 V
4V +
–

The silicon transistor has VBE = 0.7 V , β = 100 and Op-Amp is ideal and V0 = 2V . Then value
of resistance R (in Ω ) is _______. (correct upto two decimal places)
Q.109 The voltage transfer characteristic for the circuit shown below, is

D2 R
3R
15 V +
V0
– Vx
D1
R

V1

(A) V0 (B)
V0
1 1
1 Vi 1 Vi
−5 V +5 V

(C) V0 (D) V0

1 1
+5 V −5 V
1 Vi 1 Vi
−5 V 1 1 VL
1 1
GATE ACADEMY® Analog Electronics 5.29

Q.110 The op-amps used in the circuit below, RF

are ideal and operating in linear region.

R1
The output observed, is of from -
λ + μ cos ωt volts. The values of λ and +
Vout

μ are respectively V +
–
cos ωtV
1 kΩ
1 kΩ 2V +
+ Vout
1 kΩ – V0 A=
– 1 kΩ V
1 kΩ
1 kΩ Ri R
1 kΩ
If it is known that, = 4 and 0 f =
R0 Rif
(A) –2 and 4 (B) 4 and –2 625, then the value of feedback factor β
(C) 4 and –1 (D) 1 and –4 and type of feedback are respectively
Q.111 Consider the feedback topology shown (A) 0.59, current shunt
below, (B) 0.49, current series
Ri R0
(C) 0.69, voltage shunt
Vif A V0 (D) 0.49, current shunt

Rif R0f
b

where, ‘A’ is the gain of non-inverting

Op-Amp with RF = 99 kΩ and R1 = 1
kΩ, as shown below

Answers Analog Electronics

1. – 1.66 2. A, C, D 3. 3 4. A 5. D

6. 6 7. –2 8. B 9. A 10. A

11. 0.0163 12. 15.9 13. 3.5 14. 7.51 15. B

16. A 17. 4.98 18. 4.938 19. 8.56 20. 10.63

21. 397.5 22. 8 23. B 24. 33.8 25. 4.3

26. 1.35 27. A 28. C 29. A 30. 78.75

31. 30.10 32. C 33. C 34. D 35. 25

36. 20 37. 83.26 38. 397.88 39. 0.2 40. – 0.5

41. 1.04 42. B 43. 11.266 44. 7.5 45. 2.5

46. D 47. 2.5 48. 1.326 49. 40 50. 9.226

 5.30 Paramount 1111 [EC] GATE ACADEMY®

51. C 52. D 53. 1.209 54. – 1.41 55. 0.7077

56. B 57. 6.32 58. 20 59. C 60. C

61. 2 62. A, C, D 63. 6.762 64. 1.63 65. 3.78

66. B 67. – 18 68. 0.5 69. 0.707 70. A

71. 1.043 72. 32.5 73. C 74. B, C, D 75. D

76. B 77. A 78. C 79. 51.6 80. 4

81. 10 82. 0.0707 83. A 84. A 85. A

86. A, B, D 87. 2 88. C 89. B 90. B

91. A 92. A 93. A 94. A, C, D 95. –5

96. A 97. 0.8 98. 9.85 99. B 100. 15

101. – 2.1 102. A 103. B 104. B 105. D

106. B 107. C 108. 60.929 109. A 110. C

111. D

Explanations Analog Electronics

1. – 1.66 At θ = θ1 ,
Given circuit is shown below figure, 2sin θ1 = 1
+5 V
π
VS + θ1 =
V0 6
1V –
π 5π
− 5V and θ2 = π − θ1 = π − =
6 6
If Vs > 1V; output voltage V0 = 5V
The average value of output waveform is,
If Vs < 1V; output voltage V0 = − 5 V
1 2π
2π 0
Vs (volts) V0 Avg = V0 (t )dt
2
1 4π 8π
π 2π 5× − 5×
ωt (rad) 6 6
θ1 θ2 =
2π
V0 (volts)
5  2  4
= 5×  − 5× 
 6  6
π ωt (rad) 10 20
0 5π 13π
6
= − = −1.66 V
6 6 6 6
–5
Hence, the correct answer is – 1.66 V.
GATE ACADEMY® Analog Electronics 5.31

2. (A), (C), (D) AOL

= 0.75
1 + AOL
Given :
AOL = 0.75 + 0.75 AOL
1 kW 0.25 AOL = 0.75
1 kW +8 V 0.75
Vin - ∴ AOL = =3
Vx (-) V0 0.25
Vx (+) +
- 10 V Hence, the open loop gain of the given circuit is
1 kW
3.
4. (A)
1 kW

1
g m Vgs gm2
1. As input applied on inverting terminal Vin
3 3

m3 r0 Vout
it’s a type inverting Schmitt trigger. + 3

Vgs – g m Vgs
2. As Op-Amp is saturated hence output is
3
1 1

g m Vgs g m Vgs
always bistable on + 8 V and –10 V. 3 3
3 3 r0
1

m1
+Vsat = 8 V Vs ig = 0 +
3
Vgs
−Vsat = −10 V –
Vs 1

V V
Vx − = in ×1 k = in Here, Vgs , = Vgs − Vs , = Vgs
2k 2
Vs3 = Vg1  Vgs1 = Vs3
V V
Vx + = 0 ×1 k = 0 Vs3 = r03 ⋅ g m3 ⋅Vgs3
2k 2
If Vx − < V x + then V0 = +Vsat and Vin = VUTP Vgs3 = Vin − Vs3 = Vin − r03 .g m3 .Vgs3
VUTP +Vsat Vin
= Vgs3 =
2 2 1 + g m3 ⋅ r03
VUTP = 8 V Vgs1 = Vs3 = Vin − Vgs3
If Vx − > V x + then V0 = −Vsat and Vin = VLTP Vin
Vgs1 = Vin −
1 + g m3 ⋅ r03
VLTP −Vsat
= g m3 ⋅ r03
2 2 Vgs1 = Vin ⋅
VLTP = −10 V 1 + g m3 ⋅ r03

VH = VUTP − VLTP = 8 − (−10) = 18 V  1 

Vout = − g m1 ⋅ Vgs1 ⋅   r01 
Hence, the correct options are (A), (C) and (D).  gm 
 2 
3. 3  1 
Vout = − g m1 ⋅Vgs1 ⋅  r01  
AOL  g
Given : Closed loop gain, A f = = 0.75  m 2 

1 + β AOL g m3 ⋅ r03
× ⋅Vin
Given circuit is a voltage follower with β = 1 . 1 + g m3 − r03
 5.32 Paramount 1111 [EC] GATE ACADEMY®
V0 T
Voltage gain : Av = Negative half cycle :<t <T
Vin 2
Diode OFF shown in below figure,
− g m1 ⋅ g m3 ⋅ r03  1  Vc (t )
Av = ⋅  r01  
1 + g m3 ⋅ r03   g m2 + –
 + +
C
If r01 = r02 = r03 = ∞ Ω
Vi (t ) R V0 (t )
− g m1  1 
Av = ⋅ 
1  gm – –
1+  2 
g m3 ⋅ r03 Applying KVL in the above circuit,
− g m1 − Vin (t ) + Vc (t ) + V0 (t ) = 0 V
Av =
g m2 V0 (t ) = − Vc (t ) + Vin (t )
Hence, the correct option is (A). V0 (t ) = − 2 + (− 2) = − 4 V
V0 (t )
5. (D)
Given circuit is shown below figure,
Vi (t ) t

2V
–4V
t Hence, the correct option is (D).
6 ms 12 ms
6. 6
–2V
Given : VBE = 0.7 V and β is very high i.e.
IB ≈ 0 A
+ +
C

Vi (t ) R V0 (t )

– –

T
Positive half cycle : 0 < t <
2
Diode ON shown in below figure,
Vc (t )
+ – From figure,
+ + VL = VZ + VBE = 8.3 + 0.7 = 9.0 V
C
VL 9
Vi (t ) R V0 (t) IL = = = 90 mA
RL 100

–
Applying KVL in above loop,
–
V − 8.3 − 0.7 21 − 9 12
V0 (t ) = 0 V IS = i = =
125 125 125
Vc (t ) = 2 V I S = 96 mA
GATE ACADEMY® Analog Electronics 5.33

Applying KCL at collector node VC , : Method 2 :

By using Superposition Theorem :
I S − I Z = IC + I L
I C = I S − I L = 96 − 90 = 6 mA
( IZ = IB = 0 A )
So, Collector current is I C = 6 mA .
Hence, the correct answer is 6 mA.
(i) Consider only DC input, Vi = 1V
7. –2

: Method 1 :
Question is based on concept of negative
clamper circuit.
Given : Vin = (1 + 2sin ωt )
From above figure,
VC1 = 1 V and V01 = 0 V
(V01 ) avg = 0 Volt
(ii) Consider only AC input,
Vi = 2sin ωt V

VC (max) across capacitor = Vin (max) = 3 V

Output of a negative clamper is given by,
V0 = Vin − VC = (1 + 2sin ωt ) − 3
= 2sin ωt − 2
As Vi (max) = 2 V
Vi (min) = −2 V
T
(a) For 0 < t < ;
4
C
+ + -
VC
2sin wt S.C. RL

-
Average value of V0 = 0 − 2 = − 2 V Diode is ON and the capacitor is
[Average of sin ωt = 0 ] charged to maximum value.
Hence, VC2 = 2 V and V02 = 0 V
Hence, the correct answer is – 2 V.
 5.34 Paramount 1111 [EC] GATE ACADEMY®
T 3T 8. (B)
(b) For <t < ;
4 4 Given circuit is shown below figure,
+5 V 1k

D2
1 mA
D1
–

M1 M2
From figure, VD = Vi − VC = Vi − 2
Since, Vi < 2
Therefore, VD = − ve
Hence, diode is OFF. From current mirror circuit,
(W /L) 2
IM2 = × I ref
(W /L)1
I M 2 = 3 × 1mA = 3mA
I D2 = 3I D1 = 3 ×1 = 3mA
Diode D2 -ON and Diode D1 -OFF
By applying KVL in above figure, The power dissipated by the diode D1 and D2
−V02 − 2 + Vi = 0 are respectively,
V02 = Vi − 2 PD1 = I D1 × VD1 = 0 × 0.7 = 0 mW

V02 = 2sin ωt − 2 PD2 = I D2 × VD2 = 3 × 10 −3 × 0.7 = 2.1mW

Hence, the correct option is (B).
9. (A)
Given circuit is shown below,
R f = 80 K

R1 = 1K
V1 -
V0
V2 +
R2 = 1K
R3 = 100 K

The average value of V02 is,

(V02 ) avg = − 2 V Gain at inverting terminal,
R 80 K
The overall output voltage is, A− = − f = − = − 80
R1 1K
(V0 ) avg = (V01 ) avg + (V02 ) avg = 0 − 2
Gain at non inverting terminal,
(V0 ) avg = −2 V  R   R3 
A+ =  1 + f  
Hence, the correct answer is – 2 V.  R1  R2 + R3 
GATE ACADEMY® Analog Electronics 5.35
∴ Differential mode gain, V0
AV = = − ( g m1 + g m2 ) (r01 || r02 )
 100  Vin
A+ = (1 + 80)   = 80.198
 101  Hence, the correct option is (A).
+ −
A −A 80.198 − (− 80) 11. 0.016
Ad = =
2 2
Given figure is shown below,
Ad = 80.099
+15 V
Common mode gain,
AC = A+ + A− = 80.198 + (− 80) = 0.198 I Csat 5K
Ad
CMRR = +
Ac 10 K IB
V = 0.8
80.099 +
∴ CMRR = = 404.54 VBEsat = 0.8 V0 = VCEsat = 0.2
0.198 + 8V
R -
Hence, the correct option is (A). -
- -
+ 10 V
10. (A)
Small signal equivalent circuit is given by,
Assuming the transistor to be in saturation,
taking
+ S
Vsg 2 V0 = VCEsat = 0.2 V
Vin –
M2
VBEsat = 0.8 V
g m ⋅Vsg
2 2 r02
A Vout Applying KCL at node V,
g m ⋅ Vgs 0.8 − 8 0.8 + 10
1 1
+ + IB = 0
Vin M1 r01 10 R
+
Vgs − 7.2 R + 108 + 10 RI B = 0
1
–
7.2 R − 108
IB = …(i)
Vgs1 = Vg1 − VS1 = Vin − 0 = Vin 10 R

Vsg2 = Vs2 − Vg2 = 0 − Vin = −Vin 15 − V0 15 − 0.2 14.8

I Csat = = = …(ii)
5 5 5
Apply KCL + Ohm’s law at node A
0 − Vout V −0 For the transistor to be under saturation,
g m2 × Vsg2 + = g m1 .Vgs1 + out βI B ≥ I Csat
r02 r01
Given, β = 50
1 1 
− g m2Vin − g m1 .Vin = Vout  +  From equation (i) and (ii), for saturation,
 r0 r0 
 1 2 
 7.2 R − 108  14.8
 r0 + r02  50  ≥
−Vin ( g m1 + g m 2 ) = Vout  1  10 R  5
 r0 × r0 
 1 2  180 R − 2700 ≥ 14.8R
 r0 × r02  165.2 R ≥ 2700
V0
= −( g m1 + g m2 )  1  2700
Vin  r0 + r0 ∴ R≥
 1 2  165.2
 5.36 Paramount 1111 [EC] GATE ACADEMY®
∴ Minimum value of R for the transistor 10 − 5k × I + 7.5 = 0
to be in saturation 5k × I = 10 + 7.5
Rmin = 0.0163 kΩ 17.5
I= = 3.5 mA
Hence, the correct answer is 0.0163 kΩ . 5k
12. 15.9 ∴ I = 3.5mA
Let, V0 = Vm sin ωmt Hence, the correct answer is 3.5 mA.
Slew rate is given by, 14. 7.51
dV0
S= = Vm ωm Circuit shown in below figure,
dt max Ri = 150 Ω
S = 2πf mVm Ii IL +
IZ
0.5 V
S= −6
= 2π×100 ×103 × V0(max)
10 Vi = 60 V +– VZ RL VL
V0(max) = 0.796 V
V0(max) –
 Gain =
Vi VZ = 15.4 V
V0(max) 0.796 I Z (min) = 15 mA
∴ Vi = = = 15.9 mV
Gain 50 PZ (max) = 4 W
Vi = 15.9 mV
Maximum power dissipated across the Zener
Hence, the maximum input signal to get
diode is,
undistorted output should be 15.9 mV.
PZ (max) = VZ I Z (max)
13. 3.5
Drawing the equivalent circuit of Op-Amp, we PZ (max)
I Z (max) =
get VZ
5 kW
4
– I Z (max) = = 0.25974 A
15.4
– – I Z (max) = 259.74 mA
Applying KVL, in the above circuit,
Where, 'Vd ' is the difference voltage. −Vin + Ii Ri + Vz = 0
10 Vin − Vz
V0 = AOLVd × I in =
10 + 5 Ri
Given that, V0 = 50 Volts
60 − 15.4
10 I in = = 297.33 mA
50 = 10Vd × 150
15 I in = I z (min) + I L (max) …(i)
50 ×15
Vd = = 7.5 Volts I in = I z (max) + I L (min) …(ii)
10 ×10
KVL at the input side, From equation (i),
10 − 5k × I + Vd = 0 I L (max) = I in − I z (min)
GATE ACADEMY® Analog Electronics 5.37

I L (max) = 297.33 − 15 2Vy − 2Vi + Vy − 2 = 0

I L (max) = 282.33 mA 3Vy = 2Vi + 2
From equation (ii), 2Vi + 2
Vy =
I L (min) = I in − I z (max) 3
I L (min) = 297.33 − 259.74 In case of upper threshold voltage, the non-
inverting terminal is greater than inverting
I L (min) = 37.59 mA
terminal.
The value of maximum load resistance, i.e., Vx ≥ Vy
V 15.4
RL (max) = Z = 2Vi + 2
I L (min) 37.59 ×10−3 2≥
3
RL (max) = 409.68 Ω
So that, Vi ≤ 2
The value of minimum load resistance,
Hence, the correct option is (B).
V 15.4
RL (min) = Z = 16. (A)
I L (max) 282.33 ×10−3
Small signal equivalent circuit is given by,
RL (min) = 54.55 Ω
RL (max) 409.68
The ratio of, = R2
RL (min) 54.55
Vout
RL (max) A g m ⋅Vgs
= 7.51
RL (min)
R1 +
Hence, the correct answer is 7.51.
– Vgs
15. (B) Vi n
Vin
Given circuit is shown below,
Here, Vgs = Vg − Vs = 0 − Vin = −Vin
Apply KCL + Ohm’s law at node A.
0 − Vout Vout − Vin
= + g m ⋅ Vgs
R2 R1
Vin V V
− g m ⋅ Vgs = out + out
R1 R1 R2

For upper threshold voltage, output is

Vin  R + R2 
+ g m ⋅ Vin = Vout  1 
V0 = 10 V.
R1  R1 ⋅ R2 
10 × 5 Vout  R1 ⋅ R2   1 
Vx = VUTP = = 2V =  ⋅  + gm 
25 Vin  R1 + R2   R1 
Apply KCL at node V y , Vout  1
AV = =  g m +  ⋅ ( R1  R2 )
Vy − Vi Vy − 2 Vin  R1 
+ =0
10 20 Hence, the correct option is (A).
 5.38 Paramount 1111 [EC] GATE ACADEMY®

17. 4.98 82
rz = = 4.98 Ω
16.441
Given : Unregulated supply change by 1.5 V
Hence, the incremental resistance of Zener
82 W
Vz
diode is 4.98 Ω .
: Method 2 :
VS V0
When both input and output voltage are variable
I rz
then dynamic Zener diode resistance is given
by,
: Method 1 : ΔV × r
ΔV0 = in z
Apply KVL in the input circuit, RS + rz
VS = 82 I + I ⋅ rz + Vz 1.5 × rz
86 ×10−3 =
Let VS = VS1 , I = I1 82 + rz

VS1 = 82 I1 + I1 ⋅ rz + Vz …(i) rz = 4.98 Ω

Hence, the incremental resistance of Zener
Let VS = VS 2 , I = I 2
diode is 4.98 Ω .
VS2 = 82 I 2 + I 2 ⋅ rz + Vz …(ii) 18. 4.938
Apply KVL across output, Given :
V0 = I ⋅ rz + Vz
Let V0 = V01 , I = I1
V01 = I1 ⋅ rz + Vz …(iii)
Let V0 = V02 , I = I 2
V02 = I 2 ⋅ rz + Vz …(iv)
Subtract (iii) from (iv),
V02 − V01 = ( I 2 − I1 ) rz ..Method 1..
Given, V02 − V01 = 0.086 V Transconductance of cascade amplifier is given
0.086 by,
Hence, = I 2 − I1 …(v) ∂I out
rz = g m [ cascade] = α [CB] × g m [CE]
∂Vin
Subtract (i) from (ii),
Cascade amplifier is a combination CE – CB
VS2 − VS1 = 82( I 2 − I1 ) + rz ( I 2 − I1 )
configuration.
82 × 0.086 rz × 0.086 Q2 = CB configuration
VS2 − VS1 = +
rz rz Q1 = CE configuration
 82 + rz  g m [CE ] = Transconductance of CE transistor
1.5 = 0.086  
 rz  i.e. Q1 = g m1
17.44 rz = 82 + rz α[CB] = Current gain of CB transistor
16.441 rz = 82 i.e. Q2 = α 2
GATE ACADEMY® Analog Electronics 5.39

β2 80 19. 8.56
Hence, g m = × g m1 = ×5
1 + β2 1 + 80
Given :
 β2  (i) g m = 42 mA/V , β = 90
 α 2 = 
 1 + β2  (ii) Cμ = 3 × 10−13 F , Cπ = 4.8 × 10−13 F
g m = 4.938 mA/V Unity gain frequency is given by,
∂I out gm
Hence, the value of is 4.938 mA/V. fT =
∂Vin 2π (Cμ + Cπ )

..Method 2.. 42 ×10−3

fT =
I E 2 = I B 2 + IC 2 2π(3 ×10−13 + 4.8 ×10−13 )
42 ×10−3
 1  IC 2  fT = = 0.856 ×1010 Hz
IE2 = I C 2 1 +   I B 2 =  2π(7.8) ×10−13
 β2   β2 
fT = 8.56 GHz
I out Hence, the value of unity gain frequency ( fT )
IC 2
is 8.56 GHz.
IB2
VB Q2 20. 10.63

IE2 Given : λ = 0.1V −1 , VDS = 0.5V , I D = 1mA

I C1 MOSFET is working in the saturation region
I B1
Q1 1 W 
Vin I D = μ nCox   (VGS − VTH ) 2 (1 + λVDS )
2 L
I E1
I D ∝ (1 + λVDS )
I D1 1 + λ VDS1
 1 =
From figure, I C1 = I E 2 = I out 1 +  I D2 1 + λ VDS2
 β2  1 + λ VDS2
( IC 2 = I out ) I D2 = × I D1
1 + λ VDS1
∂I C1 ∂I 1 + 0.1×1 1.1
Now, = g m1 = E 2 I D2 = 1× = = 1.047 mA
∂Vin ∂Vin 1 + 0.1× 0.5 1.05
∂I out  1 So, the output impedance of the device,
g m1 = 1 + 
∂Vin  β2  ΔVDS VDS2 − VDS1 0.5
r0 = = = kΩ
ΔI D I D2 − I D1 0.047
 β  ∂I
g m1 ×  2  = out r0 = 10.63kΩ
 β2 + 1  ∂Vin
Hence, the value of device output impedance is
∂I out
= 4.938 mA/V 10.63 kΩ .
∂Vin
21. 397.5
∂I
Hence, the value of out is 4.938 mA/V. Given : VCC = 12 V
∂Vin
 5.40 Paramount 1111 [EC] GATE ACADEMY®
VCC 22. 8
VCE = = 6 V , β = 49 and VBE = 0.7 V
2
W  W 
12 V Given :   =   = 5
 L 1  L 3
8R ( I C + I B ) W  W 
IB RB   =   = 10
IC  L 2  L 4
+
All the transistors are operating in the saturation
VCC
VCE = = 6V region,
2
- 1 W 
I D = μ nCox   (VGS − Vth )2
R ( IC + I B ) 2 L
W
ID ∝
L
VCE > VCE ( sat ) : Transistor operate in active [ VGS and other parameters are constant]
regions.
W 
Applying KVL through C-E, I D2  
=  L 2
12 − ( I C + I B )8R − 6 − ( I C + I B ) R = 0 I D1  W 
 
9 R( I C + I B ) = 6  L 1
10 × I D1
R( IC + I B ) = 0.667 I D2 = = 2 I D1 = 2 × 2 = 4 mA
5
R(1 + β) I B = 0.667 ( I C = βI B ) …(i)
I D3 = I D2
Applying KVL through B-E
W 
12 − 8R( I C + I B ) − I B RB I D3  
 L 3
=
− 0.7 − R( IC + I B ) = 0 I D4  W 
 
11.3 − 9 R( I C + I B ) = I B RB  L 4
10 × 4
11.3 − 9 R(1 + β) I B = I B RB …(ii) I D4 = = 8 mA
5
From equation (i), (ii), Hence, the correct answer is 8 mA.
11.3 − 9 × 0.667 = I B RB 23. (B)
I B RB = 5.297 …(iii) VD D = 1.8 V
From equation (iii) and (i),
I B RB 5.297 RD 1kΩ
=
R(1 + β) I B 0.667
20kΩ
RB 5.297 (1 + β)
= = 2.3 × 50 IG = 0 A W  5
R 0.667 M1   =
+  L  0.18
RB VG S −
= 397.5
R RS 200 Ω
R
Hence, the value of B = 397.5
R
GATE ACADEMY® Analog Electronics 5.41
Applying KVL in the above circuit, MOSFET is in the saturation region,
−VDD + RD I D + VGS + I D RS = 0 2I D
VGS = V TH +
−1.8 + 1× I D + VGS + 0.2 I D = 0 W 
μ nCox  
L
VGS = 1.8 − 1.2 I D …(i)
2 × 0.5
1 W  = 0.4 +
I D = μ nCox  2
 (VGS − VTH ) …(ii) 20
2 L  200 ×10−6 ×
0.18
1
I D = × 100 × 10−3 VGS = 0.4 + 0.212
2
500 VGS = 0.612 V
× (1.8 − 1.2 I D − 0.5) 2
18 1
VGS = × 0.5 × R2
25 10
I D = (1.3 − 1.2 I D ) 2
18 [From the question current flow through R2 is
2
0.72 I D = (1.3 − 1.2 I D ) 1
ID ]
2
0.72 I D = 1.69 + 1.44 I − 3.12 I D
D
10
1
1.44 I D2 − 3.84 I D + 1.69 = 0 0.612 = R2
20
(2.11 mA not possible this R2 = 12.242 kΩ

I D = makes VGS < 0)
0.556 mA Applying KVL across the dotted line,

ID 11
So, I D = 0.556 mA −VDD + R1 + VGS + I D × 0.2 = 0
10 10
Hence, the correct option is (B). R1 I D 11
= 1.8 − 0.612 − I D × 0.2
24. 33.8 10 10
R1
Given : μ n Cox = 200 μA / V 2 = 1.188 − 0.11
20
W 20
= , I D = 0.5mA , λ = 0 , VTH = 0.4 V R1 = 21.57 kΩ
L 0.18
VD D = 1.8 V Hence, R1 + R2 = 21.57 + 12.24

R1 500 Ω
R1 + R2 = 33.8kΩ
D Hence, the correct answer 33.8 kΩ.
+G
25. 4.3
R2
VGS Given : Vγ = 0.7 V for each diode,
ID
10
− S 1st we assume D1 and D2 forward biased and
200 Ω D3 is reverse biased equivalent circuit is shown
in the below figure.
 5.42 Paramount 1111 [EC] GATE ACADEMY®

I 9.5 kW V0 VD 2 = − 0.7 V
V0
+
0.7 V I2 VD 2 < 0.7 V
-
+
+ 0.7 V O.C. So, diode D2 remain in reverse biased our
10 V -
- I1
assumption is true
0.5kW 5V 5V Hence, V0 = 4.3V
Hence, the correct answer is 4.3 V.
V0 = 0.7 + 5 = 5.7 V 26. 1.35
10 − 5.7 Given : VBE = 0.65 V
I= = 0.4526 mA
9.5
As β is very high, I B is negligible.
From KCL at Node V0 ,
I = I1 + I 2
10 − 5.7 5.7 − 0.7
= + I2
9.5 0.5
∴ I 2 = − 9.5474 mA
i.e. in diode D2 current I 2 flows from n to p,
which is not possible so, our assumption is
wrong.
Now we assume diode D1 and D3 is forward
By using voltage divider rule,
biased and D2 is reverse biased
10 × 2
9.5kW I VB = = 2V
V0 2+3+ 5
I1 I2
For transistor Q1 ,
+ + –
+ 0.7 V VD 2 O.C. 0.7 V VB − VBE 2 − 0.65 1.35
– 10 V – – + I E1 = = =
0.5 kW 5V 5V
1kΩ 1kΩ 1kΩ
I E1 = 1.35 mA

V0 = 4.3V Since, base current is zero,

I = I E1 = 1.35 mA
Applying KCL at node V0 ,
Hence, the correct answer is 1.35 mA.
I = I1 + I 2
27. (A)
10 − 4.3 4.3 − 0.7
= + I2
9.5 k 0.5 k Consider circuit in transform domain,
1
0.6 m = 7.2 m + I 2 CS V ( S )
NI
Vs ( s )
I 2 = − 6.6 mA
R +
V0
So, I 2 is opposite what we assumed before, -
Applying KVL in loop 1 1 VI ( S )
− 5 + 0.7 + VD 2 + 5 = 0 C1 S C2 S
GATE ACADEMY® Analog Electronics 5.43
Applying KCL at non inverting terminal 28. (C)
VNI ( s ) − VS ( s ) VNI ( s )
+ =0 10 kW
1 R
CS + +
D1
R D2
VNI ( s ) = Vs ( s ) Vi 10 kW V0
1
R+ 10 V
SC – –
Applying KCL at inverting terminal
Assume Vi > 0 V then D1 is ON, and consider
VI ( s ) VI ( s ) − V0 ( s )
+ =0 D2 is reverse biased
1 1
SC1 SC2 10 1
V0 = × Vi = Vi
10 + 10 2
 1 
 SC1  S .C 10 kW
VI ( s ) =   V0 ( s )
 1 + 1  + +
 SC SC 
 1 2  D2
Vi 10 k V0
For an ideal op-amp voltage at both the terminal 10 V
are same - -
VI ( s) = VNI ( s)
Diode D2 is remain in reverse biased until
 1  V0 ≥ 10 V
 SC1  R
  V0 ( s ) = V ( s) 1
 1 + 1  1 s Vi ≥ 10
 SC SC  R + 2
 1 2  SC
Vi ≥ 20 V
V0 ( s)  C1  s 
= 1+
Vs ( s)  C2 
 s + 1
 Hence Diode D2 get forward biased when

 RC  Vi ≥ 20 V .
V0 ( s )  C1  s  10 kW
T (s) = = 1+
Vs ( s )  C2 
 s + 1

+ +

 RC  S .C
10 kW
T ( s = 0) = 0 Vi V0
10 V
C1 - -
T ( s = ∞) = 1 +
C2
V0 = 10 V
This circuit passes high frequency signal and
Hence, the correct option is (C).
stops low frequency signal, so it is a high pass
filter. 29. (A)

Hence, the correct option is (A). Small signal equivalent circuit is given by,
 5.44 Paramount 1111 [EC] GATE ACADEMY®

30. 78.75
R1
+
I Vgs2 I1 10 mA
lg = 0
Vg 2 – VD2
M2
I g m2 ⋅Vgs2 +
R2 7 mA VD1
D1
Vout + –
VD2 D2
gm1 ⋅Vgs1 – +
Vin M1 0V V
+ I 2 = 3 mA
Vgs1 –
–

I D1 = 3mA → Q1 : FB
By using voltage divider rule I D2 = 10 m − 3m = 7 mA → Q2 : FB
R1
Vg2 = ⋅ Vout I 0 ∝ (Junction Area)
R1 + R2
D1 has 10 times the junction area of D2 .
Vsg2 = Vs2 − Vg2
A1 = 10 A2
R1 ⋅Vout
Vsg2 = 0 − where, I 0 = Reverse saturation current.
R1 + R2
I 01 ∝ A1 and I 02 ∝ A2
R ⋅V
Vsg2 = − 1 out I 01 A1 10 A2
R1 + R2 = = = 10
I 02 A2 A2
Apply KCL + Ohm’s Law at node A.
I 01 = 10 I 02
V
g m2 ⋅Vsg2 = out + g m1 ⋅Vgs1 By using KVL, V = VD2 − VD1
R1 + R2
Vgs1 = Vin − 0 = Vin I 
VD = ηVT ln  D 
 I0 
 − R ⋅V  Vout
g m2  1 out  = R + R + g m1 ⋅Vgs1 Here, multidiode circuit η = 1
 R1 + R2  1 2
 ID 
 1 + g m2 .R2  VD2 = VT ln  2 
− g m1 ⋅Vin = Vout    I0
 2 
 R1 + R2 
 ID 
V VD1 = VT ln  1 
Voltage gain AV = out  I0
Vin  1 

− g m 1 ⋅ ( R1 + R2 ) V = VD2 − VD1
AV =
1 + g m2 ⋅ R2  ID   ID 
V = VT ln  2  − VT ln  1 
 I0
Hence, the correct option is (A).  2   I 01 
GATE ACADEMY® Analog Electronics 5.45

 I D I0  IZ
V = VT ln  2 × 1  0.12 V
 I0 I D  0
 2 1 

5 mA
 7m 
V = 25 m ln  × 10  = 78.75 mV
 3m 
Hence, the value of V results is 78.75 mV. 35 mA
31. 30.10
From the characteristics of Zener diode, we can
Given : Open loop gain = 106 see that is practical Zener diode
Bandwidth = 8 Hz VZ VZ
+ – rZ
Closed loop amplifier bandwidth = 250 kHz = +–
We know that,
ΔVZ 0.12
Gain bandwidth product (GBW) = Constant rZ = = ×103 = 4 Ω
ΔI Z (35 − 5)
∴ (GBW)open loop = (GBW)closed loop
∴ VL = VZ + I Z rZ
106 × 8 = ACL × 250 kHz
Also from characteristic figure (a) till 5 mA
ACL = 32 Zener diode is Reverse biased but is not in
ACL dB = 20 log 32 = 30.10 dB breakdown.
Hence, the maximum allowed gain that the So, I Z (min) = 5 mA and I Z (max) = 35 mA
amplifier can have is 30.10 dB. VL (max) = 10 + 35(10−3 ) × 4
32. (C) = 10.14 Volts
For a three stage cascade amplifier, overall VL (min) = 10 + 5(10−3 ) × 4
midband gain is given by,
= 10.02 Volts
64000 = A0 × A0 × A0
ΔVL = VL (max) − VL (min)
A0 = (64000)1/3
ΔVL = 10.14 − 10.02 = 0.12 Volts
A0 = 40
Hence, the correct option is (C).
Lower 3-dB frequency n-identical of multistage
34. (D)
amplifier is given by,
fL Given circuit consists diodes D1 , D2 and D3
f L* = where n = 3
1/ n
2 −1 connected in parallel and identical.
fL ∴ VD1 = VD2 = VD3
20 =
1/3
2 −1 We know, from diode equation.
f L ≈ 10 Hz I D = I S eV0 / ηVT
Hence, the correct option is (C). I 
∴ VD = ηVT ln  D  …(i)
33. (C)  IS 
Given diode characteristics is shown in below Saturation current I S in a pn-junction diode is
figure, given by,
 5.46 Paramount 1111 [EC] GATE ACADEMY®
AqD p pno AqDn n p0 ηVT
IS = + rd =
Lp Ln I DDC
∴ I S ∝ A & VD1 = VD2 = VD3 As η is not given take η = 1
VT V
 ID   ID  rd = = T
So, ηVT ln  1  = ηVT ln  2  I DDC I
 IS   IS 
 1  2 
AC equivalent circuit is given by,
ID IS A
∴ I D1 = 2 × I S1 and 1 = 1
I S2 I S2 A2
OC
A 
Then, I D1 = I D2  1  …(ii) Rs SC SC
 A2 
IS +
ID A
Similarly, I D3 = 2 × I S3 and 3 = 3 vs +
– rd V0
I S2 I S2 A2 –
A 
I D3 = I D2  3  …(iii)
 A2  rd
V0 = ⋅ vs
Now by KCL, I in = I D1 + I D2 + I D3 Rs + rd
Substituting values from equation (ii) and (iii) It is given that v0 become one-half of vs
A  A  v0 1
I in = I D2  1  + I D2 + I D2  3  =
 A2   A2  vs 2
A A  1 rd
I in = I D2  1 + 1 + 3  =
 A2 A2  2 rd + Rs
I in rd + Rs = 2r2
I D2 =
A1 A3 rd = Rs
1+ +
A2 A2
VT
Hence, the correct option is (D). = Rs
I
35. 25 V
I= T
DC equivalent circuit is given by Rs
25 mV
I=
I 1k
Rs OC
I = 25 μA
Hence, the correct answer is 25 μA.
I DDC
36. 20
vs +
– +
Vg
– Given : Input voltage Vi = 10sgn (sin πt )
Vi = 10; sin πt > 0
Current, I DDC = I Vi = −10; sin πt < 0
GATE ACADEMY® Analog Electronics 5.47
The input voltage waveform can be drawn as −10 × 5 −50
∴ V0 = =
5 + RB 5 + RB
 T 
V0 (positive half cycle) × 2 
–2 –1 3  
 + V (negative half cycle) × T 
 0 2 
Vavg (output) = 
sgn[ x] T
50
1 10 × 1 − ×1
5 + RB
x 4=
-1 2
50
8 = 10 −
RB + 5
50
=2
RB + 5
RB + 5 = 25

The given diode circuit is RB = 20 Ω

D Hence, the correct answer is 20 Ω.
37. 83.26
Vi RB 5Ω V0 First we will perform ‘DC’ analysis of the
circuit. So during ‘DC’ analysis all the capacitor
will behave as open circuit.
Now, during positive half cycle from VCC
0 < t < 1sec .
Diode ‘D’ is ON and RB is shorted 0.5 mA
S.C. 5 kW
V0 V0

10 5Ω

0.25 kW
Therefore, V0 = 10 Volts .
During negative half cycle, Vi = −10 V . Hence,
I E = IC + I B = 0.5 mA
diode ‘D’ OFF
IE
IB = = 0.0049 mA = 4.9 μA
β +1
+
I C = βI B = 0.49 mA
IC
Now, gm = = 19.6 mA/V
– VT
 5.48 Paramount 1111 [EC] GATE ACADEMY®
VT 20 log ACL = 20 dB
rπ = = 5.102 kΩ
IB
ACL (close loop gain) = 10
The equivalent AC model of the circuit is
B 5K ACL = 10
A
Vi V0
+ Faithfully amplifying signal from 10 to 20 kHz
rp Vp g mVp 30 K
- So, f m = 20 kHz
VP
P S .R.
Vm =
0 × 25 K 2π× f m × ACL

0.5 ×106 5
Vm = =
Applying KCL at node A 3
2π× 20 ×10 ×10 4π
V0 − Vi V Vm = 397.88 mV
+ g mVπ + 0 = 0 …(i)
5 30
Hence, the correct answer is 397.88 mV.
Apply KCL at node P,
VP Vπ 39. 0.2
− − g mVπ = 0
0.25 rπ 0.4
Given : A = 103 , dA = 10 , β = 0.4% =
Vi − Vπ  Vπ  100
=  + g mVπ  …(ii) + Amplifier
0.25  rπ  Input Output
103 ± 10
–
 1 
Vi = 0.25  3
+ 19.6 × 10− 3 Vπ + Vπ
 5.102 × 10  Feedback
−3 factor b
Vi = 0.25 × 10 (0.196 + 19.6)Vπ + Vπ
Vi ≅ Vπ Sensitivity can be improved using negative
feedback, by a factor (1 + Aβ) ,
Put this in equation (i) we get,
S
1 1   1 i.e., Sf =
V0  +  + Vi  g m −  = 0 1 + Aβ
 5 30   5
V0 0.233 + Vi (19.6 − 0.2) = 0 % Change in gain of feedback amplifier,
dAf 1 dA
V0 (0.233) + Vi ×19.4 = 0 %= × ×100
Af 1 + Aβ A
V
Voltage gain = 0 = −83.26 dAf 1 10
Vi (%) = ×100
Af 3 4 10 3

V0 1 + 10 ×
= 83.26 1000
Vi
dA f 1 103 1
(%) = × 3 =
V0 Af 5 10 5
Hence, the value of voltage gain is 83.26.
Vi
dAf
(%) = 0.2
38. 397.88 Af
Given : S .R. = 0.5 V/μsec , Gain = 20 dB Hence, the correct answer is 0.2.
GATE ACADEMY® Analog Electronics 5.49

40. – 0.5 Similarly, V2 = 0.75 V

The given circuit can be redrawn as, Hence, the value of V1 + V2 is – 0.5 V.
41. 1.04
2.5 V
+ –
– + NMOS
(W/L)n

VI V0
10 kW
PMOS
(W/L)p

– 2.5 V
+
–
– For NMOS, VD = 2.5 V
+
and VG = 2.5 V
State of As VD = VG = VI = 2.5V
Input Output
diode
So, VDS = VGS
V D1 → RB V
−2V < in < 1V V0 = in ∴ VDS > VGS − Vt
2 D2 → RB 2
−4V < Vin < 2V (As Vt is positive for NMOS)
Vin D1 → FB V0 = 1 V VD = 2.5V
> 1V
2 D2 → RB
Vin > 2V VG = 2.5 V
Vin D1 → RB V0 = −2 V VS = V0
< −2V
2 D2 → FB So, NMOS is in saturation,
Vin < −4V VGS = 2.5 − V0
Transfer characteristics, VD = 2.5V
The condition for NMOS for saturation,
VDS > VGS − Vt and VGS > Vt
2.5 − V0 > 1
V0 < 1.5V …(i)
Now, for PMOS,
As slope of transfer characteristics during VS = V0
1
− 4 < Vin < 2 V is
2
VG = VI = 2.5 V
Vin = −2.5Volt
−2.5 VD = − 2.5 V
∴ V0 = V1 = = −1.25 V
2 VSG = V0 − 2.5
 5.50 Paramount 1111 [EC] GATE ACADEMY®

For PMOS to be in ON state, VSG > Vt . 42. (B)

V0 − 2.5 > 1 By small signal model of BJT using rπ model,
V0 > 3.5 V → NOT possible as NMOS has
 Both transistor have same g m they will
already in saturation. So PMOS is OFF.
have same rπ , the above figure can be
W
μ n Cox simplified to below figure,
ID = L (2.5 − V − 1) 2
2
0
rπ
Vin − ib − (ib + 2βib ) RE = 0
1 2
I D = (1.5 − V0 ) 2 …(ii)
2 Vin rπ
= + (1 + 2β) RE
V ib 2
and given I D = 0 mA …(iii)
10
ib
From equation (ii) and (iii),
+
V0 1 rp 2bib
= (1.5 − V0 ) 2 Vin 2
10 2 –

V0 1 RE
= ((1.5)2 + V02 − 2(1.5)V0 )
10 2
V0 1
= (2.25 + V02 − 3V0 )
10 2
V0 = 5(2.25 + V02 − 3V0 )
∴ 5V02 − 16V0 + 11.25 = 0 Vin +
–
rp rp
V01 = 2.156 and V02 = 1.043 bib bib

As V0 < 1.5 , V01 is neglected.

So, V0 = 1.043V RE

Hence, the correct answer is 1.04 V.

 Key Point Vin rπ + 2(1 + 2β) RE
NMOS : =
ib 2
Linear, VGS > Vt and VDS < VGS − Vt
β β
Saturation, VGS > Vt and VDS > VGS − Vt gm =  rπ =
rπ gm
PMOS :
β
Linear, VSG > Vt and VSD < VSG − Vt Ri = + (1 + 2β) RE
2 gm
Saturation, VSD > Vt and VSD > VSG − Vtp Hence, the correct option is (B).
Important to note when MOSFET is in
43. 11.266
saturation it has already satisfied the first
condition of linearity. If condition for linearity For dc analysis capacitor acts as open circuit
fails then MOSFET is OFF and in cut-off mode equivalent circuit is shown in figure,
and can be treated as open circuit. RB = R1 + R2 = 200 kΩ
GATE ACADEMY® Analog Electronics 5.51

MT1 is in saturation. (Drain is connected to gate)

I B + IC = I E RC +
R1 R2
VCC
–
18 V For MT2 , VDS = V0
R1 + R2 = RB VDS > VGS − VT
IB VGS = V0
+
VBE – IE MT2 is saturation. (Drain is connected to gate)
RE Current I 0 is same in both transistor,
1 W 
μ nCox   [3 − V0 − 1]2
Applying KVL, 2  L  MT1
−VCC + I E RC + I B RB + VBE + I E RE = 0 1 W 
= μ nCox   [V0 − 1]2
I E = (1 + β) I B 2  L  MT2
I B RB + (1 + β) I B ( RC + RE ) = VCC − VBE (2 − V0 ) 2 = (V0 − 1) 2
VCC − VBE
Then, I B = ∴ 2 − V0 = ±(V0 − 1)
RB + (1 + β)( RC + RE )
Take positive sign,
18 − 0.7
IB = ∴ 2 − V0 = V0 − 1
(80 + 120) + 76 (2 + 0.5)
3
17.3V 17.3 So, V0 = V
IB = = mA 2
200 kΩ + 190 kΩ 390
Now, take a negative sign,
I B = 0.0443 mA = 44.3 μA
2 − V0 = − V0 + 1
I E = (1 + β) I B
(equation does not satisfy)
I E = 76 × 44.3 μA = 3.36 mA 3
Finally, V0 = V
VC = VCC − I E RC 2
VC = 18 − 3.36 × 2 = 11.266 V By taking MT2 ,

The value of DC level of collector voltage VC 1 W 

I 0 = μ n Cox   [V0 − 1]2
is 11.266. 2  L  MT2
2
44. 7.5 1 1 30
I 0 = 30 × 2  = = 7.5 μA
V0 2 2 4
I0
Hence, the value of I 0 is 7.5 μA.
MT1 MT2
45. 2.5

3V

For MT1 , VDS = 3 − V0

VDS > VGS − VT [ VGS = VDS ] t (sec)
 5.52 Paramount 1111 [EC] GATE ACADEMY®

-
C
+
Step 5 : If V + > V − (Positive feedback) and
V − > V + (Negative feedback).
R = 150 kW + 15 V 1k
Vi -
V0 +15 V
1k V−
+
-15 V V0 = ΔV
V+
−15 V
+
V
The above given circuit is integrator using Op- 1k ΔV
Amp, 2k
t
1
V0 = − 
RC 0
Vi (t ) + Vc (0− )
2 2
−
V+ = × ΔV = ΔV and
Vc (0 ) = 0 V 2 +1 3
(∴ Capacitor is initially relaxed) 1 ΔV
V− = × ΔV =
1
t 1+1 2
RC 0
V0 = − Vi (t ) dt + −
Here, V > V . Hence, positive feedback.
1 Dominating negative feedback and Vout will be
Vi (t ) = t Volt
2 ± 15 V and virtual ground concept will not be
As output get saturated at time t = 150sec applicable.
−1
150
1 So, V0 = ±15 V
−15 =
150C  2 t dt
0
Hence the correct answer is (D).
1 1 47. 2.5
15 = × 150 ×150
150C 4 R2
150 150 R1
C= = = 2.5 mF -
60 60 +
Vout

Hence, the value of capacitor ‘C’ is 2.5 mF. C1 = 2 mF

46. (D)
R3 = 20 kW
In the given Op-Amp circuit, both positive and C2 = 4 mF R4 = 40 kW

negative feedback are presents. So, we need to

check which feedback is dominating.
Steps to indentity overall feedback.
Step 1 : Null all the external sources i.e. The above given circuit is Wien bridge
Vin = 0 V (SC) and Iin = 0 A (OC) oscillator for Wien bridge oscillator frequency
and gain ( R2 / R1 ) is given by,
Step 2 : Disconnect the output.
Step 3 : Assume small positive output i.e. 1
f = …(i)
V0 = ΔV . 2π R3 R4C1C2
Step 4 : Find V + and V − at non-inverting R2 R3 C2
and = + …(ii)
terminal and inverting terminal respectively. R1 R4 C1
GATE ACADEMY® Analog Electronics 5.53

R2 20 k 4μF The given circuit changes to,

= +
R1 40 k 2μF
I
R2 1
= + 2 = 2.5 +
R1 2 10sin wt 2.4 W
volts –
R 
Hence, the value of ratio  2  is 2.5.
 R1 
Vavg Vm 1 10
48. 1.326 I avg = = × =
2.4 Ω π 2.4 2.4 π
Given circuit is as shown below,
N = 1.326 A
A
Hence, the correct answer is 1.326 A.
I
4W 1W 49. 40
+
10sin wt Given circuit is a biased clamper circuit.
volts – 5W
8W 2W During negative cycle, Vin = −20 V , diode D is
forward biased, so output is connected across 5
B
Given, the diode used is an ideal diode. The V.
average current to be delivered to network ‘N’ V0 = 5V (Minimum voltage)
can be obtained by calculating Thevenin’s Equivalent circuit is shown in below figure,
equivalent across AB using the circuit shown Vc
below
A + + – +
4W 1W S.C.
Vin 1MW V0
5W 5V
8W 2W – –
B
Applying KVL, − Vin + Vc + 5 = 0
Rth

The network in above figure is a balanced Vc = Vin − 5 = −20 − 5 = −25 V

bridge. So, the network becomes as shown Capacitor gets charged by – 25 V during
below negative half cycle.
A
During the positive half cycle, Vin = 10 V
4W 1W
Diode is OFF,
0.1mF
8W 2W
+ +
B

Rth Vin 1MW V0

5V
12 × 3
Rth = 12 || 3 = = 2.4 Ω – –
12 + 3
 5.54 Paramount 1111 [EC] GATE ACADEMY®
Capacitor try to discharge through 1 MΩ β 150
rπ = = = 7.5 kΩ
resistor, so time constant g m 20 × 10−3
RC = 0.1×10−6 ×106 From equation (i),
RC = 0.1 sec 1
fβ =
From figure, frequency of input f = 1000 Hz , 2πrπ (Cπ + Cμ )
so time period T = 10− 3 sec and negative half 1
=
T 2π× 7.5 × 10 (2 + 0.3) × 10−12
3

cycle remains for = 0.5 ×10− 3 sec

2 fβ = 9.226 MHz
T Hence, the correct answer is 9.226 MHz.
As RC >>
2 51. (C)
So discharging of capacitor will not take place.
By KVL, Given : VGEsat = 0.2 V and VBEsat = 0.7 V
−Vin + Vc + V0 = 0 Transistor is in saturation (given)
+ 10 V
V0 = −Vc + Vin = −(−25) + (10) = 25 + 10
I Csat
V0 = 35V (Maximum)
V0 1 kΩ

35 V RB IB +
+5V VCEsat = 0.2 V
+
5V 0.7 V – –
t

V0(max) + V0(min) = 5 + 35 = 40V VCC − VCE

IC =
Hence, the correct answer is 40 V. RC
50. 9.226 10 − 0.2
I Csat = = 9.8 mA
1
Given : β = 150, Cπ = 2 pF, Cμ = 0.3pF and
5 − 0.7
I CQ = 0.5 mA , VT = 25mV RB =
I Bmin
The beta cutoff frequency is given by, βactive
1 Overdrive factor, 10 =
fβ = …(i) β forced
2πrπ (Cπ + Cμ )
βmin 50
β β forced = = =5
Where, rπ = 10 10
gm IC 9.8 m
Transconductance of BJT is given by, I Bmin = set = = 1.96 mA
β forced 5
I 0.5 mA
gm = c = = 20 mA/V 5 − 0.7 4.3
VT 25 mV RB = = = 2.2 kΩ
I Bmin 1.96 m
β = g m × rπ
Hence, the correct option is (C).
GATE ACADEMY® Analog Electronics 5.55
2W
52. (D)
Given circuit is shown below, + + +
Vin (t ) 2F V0' (t ) 1F Vc (t )
– – –

RL
The waveform for Vin (t ) can be drawn
as shown below
20 − 5 Vin (t ) volts
Is = = 1.5 mA
10 kΩ
2V
Pz (max)
Given that, = 1.4 t (sec)
pz (min) 0 1 2 3

Vz I zmax -2 V
= 1.4
Vz I zmin
V0 ' (t ) = 2 u (t)
I zmax = 1.4 I zmin …(i)
2
Is = I z + IL
I s = I zmin + I Lmax t(sec)
0
I s = I zmax + I Lmin The combination of input voltage
source, diode and 2F capacitor forms a
Vz 5 positive peak detector circuit
I L(max) = = = 0.5 mA
RL(min) 10 kΩ ∴ V0 '(t ) = 2 Volts ; t ≥ 0
I s = I zmin + I Lmax The circuit can be redrawn as shown
below,
1.5 − 0.5 = I zmin
2W
I zmin = 1mA
I zmax = 1.4 × 1mA = 1.4 mA +
2u (t) volts +
– 1F Vc (t )
[From equation (i)] –

I s = I zmax + I Lmin
The above circuit is a source R.C circuit
1.5 = 1.4 + I Lmin
where u(t ) is the unit step signal
I Lmin = 1.5 − 1.4 = 0.1mA −
t
∴ Vc (t ) = 2(1 − e ) V, t ≥ 0 2
Vz 5
Now, ( RL ) max = = kΩ = 50 kΩ At t = 2sec,
( I L ) min 0.1
−2
Hence, the correct option is (D).  1
Vc (t ) = 2(1 − e 2 ) = 2  1 − 
53. 1.209  e
= 1.264 Volts
(i) Given circuit is shown in figure below
 5.56 Paramount 1111 [EC] GATE ACADEMY®

(ii) Circuit at t = 0+ is shown in figure,  4 s + 3  2 − 0.786

I (s)  =
2V 2  2 s  s
2.428
I ( s) =
2 V +–  3
2F 1F Vc ( t ) 4 s + 
 4
0.786 2.428 1
V (s) = + ×
2 F capacitor comes across the voltage s  3 s
4 s + 
source, so it can be neglected as voltage  4
across it is fixed at 2 V. ( s + 0.75) × 0.786 + 0.606
V (s) =
For 0 ≤ t < 1 sec , s ( s + 0.75 )
τ = Req C = 2 sec A B
= +
s ( s + 0.75)
VC (0+ ) = VC (0− ) = 0
0.786 × 0.75 + 0.606
VC (∞) = 2 V A= = 1.594
0.75
−t −t
VC (t ) = 2 + (0 − 2)e 2 = 2[1 − e 2 ] 0.606
B= = − 0.808
− 0.75
At t = 1− sec,
1.594 0.808
−1 Vc ( s) = −
VC (1− ) = 2(1 − e ) = 0.786 = VC (1− )
2 s ( s + 0.75)

For 1 sec < t < 2sec , Vc (t ) = 1.594 − 0.808e− 0.75t '

R (where, t ' = t − 1 )
∴ Vc (1.99sec) = 1.594 − 0.808e− 0.75×0.99
– + +
2V + Vc2 (1- ) = 2 V 2F Vc (1- ) = 0.786 V = 1.209 V
- -
Hence, the correct answer is 1.209 V.
54. – 1.41
Transform network for t = 1+ sec is shown
Open circuit test,
below, R
2W
+ VP P +

2 + + 0.786
– –
s s Vs (t ) VN N V0 (t )
I (s) +
1 1 Vb
– – –
2s s

V p = Vs (t ) and VN = Vb
Applying KVL, D : FB; VD = V p − VN > 0V
−2 0.786
+ 2 I ( s) + Vs (t ) − Vb > 0V
s s
1 1 Vs (t ) > Vb
+ × I ( s) + × I ( s) = 0
s 2s Diode act as a short circuit.
GATE ACADEMY® Analog Electronics 5.57

Hence, V0 (t ) = Vb = 2.5 V 1
AX = 25 m − × 3.75 × 7.5 m
D : RB : VD ≤ 0 V 2
AX = 10.9375 m
Vs (t ) ≤ VB = Diode act as open circuit
Total Area = AX + AN
Hence, V0 (t ) = Vs (t )
Total area = 10.9375 m + (−25m)
Vs (t )
= −14.0625 m
10 V Total Area
Average value of Vout =
Fundamental Time
t(msec)
0 5 10 −14.0625 m
-10 V
=
10 m
Voutavg = −1.40625 V  −1.41 V
Vs (t ) dy 10 Hence, the correct answer is – 1.41 V.
Slope = = =4
dx 2.5 55. 0.7077
10 V
A1 Given : α = 1
2.5 V 7.5
5
0 t1 2.5 t2
t (msec) ∴ I E = I C and I B = 0 A
10
Small signal equivalent circuit is given as,
-10 V ib
Area : Ax V0
+
1 RC
T T
Vs
Average value of Vout = V0 (t ) ⋅ dt ib
–
E
Area of V0 (t ) over a fundamental Time
Vout =
Fundamental Time re
2.5
Slope = 4 = RE
t1
t1 = 0.625 msec Req re R E
t2 = 5 − 0.625 = 4.375 msec Ceq CE

Area of positive half cycle, 1

1 f L3 dB =
Ap = × 5 m ×10 = 25 m 2πReq .Ceq
2
1
Area of Negative half cycle, f L3 dB =
2π.(re + R E ).C E
1
AN = × 5 m × (−10) = −25 m VT V 25
2 re = = T = = 25 Ω
Area of output in positive half cycle. I EDC I 1
AX = Ap − A1 Here, RE = 200 Ω , CE = 1 μF
1 1
AX = 25 m − × (t2 − t1 ) × (10 − 2.5) f L3 dB =
2 2π.(25 + 200).(1× 10 −6 )
 5.58 Paramount 1111 [EC] GATE ACADEMY®
f L3 dB = 0.7077 kHz 1m(15k  15k )
Av =
Hence, the correct answer is 0.7077 kHz. 1 + 1m × 2k
7.5
56. (B) Av = = 2.5
3
Given : g m = 1 mA/v 2 Hence, the correct option is (B).
Small signal equivalent circuit is 57. 6.32

15 kΩ RD The Zener diode in the given circuit is in reverse

SC bias condition. Assume that it is not in
V0
g mVgs breakdown.
Vg RL 15 kΩ 1 kΩ V
+ I
Vgs – Vs = Vx
g m Vgs Vi 1 kΩ
Vi Rs Vx SC I x
Vs
2 kΩ
+ OC
Vi Using voltage division rule,
Vx
– Rin =
Ix 1k Vi
V = Vi × =
2k 2
I x = − g m .Vgs
Where, Vi = 20 × [1 − e− t ]
Vg = 0v and Vs = Vx
The waveform of Vi can be drawn as shown
Vgs = Vg − Vs = 0 − Vx below,
Vgs = −Vx Vi

I x = − g m (−Vx )
Vx 1 20 V
Rin = =
I x gm
1
Rin = = 1 kΩ 0
t
gm
For Zener diode to go into breakdown region.
V0 = − g m .Vgs .( RD  RL )
V > 15 V
Vs − Vi Vi
g m .Vgs = > 15 V
Rs 2
g m .Vgs .Rs = Vs − Vi Vi > 30 V
But, Vgs = Vg − Vs = −Vs So, Vi must be greater than 30 V for the Zener
+ g m .Vgs .Rs = −Vgs − Vi diode to go into breakdown region which is not
at all possible because maximum value of Vi is
Vi = −(1 + g m .Rs ).Vgs
20 V.
V g .( R  RL )
Av = 0 = m D ∴ The Zener diode never goes into
Vi (1 + g m .Rs ) breakdown region.
GATE ACADEMY® Analog Electronics 5.59

Vi V V01 = 5 − 5V0
I= = i
1 kΩ + 1 kΩ 2 kΩ V01 + 5V0 = 5 …(i)
−t
20(1 − e ) Apply KCL + Ohm’s Law node A
I= = 10 × (1 − e − t ) mA
2 V2 − V0 V01 − V0 V0 − 0
+ =
∴ I at t = 1 sec = 10(1 − e−1 ) = 6.32 mA 10 10 10
Hence, the correct answer is 6.32 mA. V2 + V01 = 3 V0
58. 20 V0
1+ + V01 = 3 V0
Concept : 2
10 W 5
V0 − V01 = 1 …(ii)
2
10 W V2 – From equation (i),
2V 10 W A
V0 V01 = 5 − 5V0
V1 +
2V V01
10 W
I0
5
V0 − 5 + 5 V0 = 1
10 W 2
10 W
15V0
=6
1V 2
12 4
V1 V0 = = = 0.8 V
15 5
4
R1 V01 = 5 − 5 × = 1 V
5
I V1R2 + V2 R1 V0 − V0 1 − 0.8 0.2
Vx Vx = I0 = 1 = = = 20 mA
R1 + R2 10 10 10
The value of current I 0 is 20 mA.
R2 59. (C)
Let ACL be the closed loop gain of Op-Amp.
V2 dV0
Slew rate, S .R =
(2 ×10) + (1×10) dt
V1 =
10 + 10 Where 'V0 ' is the output voltage but
20 + 10 3 V0 = ACL ×Vi
V1 = = V
20 2
d dVi
(2 ×10) + (10 × V0 ) V S .R = [ ACL × Vi ] = ACL ×
V2 = = 1+ 0 dt dt
10 + 10 2
1 0.4
V01 = A0V ⋅ Vid ×106 = ACL × ×106
6 12
V01 = 10 × (V1 − V2 ) 12 2
ACL = = =5
3 V   1 − V0  6 × 0.4 0.4
V01 = 10 ×  − 1 − 0  = 10 ×  
2 2  2  Now, AOL = 10
 5.60 Paramount 1111 [EC] GATE ACADEMY®
Rf 60. (C)

Ri = 5 W Current shunt feedback is also called as current

– amplifier and it represents current sampling and
Vx
V0 shunt mixing. Due to this, it decreases input and
+ increases output impedances.
Vi
Hence, the correct option is (C).
By KCL at inv. terminal,
61. 2
Vx − 0 Vx − V0
+ =0 Given circuit is as shown below,
5 Rf
5
Vx + (Vx − V0 ) = 0
Rf
Given, AOL = 10 1k

V0
= 10
Vi − Vx
V0 = 10Vi − 10Vx
V0 Also given that β is very high
=5
Vi β=∞
10Vi − V0 5  10Vi − V0  IC
+  − V0  = 0 =∞
10 R f  10  IB
5 IB = 0 A
10 Vi − V0 + (10 Vi − V0 − 10 V0 ) = 0
Rf I E = IC
50 5 Assume that the zener diode is not in breakdown
10 Vi + Vi = V0 + (11V0 )
Rf Rf or not connected in circuit. So, the circuit
50 5 becomes as shown below
10 + = 5+ × 11× 5
Rf Rf
275 − 50
5=
Rf 1k

Rf

Ri = 5 W + 15 V
–
V0
+
2K
Vx = 10 × = 4 Volts
Vi -15 V 5K
225 As Vx > 3 Volts that is breakdown voltage of
Rf = = 45 Ω
5 zener diode  zener diode is in breakdown. So,
Hence, the correct option is (C). the circuit becomes as shown below
GATE ACADEMY® Analog Electronics 5.61
5V 3−0 1
I1 = = mA
IC 12 K 4
2k I1 = 0.25 mA
0 − (−3)
3V I D2 =
6K
IC I D2 = 0.5 mA
KVL
3k I D1 = I1 − I D2

– 5V I D1 = 0.25 m − 0.5 mA
By KVL, I D1 = − 0.25 mA
3 − 0.7 − IC × 3K + 5 = 0 D1 D2
Assumption :
I C × 3K = 7.3 FB FB
I C = 2.433 mA Take : VD1 = 0, VD2 = 0
Now by KVL, Find : I D1 = −1.25 mA < 0, I D2 = 0.5 mA
−5 + I C × 2 + VCB + 3 = 0
↓ ↓
VCB = 2 − 2.43 × 2 = −2.86 V
D1 = RB D2 = FB
So transistor is in saturation as no information is
Hence, our assumption is wrong.
given below,
Now, take D1 = RB & D2 : FB
VCE (sat) = 0 V
3V
5 − I C × 2 K − 0 − I C × 3K + 5 = 0
10
IC = = 2 mA 12 kΩ
5K
Hence, the correct answer is 2 mA. 0V ID 2

62. (A), (C), (D) + P

VD D1 N
Assume both the diodes D and D2 operates in 1
ID V
I – N 1

FB. 6 k
+3 V
I1 −3 V
12 kW
I D1 = 0 A = I
0V
ID 2 3 − (−3) 1
ID1 I D2 = = mA
P
D2 S.C. 18K 3
S.C. D1
V = 3 − I D2 .12 K = −1 V
N N 0V
Hence, the correct options are (A), (C) and (D).
6 kW
63. 6.762

-3 V Given : VZ = 6.8V at I Z = 5 mA & rZ = 20 Ω

 5.62 Paramount 1111 [EC] GATE ACADEMY®
N + N + KCL + ohm’s law at node-A
IZ
10 − VL VL − 6.7 VL − 0
≡
VZ = +
VZ 500 20 2000
0
VZ
BD
IZ rZ
40 − 4VL = 100VL − 670 + VL

P
–
P
– 710 = 105 VL
VZ = VZ0 + I 2 .r2 710
VL = V = 6.762 V
105
6.8 = VZ0 + 5 m × 20
VL = 6.762 V
VZ0 = 6.7 V (Break down coltage)
Hence, the correct answer is 6.762 V.
Now, RL = 2 kΩ do open circuit test to check 64. 1.63
conducting state of zener diode. Ripple voltage formula for FWR is given by,
VS 10 V
Vm − VDON
Vr =
RS 0.5 kΩ 2. f .RL .C
Vm
VL Here, V1rms = 18 =
+ N 2
RL = 2 kΩ
VZ
– P Vm = 18 2
Vr = 0.25 V, RL = 0.5 kΩ, f = 60 Hz
2k Vm − VDON
VZ = ×10 = 8 V C= VDON = 1 V 
2k + 0.5k Vr .2. f .RL
(VZ = 8 V) > (VZ0 = 6.7)
18 2 − 1
Hence, zener Diode operates in BD region. C=
0.25 × 2 × 60 × 0.5 ×103
Equivalent circuit is given by
10 V
C = 1.63 mF
Hence, the correct answer is 1.63 mF.
RS 0.5 k
A
VL VL
+
RL 2k
6.7 V VZ 0
–
rZ 20 Ω

65. 3.78
VB = 0.6
9 − 0.6 8.4
I 2k = = = 4.2 mA
2 2
IC
I 2 k = I c + I B + NI B = I C + ( N + 1)
β
GATE ACADEMY® Analog Electronics 5.63

 β + N + 1 9V
I2k = Ic  
 β  2k I C1 I C2 I CN -1 I CN
I B + NI B
Given circuit is a current mirror, IC
I C = I C1 = I C2 = ...... = I CN Q1 Q2
Q
IB NI B
 β 
I C = I CN =   I 2k
 β + N + 1
I 2k
I CN = I C = N - TX (Identical)
 N +1
1+  
 β 
 90 
=  4.2 = 3.78 mA
 90 + 9 + 1 
Hence, the correct answer is 3.78 mA.
66. (B)
In the given Op-Amp circuit, both positive and negative feedback are presents. So, we need to check
which feedback is dominating. 1k
Steps to indentity overall feedback :
+15 V
Step 1 : Null all the external sources i.e. 1k V−
Vin = 0 V (SC) and Iin = 0 A (OC) +
V0 = ΔV
V
Step 2 : Disconnect the output. −15 V
Step 3 : Assume small positive output i.e. V0 = ΔV . V +

+ − 2k ΔV
Step 4 : Find V and V at non-inverting terminal
1k
and inverting terminal respectively.
Step 5 : If V + > V − (Positive feedback) and
V − > V + (Negative feedback).
1 1
V + = ΔV and V − = ΔV
3 2
− +
Here, V > V (Negative feedback)
Virtual ground concept is applicable.
1
Now, V + = V − = V0
3
Apply KCL + Ohm’s law at V − ,
1 1
2 − V0 V0 − V0
3 =3
1k 1k
2 V
2 = V0 − V0 = − 0
3 3
V0 = − 6 V
Hence, the correct option is (B).
 5.64 Paramount 1111 [EC] GATE ACADEMY®

67. – 18 68. 0.5

Given figure is shown below, DC equivalent circuit is given by,

3kW
Z
1 mA
I in
+ 0.5 m OC
V0 v0
Vin +
– – +
C2
I D1 Vr1 +
ID2 Vr 2
–
OC –
R1 = 5 kW vi
C1
R2 30 kW
I = 500 mA = 0.5 mA

I D1 = 0.5 mA
By using voltage division at inverting terminal,
R2 I D2 = 1 mA − I D1 = 1 mA − 0.5 mA
V− = V0 × …(i)
R1 + R2 I D2 = 0.5 mA
V+ = V− = Vin VT 25 mV
rd 1 = = = 50 Ω
(∴ virtual ground/short concept) I D1 0.5 mA
Now by KCL at V+ , VT 25 mV
rd 2 = = = 50 Ω
Vin − V0 I D2 0.5 mA
I in =
Z Small signal equivalent circuit is given by,
 ( R + R2 ) 
Z I in = Vin − 1 Vin 
 R2  OC

[Using equation (i)] SC

v0
v0
− R 
C2
Z I in = Vin  1  rd1 rd1
 R2 
SC
vi
Vin − R2 C1
= Z in = Input impedance = Z
I in R1 OC

Vin −30 kΩ
= × 3 kΩ
I in 5 kΩ rd2 50
V0 = ⋅ v1 = ⋅ v1
Vin rd1 + rd 2 50 + 50
= − 6 × 3 = −18 kΩ
I in v0
= 0.5
V  v1
Hence, the value of  in  is −18kΩ.
 I in  Hence, the correct answer is 0.5.
GATE ACADEMY® Analog Electronics 5.65

69. 0.707
Transform domain,
1 s +1 1 2s + 1
Z1 = 1 + = and Z 2 = 2 + =
s s s s
Since inverting OP-AMP, 1
V −Z2 2 s
Transfer function, G ( s ) = 0 = 1
Vi Z1
1 s Z2
2s + 1 Vi ( s) −
G(s) = −
s +1 Z1 V0
+
2 jω + 1
G ( jω) = −
jω + 1
 2ω  −1  ω 
∠G ( jω) = 1800 + tan −1   − tan  
 1  1
d 2 1
∠G ( jω) = − =0
dω  (2ω)  1 + ω2
2

1 + 
 1 
2 1
=
1 + 4ω 1 + ω2
2

2 + 2ω2 = 1 + 4ω2
2ω2 = 1
1
ω= = 0.707 rad/sec
2
Hence, the correct answer is 0.707 rad/sec.
70. (A)
Vin
+
Vout
–
1 kΩ

1 kΩ 1 mA

Source Transformation
Vout = AV Vid = AV (V1 − V2 )
V1 = Vin
1 1 V 1
V2 = × Vout + × (−1) = out −
1+1 1+1 2 2
 5.66 Paramount 1111 [EC] GATE ACADEMY®

 V 1
Vout = 10 ×  Vin − out +  = 5 × ( 2Vin − Vout + 1)
 2 2
6Vout = 10Vin + 5
5Vin 5 5
Vout = + = × ( 2Vin + 1)
3 6 6
Hence, the correct option is (A).
71. 1.043 Now, VB1 = 10 V & VBE1 = 0.7 V

Assume Q1 & Q2 operates in Active region & VE1 = VBE1 − VB1 = 10 − 0.7 V = 9.3 V
both the diodes D1 & D2 are in F.B. VE1 − V0 VE1 − V0
R= =
+ 15 V I E1 I C2
9.3 − 2
VB
R= = 1.043 kΩ
+10 V
1

Q1 7 mA
+
0.7 V
–
VE 1
Hence, the value of resistance R is 1.043 k Ω .
R 72. 32.5
I E = IC IE
1 2 1
V0 = 2 V +15 V
IC 20 W V2
–
VB
2 Vin
2 + – Vout
Q2 0V +
+ + V1
0.7 V 0.7 V – VE 2
5W
– -15 V
+ 100 Ω
0.7 V V1
– IE 2

R
− 15 V
− 15 V

VB2 = −15 + 0.7 + 0.7 R

V2 = Vin and V1 = ⋅ Vout
VB2 = −13.6 V R+5
R
VBE2 = 0.7 V Vid = V1 − V2 = ⋅Vout − Vin
R+5
VB2 − VE2 = 0.7 V (i) Vout = 15 V and take Vid = 0
VE2 = VB2 − 0.7 V = −13.6 − 0.7 V1 = V2
VE2 = −14.3V R
Vin1 = .Vout
VE2 − (−15) R+5
I E2 =
100 Ω R 15R
Vin1 = × (+ 15 V) =
R+5 R+5
−14.3 + 15 0.7
I E2 = = 7 mA (ii) Vout = −15 V and take Vid = 0
100 100
As β very large, I C = I E V1 = V2
GATE ACADEMY® Analog Electronics 5.67

R Vout R1
Vin 2 = × Vout 0=
R+5 R1 + R2
R −15R Vout = 0 V
Vin 2 = ⋅ (−15 V) =
R+5 R+5
Hence, above circuit blocks the low
Here, Vin1 > Vin 2 frequency signal.
Vin = VUTP and Vin 2 = VLTP (ii) At high frequency ( f → ∞) :
Hysteresis width = VUTP − VLTP 1 1
XC = = →0 (short circuit)
15R −15 R ωC 2πfC
26 = −
R+5 R+5
15 R 15R 30 R
26 = + = S.C.
R+5 R+5 R+5
26 R + 130 = 30 R S.C.

4 R = 130
R = 32.5 Ω
Hence, the value of resistance R is 1.66 Ω.
Applying voltage division rule on output
73. (C) side,
Given circuit is shown below, V R
0 = out 1
R R1 + R2

Vin
R1 C
+ Vout = 0 V

–
Vout Hence, above circuit blocks the high
C 2R
frequency signal also.
R2 Since, V0 = 0 V for low and high frequency
R1
therefore, given circuit is BPF.
Hence, the correct option is (C).
(i) At low frequency ( f → 0) : 74. (B), (C), (D)
1 1
XC = = → ∞ (Open circuit) Assuming t = 0 + opamp is at +12 V and
ωC 2πfC
capacitor is zero volt, hence appropriate graph
will be
Vc = V−
4.28 V
t

O.C. V0 (t) 12 V

t
Applying voltage division rule on output Because input voltage are +12 V and zero volt
side, Hence, the correct options are (B), (C) and (D).
 5.68 Paramount 1111 [EC] GATE ACADEMY®

75. (D) VB = −0.69

Small signal circuit is given by VE = −0.69 − 0.7 = −1.4 V
VE − (−3) −1.4 + 3
I EDC = =
R1 40 kΩ RC 1.56 kΩ 0.6 K + 0.15K 0.5K
I EDC = 2.14 mA
B = 200
CC VT 25m
1
re = = = 11.66 Ω
RS R2 25 k RE 0.6 kΩ I EDC 2.14m
+ 0 V
VS  40 K  25K  (200 + 1) 
0.15 kΩ Req = 0.5K + 
× (11.66 + 0.6 K ) 
– SC

0V Req = 0.5K + (40 K  25 K  123K )
C eq & Req
Req = 0.5K + (15.38  123K )
Req = 0.5K + 13.67 K = 14.175 kΩ
1
RS CC
R1  R2
ie Req  f L3 dB =
2π.Req .Ceq
1
re
25 K  40 K
+ ie ↓ RE
1
VS Req  CC1 =
– 2π.Req . f L3 dB
1
CC1 = = 0.561 μF
Rin = R1  R2  Rib Rib = (re + RE ).(β + 1) 2π×14.175K × 20
Req = Rs + R1  R2  (β + 1).(re + RE ) Hence, the correct option is (D).
76. (B)
Ceq = CC1
12 V
V
Re = T
I EDC 5 μsec
0V
DC equivalent circuit is given as follow, Vi
3V Fig. (a)
8k
VI
40 kΩ R=
IE DC D
Vb
β = 200 Vi 1000 pF V0
+ 30 k
0.7 V – VE
0.5 k 25 k
0.6 kΩ I
E DC

SC 0.15 kΩ OC
Fig. (b)
0 < t < 5,
−3 V V (0) = 0
β = 200 >> 1  I B  0 30 ×12
V0 (∞) = = 9.473
(3 × 25) + (−3 × 40) 75 − 120 30 + 8
VB = =
25 + 40 65 V0 (t ) = 9.473 − 9.473e − t / τ
GATE ACADEMY® Analog Electronics 5.69

30 × 8 V0 (t )
τ = RC = ×103 ×1000 ×10−12
38
τ = 6.315 μ sec 5.18
−6
/6.315×10− 6
V0 (t ) = 9.473(1 − e − 5×10 )
V0 (t ) = 9.473(1 − e− 0.791 ) t
0 5μ
V0 (t ) = 9.473 × 0.546 = 5.18 V Hence, the correct opiton is (B).

77. (A)
Let’s check operating condition of BJT. Let’s assume it operates in cut-off region
+15 V
15 V
+

+ N 0V 8 kΩ
–
5.6 V– BD
P +
15 V VB Cut-off
V1 + P
V2 – Vx
N E
– V0

20 K RL

V2 = 15 − 5.6 = 9.4
V1 = 15 V
Vid = V1 − V2 = 15 − 9.4 = 5.6 V > 0  Vx > 0
↓
BJT : ON
↓
Active region (CE : 1800 )
+15 V

+ N IC 8 kΩ
9.4
5.6 V– BD – IC
VB C
P + Vx +

– VB +
9.4 I E = 0.7 mA
0.7 V –
Positive V0
feedback
20 kΩ RL

Non-Inverting OP-Amp CE
00 Phase Shift 0
180 Phase Shift
 5.70 Paramount 1111 [EC] GATE ACADEMY®
Overall negative feedback → VGC is applicable.
15 − 9.4
IC = = 0.7 mA
8K
VB = 9.4 V = Vx
VE = 8.7 V = V0
V
RL = 0 = 12.43 kΩ
IE
Hence, the correct option is (A).
78. (C) 1.3
IB = = 11.89 μA
109.33
1. DC analysis :
IC = β⋅ I B = 1.189 mA
VCDC = VCC − I C RC = 6.05 V
RC
2. AC analysis :

R1 50 kW RC 5 kW

Vc
R2

10 kW
+
V (t )
– RE 1kW

10 10
Vth = ×12 = ×12 = 2 V
10 + 50 60 Vth
50 ×10 50 Rth
Rth = R1  R2 = = kΩ 50 5
50 + 10 6 Vth = × Vs = Vs
60 6
50 ×10 50
Rth = = kΩ
50 + 10 6

Rth

50
kΩ
6
Vth

KVL,
Vth − I B ⋅ Rth − 0.7 − I B (β + 1) ⋅ RE = 0
Vth − 0.7 2 − 0.7
IB = = Vth − ib ⋅ Rth − ie ⋅ re − ie ⋅ RE = 0
Rth + RE (β + 1) 50 + 1(100 + 1)
6 ie = (β + 1) ⋅ ib
GATE ACADEMY® Analog Electronics 5.71

Vth = ib [ Rth + (β + 1)re + (β + 1) RE ] 25 m

re = = 20.82 Ω
5 (100 + 1) × 11.89 μ
⋅Vs = ib [ Rth + (β + 1) ⋅ (re + RE )]
6 −100 × 5k × 5 × (1.0sin ωt )
Vc =
6  50 
Vs = ⋅ ib [ Rth + (β + 1) ⋅ (re + RE )] 6  k + (100 + 1) ⋅ (20.82 + 1000) 
5  6 
Vc = −β⋅ ib ⋅ Rc −500 × 5 ×103 (1.0sin ωt )
Vc =
Vc −β ⋅ RC 6 (111.44k )
=
Vs 6 ⋅ [ R + (β + 1) ⋅ (r + R )] Vc = − 3.7391sin ωt (V )
th e E
5
Vc  − 3.74sin ωt (V )
−β ⋅ Rc .5
Vc = ⋅ Vs Vctotal = Vc + vc
6[ Rth + (β + 1) ⋅ (re + RE )]
VT VT Vctotal = 6.05 − 3.74sin ωt
re = =
I EDC (β + 1) ⋅ I BDC Hence, the correct option is (C).

79. 51.6
Given : β = 50, rπ = 2 kΩ
AC Analysis : All the capacitors are short circuited.
AC equivalent circuit of CE amplifier is shown below,

S.C.

V0
Internal voltage gain of CE amplifier is given by, Av = = − g m RL' [CE without RE ]
Vs
β
Where, g m = = 25 mA/V
rπ 1 kW

RL ' = 5 ||10 = 3.33 kΩ Vs Vi Ri ' = 1.636 kW

AV = − 25 × 3.33 = − 83.25
V0 V0 Vi V
AVS = = × = AV × i …(i)
Vs Vi Vs Vs
From figure, Ri ' = 11.5 || 41.1|| rπ
Ri ' = 8.98 || 2 = 1.636 kΩ
Vi 1.636
= = 0.62 …(ii)
Vs 1 + 1.636
 5.72 Paramount 1111 [EC] GATE ACADEMY®
From equation (i) and (ii),
AVS = − 83.25 × 0.62 = − 51.6
V0
Mid-band voltage gain = = 51.6
Vs
V0
Hence, the value of mid-band voltage gain is 51.6.
Vs
Use voltage divider rule at node V f
80. 4
ZB
Redraw the given circuit Vf = × V0
R2
ZA + ZB
V0
Vf ZB
β= =
R1 V0 Z A + ZB
–
Vf 1
+
V0 A×β = 1  A =
β
R2 Z A + Z B
1+ =
Vf V0 R1 ZB
CA RA
ZA R2 Z
CB RB
1+ = 1+ A
R1 ZB
ZB
R2 Z A 1 + SC A RA 1 + SCB RB
= = ×
R1 Z B SC A RB
RA = 4 kΩ , RB = 2 kΩ , CA = 5μF & CB = 10μF R2 1 + SC A RA + SCB RB + S 2 RA RB C ACB
=
1 1 + SC A RA R1 SC A RB
Here, Z A = RA + =
SC A SC A R2 SC A RA SCB RB
= +
1 R1 SC A RB SC A RB
RB ×
1 SCB RB S 2 RA RB C ACB 1
Z B = RB || = = + +
SCB R + 1 1 + SCB RB SC A RB SC A RB
B
SCB
R2 RA CB 1
To produce sustained oscillation loop gain must = + + SRACB +
R1 RB C A SRB C A
be equal to unity i.e. A⋅β = 1
Put S = jω ,
V V
Where, A = 0 and β = f R2 RA CB  1 
Vf V0 = + + j  ωR A × C B − 
R1 RB C A  ωRB C A 
Here, Apply KCL + Ohm’s law at inverting
Compare real part both the side,
node. R2 RA CB
0 − V f V f − V0 = +
= R1 RB C A
R1 R2 R2 4k 10 μ
= + = 2+2 = 4
V0 R R1 2k 5 μ
= A = 1+ 2
Vf R1 Hence, the correct answer is 4.
GATE ACADEMY® Analog Electronics 5.73

81. 10 1
C=
The given amplifier is a series-shunt feedback 2 πR f cutoff
amplifier. Now for approximation we can take 1
C= = 0.0707 μF
voltage gain with feedback, 2π×1.5 ×103 ×1.5 ×103
A A 1 Hence, the value of capacitor is 0.0707 μF.
Af =  
(1 + Aβ) Aβ β
83. (A)
[Since, Aβ >> 1 , (∴ 1 + Aβ  Aβ )]
Vf 1 Let output V0 = −15 (Saturated)
β= =
V0 10 V − − 10 V − + 15
+ =0
1 1 1 2
Af = =
β 10 2V − − 20 + V − + 15 = 0
3V − = 5
5
V− =
3
5
10 −
I= 3 = 8.33mA
1
Hence, the correct option is (A).
84. (A)
V
Hence, the approximated voltage gain A = 0 Given : Circuit shown in below figure,
Vin
12 V
for small signal input of Vin is 10.
82. 0.0707
I = 100 mA
Given : f cut off = 1.5 kHz
D1 D2
Circuit is shown below, VI
R2 = 20 kW I D2

+
R1 = 10 kW VB = 9 V
–
-
V0
+
C
R = 1.5 kW
Diode cut in voltage, Vv = 0.7
Responsible for cut Input voltage 0 ≤ VI ≤ 12 V
off frequency
Cutoff frequency for above circuit is, Case 1 :
1 If input voltage VI < 9 V , diode D1 -ON ,
f cutoff =
2 πRC D2 -OFF
 5.74 Paramount 1111 [EC] GATE ACADEMY®
I D2 (mA)

100 mA 100

– +
VI
VI (V)
0.7 I D2 0 9
+ Hence, the correct option is (A).
VB = 9 V
85. (A)
–
Given : Circuit shown in below figure,

I1 ID +
I D2 = 0 mA +
0.7
I R1 = 1kΩ – V0
I D2 (mA) +
1V
– –

Cut in voltage of diode Vγ = 0.7 V

0
Vin (V) Input current I ; 0 ≤ I ≤ 2 mA
9
Case 2 : Input voltage VI > 9 V diode
Let diode is ON;
ID +
D1 -OFF, D2 -ON I1
+
12 V 0.7
I R1 = 1kΩ – V0
+
1
–
100 mA –

1.7
+ – I1 = = 1.7 mA
VI 1 KΩ
O.C. I D2 0.7 V
Applying KCL at node A,
+
VB = 9 V ID = I − I 1
–
If diode is ON, then I D > 0; flow from P –
terminal to n – terminal of diode,
ID > 0
I D2 = 100 mA
I − I1 > 0
I D2 (mA)
I > I1
100 I > 1.7 mA
If input current I > 1.7 mA , then diode is ON
Vin (V) otherwise diode is OFF.
0 9
Hence, from case 1, and case the plot can be Case 1 :
draw, When, input current I < 1.7 mA , diode is OFF.
GATE ACADEMY® Analog Electronics 5.75

+ Given, Vc (0− ) = 0 V,
O.C. Vc (0− ) = Vc (0+ ) = 0 V
I R1 = 1kΩ V0
+ (From the property of the capacitor)
1V
–
–
Vc (∞) = 6 V
−t
V0 = IR1 Vc (t ) = Vc (∞) + Vc (0+ ) − Vc (∞)  e τ
Case 2 : t
−
When input current I > 1.7 mA , diode is ON Vc (t ) = 6(1 − e 2 ) V , t ≥ 0
+ At t = 4sec ,
+
0.7 V −
4
– Vc (t = 4 sec) = 6(1 − e ) V = 5.187 V 2
I R1 = 1kΩ V0
+
1V −
∝
–
–
Vc (t = ∞) = 6(1 − e 2 ) V = 6 V

V0 = 1.7 V 2
I= =1 A
2
Hence, from case 1 and case 2, the plot is draw
Hence, the correct options are (A), (B) and (D).
shown below,
V0 (V) 87. 2

1.7

R1
I (mA)
0 1.7
Hence, the correct option is (A).
86. (A), (B), (D)
Given circuit is as shown below for t ≥ 0 Applying KCL at node V1 ,
V1 V1 − V f
(V1 − V0 ) sC + + =0
– R R
V0 (2 + sCR )V1 = V f + V0 sCR …(i)
Applying KCL at node V f ,
V f − V1
V f sC + =0
 4 R
V0 = 1 +  × 2V = 6 V
 2 V f ( sCR + 1) = V1
(output of non-inverting ideal Op-Amp) Put value of V1 in equation (i),
Capacitor start charging through V0 and 2 Ω
(2 + sCR ) (1 + sCR)V f = V f + V0 sCR
resistor with time constant
τ = RC = 2 ×1 = 2 sec [(2 + sCR)( sCR + 1) − 1]V f = V0 sCR
 5.76 Paramount 1111 [EC] GATE ACADEMY®
Vf sCR VTN is positive. So, above condition is satisfied.
β= = 2 2 2
V0 s C R + 3sCR + 1 i.e. MOSFET M is in saturation
jωRC μ nCoxW
β( jω) = ID = (VGS − VTN ) 2
1 − ω R C 2 + 3 jωRC
2 2
2L
1 1 μ nCox W
At ω = or f = , = (− Vout − VTN )2
RC 2πRC 2L
 j  j 1 Vin μ n CoxW
β = = = (−Vout − VT )2
 RC  3 j 3 R 2L
Condition for oscillation : Aβ ≥ 1 2Vin L
(−Vout − VT ) =
Rf μ n CoxWR
A = 1+
R1 2Vin L
Vout = − − VTN
(Non-inverting configuration) μ n CoxWR
 Rf  1 Vout ∝ Vin
1 + × ≥1
 R1  3
This circuit is referred as square root amplifier
R f ≥ 2 kΩ because output is proportional to the square root
R fmin = 2 kΩ of input.
Hence, the correct option is (C).
Hence, the correct answer is 2 kΩ .
89. (B)
88. (C)
V0 ∂T
=T ± × 100%
Vs T
 −10 
T = −  = 10
 1 
∂T
× 100%
R ∂T
S RT = T = ×
∂R
From figure × 100% T ∂R
R
Vin
ID = R ∂  10 k 
R = ×  
T ∂R  R 
For MOSFET M,
∂T R 1
VGS = 0 − Vout = −Vout ×100% = − ×10 × 2 ×10 %
T T R
VDS = 0 − Vout = − Vout
R× R 1
=− × 10 k × 2 × 10 %
( VD = 0 from virtual ground concept) 10 k R
VDS > VGS − VTN = −10%
[Condition for saturation region] Hence, the correct option is (B).
GATE ACADEMY® Analog Electronics 5.77

90. (B)

Case 1 : When Vin > 0, [Inverting terminal > Non inverting terminal.]
So, V01 = −Vsat
Hence, D1 → ON, D2 → OFF

Current through R is 0 A in 1st stage. Hence, VA = 0

Second stage is a non-inverting amplifier.
Since, VA = 0
Hence, V0 = 0
Case 2 : When Vin < 0, [Inverting terminal < Non inverting terminal.]
So that, V01 = + Vsat
Hence, D1 → OFF, D2 → ON

From above figure,

 −R 
VA =   Vin = − Vin
 R 
 R
and V0 = 1 +  VA = (2) (−Vin ) = − 2Vin
 R
 5.78 Paramount 1111 [EC] GATE ACADEMY®
The transfer characteristics is shown below,
V0
Slope = -2

Vin

Hence, the correct option is (B).

91. (A)
Given circuit shown in below figure,
Vi (V)
D1 D2

25 +

T/2 T + 10 kΩ 20 kΩ
t(sec) Vi V0
– + +
2.5 V 10 V
– 25 – –
–

T
Case 1 : During positive half cycle, 0 < t <
2
Both diode D1 and D2 ON, (Given Vγ = 0 V )

S.C. S.C. +

+ 10 kΩ 20 kΩ
Vi V0
– + +
2.5 V 10 V
– –
–

Applying KVL, in the above circuit.

−Vi + V0 = 0
V0 = Vi
V0 (V)

25

t(sec)
0 T/2
T
Case 2 : During negative half cycle, <t <T
2
Both diode D1 and D2 are OFF.
GATE ACADEMY® Analog Electronics 5.79
O.C. O.C. 0 A 0A
+
0A
+
+ 10 kΩ
Vi 20 kΩ 0V
V0
– + –
2.5 V +
– 10 V
– –

Applying KVL, in the above circuit.

−10 − 0 + V0 = 0
V0 = 10 V
V0 (V)

25

10

t(sec)
0 T/2 T
Hence, from case 1 and case 2, the output wave form can be drawn as shown below,
V0 (V)

25

10
t(sec)
0 T/2 T
Hence, the correct option is (A).
92. (A)

Given : Circuit shown in below figure, and cut-in voltage of diode is Vγ = 0.7 V
Break down voltage of Zener diode VZ1 = 2.3 V and VZ2 = 5.6 V
Input voltage −10 V ≤ Vi ≤ 10 V
0.5 kΩ
Vi n V0
–
+
0.7 D1 D2 0.7
+
–
–
+
2.3 VZ1 VZ2 5.6
+
–

1 kΩ 2 kΩ
 5.80 Paramount 1111 [EC] GATE ACADEMY®

Case 1 : −6.3 < Vin < 3; D1 and D2 are reversed biased and Zener diode Z1 and Z 2 are also reversed
biased
0.5 kΩ 0 A 0A 0A
Vi n V0
+ 0V–
0A 0A

O.C. O.C.

O.C. O.C.

1 kΩ 2 kΩ

V0 = Vin
Case 2 : Vin > 3; Diode D1 -ON and Zener diode Z1 is breakdown diode D2 -OFF and Zener diode Z 2
is also OFF shown in below figure.
I 0.5 k 0A 0A
Vi n V0
I 0A
+
0.7 O.C.
–

+
2.3 O.C.
–

1 kΩ 2 kΩ

Applying KVL, in the above circuit,

−Vin + 0.5 KI + 0.7 + 2.3 + 1 KI = 0
Vin − 3
I=
1.5 K
Output voltage, V0 = Vin − 0.5 ×103 I
(Vin − 3)
V0 = Vin − 0.5 ×103 = 0.666 Vin + 1
1.5 ×103
Case 3 : For Vin < −6.3 V , Diode D1 − OFF and Zener diode is also revers biased diode D2 − ON and
Zener diode is breakdown, shown in below figure,
GATE ACADEMY® Analog Electronics 5.81

I 0.5 k I
Vi n V0
0A I
–
O.C. + 0.7

–
O.C. + 5.6

1 kΩ 2 kΩ

Applying KVL, in the above circuit,

−Vin + 0.5 KI − 6.3 + 2 KI = 0
Vin + 6.3
I=
2.5 K
(Vin + 6.3)
V0 = Vin − 0.5 K = 0.8 Vin − 1.26
2.5 K
The transfer characteristic of given circuit is shown below,
V0 (V)

0.66
3
1
– 6.3
Vin (V)
3

– 1.26

– 6.3

0.8

Hence, the correct option is (A).

93. (A)
 5.82 Paramount 1111 [EC] GATE ACADEMY®
1. DC analysis :
AC source will be replaced by short circuit.
9×3 2 kΩ
Vth = =3 V [By, VDR]
6+3 +
and Rth = 3 kΩ 6 kΩ = 2 kΩ 3V ID 1.4 V
-
3 − 1.4
ID = = 0.8 mA
2 kΩ
VT 25 mV
rd = = = 31.25 Ω
I D 0.8 mA
2. AC analysis :
DC source will be replaced by short circuit.
9sin ωt × 3
Vth = = 3sin ωt
6+3
Rth = 3 kΩ 6 kΩ = 2 kΩ
and replace both diode with its dynamic resistance.
Applying KVL in above loop,
3sin ωt ×10−3
ia (t ) = =1.45sin ωt μA
2 ×103 + 62.5
Hence, the correct option is (A).
94. (A), (C), (D)
+10 V +10 V +10 V +10 V +10 V

+ 0.7 V
–
VB1
VB1
10 K 8K
I R1 = 20 kΩ
+ I1
I2 I3 5K +5 V
–
Vx
VB2
3.6 K
VB 2

+
0.7 V –

−5 V −5 V

VB1 = 10 − 0.7 = 9.3 V

VB 2 = −5 + 0.7 = −4.3 V
VB1 − V B 2 9.3 − (−4.3)
I= = = 0.68 mA
R1 20 K
GATE ACADEMY® Analog Electronics 5.83
According current mirror circuit
I1 = I 2 = I ( β >> 1 and all transistors are identical)
I1 = I 2 = 0.68 mA
I3 = I = 0.68 mA
Hence, the correct options are (A), (C) and (D).
95. –5
Let’s assume zener diodes operates in breakdown region.
10 k Ω
V0

2 kΩ I 5 kΩ
+15V
Iz VN
+ V0
5V +

VP

5V +

V p = 5 V by virtual ground concept.

V p = VN = 5 V
Vx = 5 + 5 = 10 V
15 − Vx 15 − 10 5
Current, I = = = = 2.5 mA
2 2 2
Apply KVL + Ohm’s law at node VN
Vx − VN VN − V0
=
5 10
10 − 5 5 − V0
=
5 10
10 = 5 − V0
V0 = −5V
Applying KCL + Ohm’s Law at node Vx
Vx − VN
I = Iz +
5
15 − Vx 10 − 5
= Iz +
2 5
15 − 10 5
= Iz +
2 5
 5.84 Paramount 1111 [EC] GATE ACADEMY®
I z = 2.5 − 1mA
I z = 1.5mA > 0 Zener Diode operates in break down region
Hence, our assumption is correct and output voltage V0 = − 5 V .
96. (A)
Given : Diode and are Op-Amps are ideal and Vin = sin ωt
For positive half cycle Diode D → OFF,

V0 = Vin = sin ωt
For negative half cycle D → ON,

−R
For A1 , V ' = Vin = − Vin [Inverting amplifier]
R
For A2 , V0 = V '
 V0 = − sin ωt
Peak value (Vm ) = 1V
Vin
1V

–1 V
V0
1V

t
Full wave rectifier
Hence, the correct option is (A).
GATE ACADEMY® Analog Electronics 5.85

97. 0.8
Given figure is shown below,
I0
+
20 mA 40 A1 A2 A3 V0 0.46 kW
–

Current amplifier block can be represented in two-port network form as follows,

I

Ri AI R0

So, circuit can be modelled as,

Amplifier 1 Amplifier 2 Amplifier 3

20 mA

20 × 40
By using current division, I1 = = 10 mA
40 + 40
Ri = R0 = 40 Ω (for all amplifier)
 40  1
Using current division rule, I 2 = − A1 I1 ×   = −50 ×10 × = −250 mA
 40 + 40  2
40
I 3 = − A2 I 2 × = 625 mA
40 + 40
 40  40
I 4 = I 0 = − A3 I 3 ×   = −16 × 625 × mA = − 800 mA
 40 + 460  500
So, I 0 = 0.8 A
Hence, the correct answer is 0.8 A.
98. 9.85
Given circuit is shown below,
+

+
10sin t 2F Vc (t )
volts –

–
 5.86 Paramount 1111 [EC] GATE ACADEMY®
Since the capacitor is initially unchanged, the zener diode will not be in breakdown initially. So, the
circuit looks as shown below,
+

+
10sin t 2F Vc (t )
volts –

–
∴ Figure represents a positive peak detector circuit. So voltage across the capacitor will be the
peak value of 10sin t
10sin t V 10sin(t )V

10 V 10 V
t (sec) Peak t (sec)
detector p t = 2sec
t=
– 10 V 2

π
∴ At t = sec or 1.57 sec , Vc (t ) = 10 V
2
∴ At t = 1.4sec , let us assume Zener diode is OFF.
So, Vc (t ) = 10sin t = 10sin1.4 = 9.85 V
Here, Vz = 12 V so zener never come in breakdown.
∴ Vc (t ) t =1.4 sec = 9.85 V
Hence, the correct answer is 9.85 V.
99. (B)
O.C test :
10 k –
+ VZ 0V
Vi V0
VN VP VN –
Ii 2
2
1

VD +
VP +
1 0 V 10 kΩ
–
0V
0V

VZ = VP2 − VN2 = 0 − Vi
VZ = −Vi , VD = VP1 − VN1 = 0 V
So, during positive half cycle i.e. for 0 ≤ Vi ≤ 10 → zener diode may enter into breakdown  given
VZ0 = 3 V
(i) 0 ≤ Vi ≤ 3 V
DZ : off & D = off
Hence, current I = 0 A
GATE ACADEMY® Analog Electronics 5.87

(ii) 3 ≤ Vi ≤ 10 V
D2 : BD & D : RB
Ii
Vi – V0
10 k +
3V
OC
10 kΩ

Vi − 3
I=
10 K + 10 K
Vi = 3 V  I = 0 A
10 − 3
Vi = 10 V  I = = 0.35 mA
20 K
During negative half cycle. i.e. −10 ≤ Vi ≤ 0 V zener diode operates in FB & PN junction diode also
operates in FB.
Ii SC
Vi V0
10 k D2
SC
10 kΩ

Vi
I=  Vi = 0 V  I = 0
10 K
Vi = −10 V  I = −1 mA
I (mA)

0.35
−10
V (volts)
3 10

−1
Hence, the correct option is (B).
100. 15
8V

1 kΩ
5 kΩ I0 I C' 2 kΩ 0A +15 V
Vx +
IC IC V0
+ 2IB −
10 V
Q1 Q2 2 kΩ –15 V
IB IB
18 k
1 2

6k
 5.88 Paramount 1111 [EC] GATE ACADEMY®
I B1 = I B2 = I B , I 0 = I C + 2 I B
IC
IB =
β
10 − 0.7
I0 = = 1.86 mA
5
2I
I0 = IC + C
β
 β 
Ic = I0   = 1.823 mA
β + 2 
Ic = Ic '
Vx = 8 − 1×1.823 = 6.176 V
 R   18 
Op-Amp, V0 = 1 + f  Vx = 1 + 6  6.176
 R   
V0 = 24.7 V
Here, V0 > Vsat (Op-Amp is in saturation)
Hence, V0 = +Vsat
V0 = 15 V
Hence, the value of V0 is 15 V.
101. – 2.1

I
GATE ACADEMY® Analog Electronics 5.89

β >> 1  I B = 0
Voltage divider rule,
2
VE1 + 0.7 = × VE1
2 +1
2
VE1 + 0.7 = × VE1
3
3VE1 + 2.1 = 2VE1
VE1 = −2.1V
Hence, the node voltage VE1 is – 2.1 V.
102. (A)
D

id
g m Vgs
C D
+
ig = 0
Vgs g m Vgs C
+

– Vgs lW

g m Vgs
S –
S
Fig.1 Fig. 2
Vgs = (λ) × ( g mVgs )
1
λ= = g m−1
gm
Hence, the correct option is (A).
103. (B)
For f > f 2 , both the capacitors C1 & C2 act as short circuit & gain G is constant. The equivalent circuit
is given by

15 kW RC

0A

100 kW 4.7 MW

Vi CE
 5.90 Paramount 1111 [EC] GATE ACADEMY®

The given above circuit is a common source amplifier without Rs .

4.7 ×106 4.7 ×1000
Vg = 3
V =
6 i
Vi
100 ×10 + 4.7 ×10 100 + 4.7 ×1000
∴ Vg = 0.98Vi
V0 = − g mVgs ( RC  RL )
Vgs = Vg − Vs = 0.97 Vi − 0 = 0.98 Vi
V0 = − g m ⋅ ( RC  RL ) × 0.97 Vi
V0
= −5 × (15  15) × 0.98
Vi
V0
= −5 × 7.5 × 0.98 = −36.75
Vi
V0
Now, = 20 log10 −36.75 = 31.3 dB
Vi dB

Now, we have to find f1 & f 2 due to C1 = 3.3 nF & C2 = 53 nF

RC

R1 4.7 MW

Vi

(i) Due to C1 ,
Ceq = 3.3 nF
Req = R1 + RG = 100 × 103 + 4.7 × 106 = 4.8 MΩ
1 1
f1 = = = 10 Hz
2π ⋅ Ceq ⋅ Req 2π× 3.3 ×10−9 × 4.8 ×106
(ii) Due to C2 ,
Ceq = 53 nF & Req = RC + RL
1 1
f2 = = = 100 Hz
2π ⋅ Ceq ⋅ Req 2π× 53 ×10−9 × 30 ×103
Hence, the correct option is (B).
GATE ACADEMY® Analog Electronics 5.91

104. (B)
R2 = 10 kΩ

R1 = 1 kΩ +15 V
Vin –

Ii Vout
+
R3 = 10 kΩ
−10V

For linear operation : −10 V ≤ Vout ≤ 15 V

RF 10
Vout = − .Vin = − .Vin = −10.Vin
R1 1
−10 V ≤ −10.Vin ≤ 15 V
−1 V ≤ − Vin ≤ 1.5 V
−1.5 V ≤ Vin ≤ 1 V
Hence, the correct option is (B).
105. (D)

Apply KCL + Ohm’s law, node V1 and V2

VB − V1 V1 − V2 V1 − V2 V2 − VA
= =
5 1 1 5
VB = 6V1 − 5V2 5V1 − 5V2 = V2 − VA
VB = 6V1 − 5V2 VA = 6V2 − 5V1
 5.92 Paramount 1111 [EC] GATE ACADEMY®
Given dotted circuit is a subtractor circuit
∴ V0 = VA − VB
V0 = VA − VB = 6V2 − 5V1 − 6V1 + 5V2 = 11V2 − 11V1
Given V1 (t ) = A + B.cos ωt
V2 = 2 V
V0 = (11× 2) − 11× ( A + B cos ωt )
V0 = 22 − 11A − 11B.cos ωt …(i)
V0 = A0 + B0 .cos ωt …(ii)
Compare equation (i) & (ii)
A0 = 22 − 11A B0 = −11B
A0 = 11(2 − A) B0 = −11B
Hence, the correct option is (D).
106. (B)
When switch S is open,

0 − 2 2 − V0
=
20 k 40 k
V0 = 6 V
VC (∞) = 6 V
When switch S is closed,

Time constant = RC
GATE ACADEMY® Analog Electronics 5.93

VN = 2 V
V0 = VN = 2 V
VC (t ) = VC (∞ ) + [VC (0) − VC (∞ ) ] ⋅ e − t / τ
τ = RC
1
τ = 40 K × 4 μF = sec
6.25
1
−t /
VC (t ) = 6 + (2 − 6) ⋅ e 6.25

VC (t ) = 6 − 4.e−6.25t (V)
Hence, the correct option is (B).
107. (C)
Form the given frequency response, initial slope is 0 dB/dec.
∴ 20log10 K = 40
So, K = 100 and at ω = 104 rad/sec slope changes by −20dB/dec . So, there exist a single pole.

Slope = – 20 (dB/dec)

K
A(s) =
S
1+
104
Put, S = jω
100
A( s) =
jω
1+ 4
10
Input xi (t ) = 0.05cos (105 t ) V
∴ ω i = 105 rad/sec
Sinusoidal steady state Response is given by,
x0 (t ) = 0.05 × P × cos (105 t + θ A )
Where, P = A(ω) ω=ω , θ A = ∠ A(ω) ω=ω
i i

100  ω 
A(ω) = , ∠A(ω) = − tan −1  4 
 ω 
2
 10 
1+  4 
 10 
 5.94 Paramount 1111 [EC] GATE ACADEMY®

100  105 
P= , ∠A(ω) = − tan −1  4  = − tan −1 10 = −84.30
 ω 
2
 10 
1+  4 
 10 
100 100 100
P= = = = 9.95
5 2
 10  1 + 100 101
1+  4 
 10 
∴ P  10
x0 (t ) = 0.05 ×10 × cos (105 t − 84.30 )
x0 (t ) = 0.5 × cos (105 t − 84.30 )
Hence, the correct option is (C).
108. 60.929
10 V

100 Ω

4 kΩ VB

IB R
0.7 V 4V
6V + IE +10 V
–
A
VE
4V
V0 = 2 V
4V

– 10 V
4 V +–

By using virtual ground concept,

VE = 4 V
VBE = VB − VE = 0.7 V
VB − 4 = 0.7 V
VB = 4.7 V
6 − VB 6 − 4.7
IB = = = 0.325 mA
4k 4k
I E = (β + 1) I B = (100 + 1) × 0.325 m = 32.825 mA
Use KCL + Ohm’s law at node A,
4 − V0 4 − 2
IE = =
R R
GATE ACADEMY® Analog Electronics 5.95

2 2
R= = = 60.929 Ω
I E 32.825 m
Hence, the value of resistance R is 60.929 Ω.
109. (A)

Open circuit test to find Vid = V1 − V2

V1

V2

15 × R + 3R × Vi 3 15
V2 = = Vi +
R + 3R 4 4
V1 = 0 V [ V2 = 0]
3 15 3V 15
Vid = V1 − V2 = 0 − Vi − = − i −
4 4 4 4
Case 1 : Vid > 0, Op-Amp output Vx > 0  D1 : ON and D2 : OFF
Vid > 0
3Vi 15
− − >0
4 4
Vi < − 5

OC

SC

Use KCL and Ohm’s law at node A,

15 − 0 Vi − 0 0 − V0
+ =
3R R R
 5.96 Paramount 1111 [EC] GATE ACADEMY®
5 + Vi = − V0
V0 = −Vi − 5
Vi < − 5 V
V0 = −Vi − 5
Case 2 : Vid < 0, Vx < 0  D1 : OFF and D2 : ON
Vid < 0  Vi > − 5 V

SC

OC

Vi > − 5V  V0 = 0 V
Transister characteristic,
V0
1
1 Vi
−5 V

Hence, the correct option is (A).

110. (C)
Both the Op-Amps are operated in linear region, negative feedback and ideal. So we can we virtual
ground concept.
V1 cos wt (V)

1 kW
2 V 1 kW
+ V0
VP + + 0V–
V01 2V
–
– 1 kW A
1 kW
1 kW
1 kW
VP
VN = VP
1 kW
GATE ACADEMY® Analog Electronics 5.97

V p by voltage divider rule

1 V
Vp = × V1 = 1
1+1 2
VN = VP
1
Vp = × V0
1+1 1
V1 1
= .V0
2 2 1
V01 = V1
Now, KCL + Ohm’s law node A
V01 − 2 2 − V0
=
1 1
V0 = 4 − V01 V0 = 4 − cos ωt

V0 = 4 − V1 V0 = λ + μ cos ωt
Hence, λ = 4 & μ = −1
Hence, the correct option is (C).
111. (D)

Feedback topology shown below figure,

Ri R0

Vif A V0

Rif R0f
b

Given topology shows sampling is done in series manner so it is current sampling and mixing at input
is done by shunt arrangement so, type of feedback is current shunt.
Ri = Input impedance without feedback
Rif = Input impedance with feedback,

R0 = Output impedance without feedback and

R0 f = Output impedance with feedback.
Ri
Rif = …(i)
(1 + Aβ)
R0 f = R0 (1 + Aβ) …(ii)
 5.98 Paramount 1111 [EC] GATE ACADEMY®
Take ratio of equation (i) and (ii),
R0 f R0 (1 + Aβ) (1 + Aβ) 2
= =
Rif  1   Ri 
Ri    
 1 + Aβ   R0 
Substituting value from questions,
(1 + Aβ) 2
625 =
4
(1 + Aβ)2 = 625 × 4
(1 + Aβ) = 2500 = 50
Aβ = 49 …(iii)
Vout
Now, A=
V
RF = 99 kW
Using standard result,
Vout  R   99 k  R1 = 1 kW
= A = 1 + f  = 1 +  = 100 -
V  R1   1k  Vout
+
Using equation (iii),
Aβ = 49 V +
–

49
β= = 0.49
100
Hence, the correct option is (D).

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