UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.

ge 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

UMC 40nm Logic and Mixed-Mode Low

Power with Regular Threshold Voltage 1.1 V
MOSFET Monte Carlo SPICE Model
Document

Version 1.4 Phase 1

2013/06/24

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

Table of Contents

1 INTRODUCTION ................................................................... 5
1.1 Revision History ................................................................................................. 5
1.2 General Information ............................................................................................ 7
1.3 Model Usage ....................................................................................................... 8
1.3.1 Simulators ................................................................................................... 8
1.3.2 The combination of statistical model & corner model................................ 8
1.3.3 Mismatching parameters in corner model .................................................. 8
1.3.4 Sigma number for Monte-Carlo model ....................................................... 9
1.3.5 Model usage ................................................................................................ 9
2 MONTE CARLO DC SIMULATION RESULTS FOR
PROCESS VARIATION............................................................. 17
2.1 Threshold voltage in linear region VTLIN ....................................................... 17
2.2 Threshold voltage in saturation region VTSAT................................................ 19
2.3 Linear Current IDLIN ....................................................................................... 20
2.4 Saturation Current IDSAT ................................................................................ 21
2.5 Transfer Conductance GM ................................................................................ 22
2.6 Output Conductance GDS................................................................................. 23
3 MONTE CARLO DYNAMIC SIMULATION RESULTS
FOR PROCESS VARIATION ................................................... 24
3.1 Ring Oscillator Circuit ...................................................................................... 24
4 MONTE CARLO SIMULATION RESULTS FOR
MISMATCH ................................................................................. 26
4.1 Threshold voltage in linear region VTLIN ....................................................... 26
4.2 Saturation Current IDSAT ................................................................................ 27
5 APPENDIX ............................................................................. 29
5.1 HSPICE Warning Message ............................................................................... 29
5.2 ELDO Warning Message .................................................................................. 29
5.3 SPECTRE Warning Message ........................................................................... 29

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

List of Figures
Figure 1-1 Layout Example of parallel devices. ............................................................... 10
Figure 1-2 Layout Example for LOD effect ..................................................................... 11
Figure 2-1 Monte Carlo plots of threshold voltage at low drain bias ............................... 18
Figure 2-2 Monte Carlo plots of threshold voltage at high drain bias .............................. 19
Figure 2-3 Monte Carlo plots of linear current ................................................................. 20
Figure 2-4 Monte Carlo plots of saturation current .......................................................... 21
Figure 2-5 Monte Carlo plots of transfer conductance ..................................................... 22
Figure 2-6 Monte Carlo plots of output conductance ....................................................... 23
Figure 3-1 Ring oscillator netlist diagram ........................................................................ 24
Figure 3-2 Corner plot of ring oscillator ........................................................................... 25
Figure 4-1 VTLIN mis-matching simulation of 1.1V n-ch MOSFET .............................. 26
Figure 4-2 VTLIN mis-matching simulation of 1.1V p-ch MOSFET .............................. 27
Figure 4-3 IDSAT mis-matching simulation of 1.1V n-ch MOSFET .............................. 28
Figure 4-4 IDSAT mis-matching simulation of 1.1V p-ch MOSFET .............................. 28

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

List of Tables
Table 1-1 Revision history .................................................................................................. 5
Table 3-1 Ring oscillator (inverter) structure description for SA=0.099um .................... 25
Table 5-1 HSPICE warning message ................................................................................ 29
Table 5-2 ELDO warning message ................................................................................... 29
Table 5-3 SPECTRE warning message ............................................................................ 29

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

1 Introduction

1.1 Revision History

Table 1-1 Revision history

Version Date Author Remark
1. Original release.
2. This Monte Carlo model includes both
process and mis-matching characteristics
T.0_P1 2009/07/13 Jr-Hua Liu
extracted from model cards as below:
L40LP_RVT11_VT01.mdl
L40LP_RVT11_VT01.lib
1. Current trend of Length through Width
modification.
2. Corner range modification
3. This Monte Carlo model includes both
T.1_P1 2009/08/26 Jr-Hua Liu
process and mis-matching characteristics
extracted from model cards as below:
L40LP_RVT11_VT11.mdl
L40LP_RVT11_VT11.lib
1. NMOS Cja and Cov modification
2. PMOS Cov modification
3. I-V curve and temperature-effect
modification
4. Based on New DSM version definition
0.1_P1 2010/05/31 Jr-Hua Liu from 2009/11/30.
5. This Monte Carlo model includes both
process and mis-matching characteristics
extracted from model cards as below:
l40lp_rvt1p1_v012.mdl
l40lp_rvt1p1_v012.lib
1. Added Noise parameters.
2. Added DNW device.
3. This Monte Carlo model includes both
0.1_P2 2010/09/20 Jr-Hua Liu process and mis-matching characteristics
extracted from model cards as below:
l40lp_rvt1p1_v013.mdl
l40lp_rvt1p1_v013.lib
1. This Monte Carlo model includes both
process and mis-matching characteristics
0.1_P3 2011/01/14 Chun Wei Chen extracted from model cards as below:
l40lp_rvt1p1_v014.mdl
l40lp_rvt1p1_v014.lib
1. This Monte Carlo model includes both
Chun Wei Chen process and mis-matching characteristics
1.0_P1 2011/05/03 Louis Yuen extracted from model cards as below:
l40lp_rvt1p1_v111.mdl

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

l40lp_rvt1p1_v111.lib
1. This Monte Carlo model includes both
process and mis-matching characteristics
1.1_P1 2011/05/26 Chun Wei Chen extracted from model cards as below:
l40lp_rvt1p1_v121.mdl
l40lp_rvt1p1_v121.lib
1. Modify noise parameters.
2. Add noise corner parameters.
3. Modified NMOS LOD parameters.
4. Revised leff trend of Cgc for N/P
MOS
1.2_P1 2011/11/30 Yeong-Jia Chen 5. Revised N/P MOS corner range
6. This Monte Carlo model includes both
process and mis-matching characteristics
extracted from model cards as below:
l40lp_rvt1p1_v141.mdl
l40lp_rvt1p1_v141.lib
1. Modify global corner range.
2. This Monte Carlo model includes both
Annie Kuo
process and mis-matching characteristics
1.3_P1 2012/03/01 Louis Yuen
extracted from model cards as below:
Yeong-Jia Chen
l40lp_rvt1p1_v141.mdl
l40lp_rvt1p1_v141.lib
1. This Monte Carlo model includes both
process and mis-matching characteristics
1.4_P1 2013/06/24 Ryan LK Chen extracted from model cards as below:
l40lp_rvt1p1_v151.mdl
l40lp_rvt1p1_v151.lib

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

1.2 General Information

This document serves as a reference to the design of products that will be manufactured
by UMC using the following process.

UMC 40nm Logic and Mixed-Mode Low Power Process

For more information about this process and technology, please see the electrical design
rule listed below.

G-02-LOGIC/MIXED_MODE40N-LP-EDR

The creation, verification, and usage of the compact model of the following devices are
presented in this document.

1.1V n-ch MOSFET

1.1V p-ch MOSFET

The following compact model is chosen for the modeling of these devices.

BSIM4V4.6.0

For detailed descriptions of the compact model equations and parameters, please refer to
this material.

BSIM4V4.6.0 MOSFET Model User Manual

In BSIM4V4.6.0, there are two types of models that can be used. One is a binning model,
which means the whole device dimension range is chopped into several "bins" and
different model parameter sets are provided for each bin. The other one is a global model,
which means one scalable parameter set is provided and it can cover the whole device
geometry range. Each of these two approaches has advantages over the other.

UMC provides global models for their many benefits and the model accuracy is
guaranteed by a quantitative report of model fitting error against the silicon data, which
can be found in the following sections.

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

1.3 Model Usage

1.3.1 Simulators

The compact model is provided in various formats. It is guaranteed that the simulation
results of this model from different simulators show differences less than 0.5% and 1%
for DC and AC simulations respectively. It should be noted that the model has been
verified on different simulators of the specific versions listed below, and the simulation
results from other versions of the simulators might be different

Synopsys HSPICE release 2012.06

Cadence SPECTRE version 10.1.1.111.isr8
Mentor Graphics ELDO version 6.11_1.1

1.3.2 The combination of statistical model & corner model

The Monte-Carlo model and corner model (5 corners) are combined into a single
model library. The user can choose either the Monte-Carlo model or a corner case
by selecting different model sections for simulation. The following sections are
included:
MC: Monte-Carlo model
TT: Typical n-ch MOSFET and Typical p-ch MOSFET
SS: Total corner of Slow n-ch MOSFET and Slow p-ch MOSFET
SNFP: Total corner of Slow n-ch MOSFET and Fast p-ch MOSFET
FNSP: Total corner of Fast n-ch MOSFET and Slow p-ch MOSFET
FF: Total corner of Fast n-ch MOSFET and Fast p-ch MOSFET
TT_G: Typical n-ch MOSFET and Typical p-ch MOSFET (the same as TT)
SS_G: Global corner of Slow n-ch MOSFET and Slow p-ch MOSFET
SNFP_G: Global corner of Slow n-ch MOSFET and Fast p-ch MOSFET
FNSP_G: Global corner of Fast n-ch MOSFET and Slow p-ch MOSFET
FF_G: Global corner of Fast n-ch MOSFET and Fast p-ch MOSFET

1.3.3 Mismatching parameters in corner model

The mismatching parameters are included in the corner models. Therefore, the user can
run Monte-Carlo mismatching simulation over a corner model. For example, the user can
evaluate the mismatching performance at the SS_G case.

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Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

1.3.4 Sigma number for Monte-Carlo model

The user can define standard deviation at sigma level for Monte-Carlo simulation. If a
larger sigma number is used, it means the model parameters will have greater variation.
Sigma=3 is recommended to be used.

1.3.5 Model usage

The definitions of sub-circuit model parameters

After invoking Monte-Carlo model parameters, the compact transistor models evolve to
sub-circuit models. The input parameters for the sub-circuit model are the same as the
compact model, except two more input parameters (mis_flag, & mf) are added for the
sub-circuit model.

The following is the parameter list:

- nf: number of gate fingers

- m: number of devices
- mf: the same as "m"
- mis_flag: the flag parameter is used to turn on/off mismatching parameters for
individual devices. 1 is turn-on and 0 is turn-off. Default is 1.
- w: total gate width (gate finger width * number of gate fingers)
- l: gate finger length
- as: source area per finger
- ad: drain area per finger
- ps: source periphery per finger
- pd: drain periphery per finger
- sa: distance between OD edge to poly from one side
- sb: distance between OD edge to poly from the other side
- sd: poly space for multiple finger device
- sca: integral of the first distribution function for scattered well dopant
- scb: integral of the second distribution function for scattered well dopant
- scc: integral of the third distribution function for scattered well dopant
- sga: effective distance between poly gate to adjacent poly gate from one side
- sgb: effective distance between poly gate to adjacent poly gate from the other
side
- sg2a: effective distance between 2nd poly gate to adjacent poly gate from one
side
- sg2b: effective distance between 2nd poly gate to adjacent poly gate from the
other side

The following example shows 3 transistors connected in parallel; each transistor has 5
fingers and each finger has width 5u and length 1u. The mismatching parameters are
turned on. And the parameter "mf" is a must for mismatching simulation of parallel
devices. Please note mf and m have to be equal.

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design of products manufactured by UMC.

x1 (d g s b) DeviceName w='W1*NF1' l=1u nf=5 mis_flag=1 m=3 mf=3

Figure 1-1 Layout Example of parallel devices.

Follow the description for the net-list of the LOD effect and these steps to invoke the
model file during simulation.

(a) Example for odd finger number

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Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

(b) Example for even finger number

Figure 1-2 Layout Example for LOD effect

For Synopsys HSPICE

- Include library file and select section.

Example 1: .lib " l40lp_rvt1p1_v141_mc _corner.lib" MC
Example 2: .lib " l40lp_rvt1p1_v141_mc _corner.lib" FF
Example 3: .lib " l40lp_rvt1p1_v141_mc _corner.lib" FF_G

- Define sigma value for MC simulation.

Example: .param sigma=3

- Add the following statement in the input file to the simulator for 90% dimension
shrinkage.
.Option scale=0.9
.lib "./ModelFileName.lib" CaseName
, where CaseName could be MC,TT, FF, SS, FNSP, SNFP, FF_G, SS_G,
FNSP_G or SNFP_G.

- Define device condition by 'Xxx' statement.

Example: For Finger Number device (Refer to Figure 1-2)
X1 Vdd Vgg Vss Vbb DeviceName W='W1*NF1' L=L1 NF=NF1
+ SA=SA1 SB=SB1 SD=SD1 SCA=SCA1 SCB=SCB1 SCC=SCC1
+ NF_ODD='NF-2*INT(NF/2)' NF_EVEN='1-NF_ODD'
+ A_UNIT='SD*W/NF' P_UNIT='2*(SD+W/NF)'

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design of products manufactured by UMC.

+ A_SA_EDGE='SA*W/NF' P_SA_EDGE='2*(SA+W/NF)'
+ A_SB_EDGE='SB*W/NF' P_SB_EDGE='2*(SB+W/NF)'
+ AD='NF_ODD*(A_UNIT*((NF+1)/2-1)+A_SB_EDGE) +
NF_EVEN*(A_UNIT*NF/2)'
+ AS='NF_ODD*(A_UNIT*((NF+1)/2-1)+A_SA_EDGE) +
NF_EVEN*(A_UNIT*(NF/2-1)+A_SA_EDGE+A_SB_EDGE)'
+ PD='NF_ODD*(P_UNIT*((NF+1)/2-1)+P_SB_EDGE) +
NF_EVEN*(P_UNIT*NF/2)'
+ PS='NF_ODD*(P_UNIT*((NF+1)/2-1)+P_SA_EDGE) +
NF_EVEN*(P_UNIT*(NF/2-1)+P_SA_EDGE+P_SB_EDGE)'
+ SGA=SGA1 SGB=SGB1 SG2A=SG2A1 SG2B=SG2B1

- Define the control of Monte-Carlo simulation.

Indicator:
PROCESS: 1 to turn on the global MC simulation
0 to turn off the global MC process simulation
MISMATCH: 1 to turn on the local MC mismatch simulation
0 to turn off the local MC mismatch simulation
Example 1:
run global & local (total) MC simulation together.
.lib "./ModelFileName.lib" MC
.PARAM PROCESS=1 MISMATCH=1

Example 2:
run global MC simulation only.
.lib "./ModelFileName.lib" MC
.PARAM PROCESS=1 MISMATCH=0

Example 3:
run local MC simulation only.
.lib "./ModelFileName.lib" MC
.PARAM PROCESS=0 MISMATCH=1

Example 4:
run local MC simulation on global corners.
.lib "./ModelFileName.lib" FF_G (or SS_G, FNSP_G,SNFP_G)
.PARAM PROCESS=0 MISMATCH=1

- Define the number of Monte Carlo iterations to run MC simulations.

Example: .DC Vgg 0 1.1 0.01 Sweep Monte=200

For Cadence SPECTRE

- Include library file and select section.

Example 1: include " l40lp_rvt1p1_v141_mc _corner.lib.scs" section=mc
Example 2: include " l40lp_rvt1p1_v141_mc _corner.lib.scs" section=ff
Example 3: include " l40lp_rvt1p1_v141_mc _corner.lib.scs" section=ff_g

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Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

- Define sigma value for MC simulation.

Example: parameters sigma=3

- Add the following statement in the input file to the simulator for 90% dimension
shrinkage.
SetOption1 options scale=0.9
include "./ModelFileName.lib.scs" section=CaseName
, where CaseName could be mc,tt, ff, ss, fnsp, snfp, ff_g, ss_g, fnsp_g or snfp_g.

- Define device condition by 'Xxx' statement.

Example: For Finger Number device (Refer to Figure 1-2)
X1 (Vdd Vgg Vss Vbb) DeviceName w='W1*NF1' l=L1 nf=NF1
+ sa=SA1 sb=SB1 sd=SD1 sca=SCA1 scb=SCB1 scc=SCC1
+ nf_odd=nf-2*int(nf/2) nf_even=1- nf_odd
+ a_unit=sd*w/nf p_unit=2*(sd+w/nf)
+ a_sa_edge=sa*w/nf p_sa_edge =2*(sa+w/nf)
+ a_sb_edge=sb* w/nf p_sb_edge =2*(sb+w/nf)
+ ad=nf_odd *( a_unit *((nf+1)/2-1)+ a_sb_edge) + nf_even *( a_unit
*nf/2)
+ as=nf_odd *( a_unit *((nf+1)/2-1)+ a_sa_edge) + nf_even *( a_unit
*(nf/2-1)+ a_sa_edge + a_sb_edge)
+ pd=nf_odd *( p_unit *((nf+1)/2-1)+ p_sb_edge) + nf_even *( p_unit
*nf/2)
+ ps=nf_odd *( p_unit *((nfF+1)/2-1)+ p_sa_edge) + nf_even *( p_unit
*(nf/2-1)+ p_sa_edge + p_sb_edge)
+ sga=SGA1 sgb=SGB1 sg2a=SG2A1 sg2b=SG2B1

- Define the number of Monte Carlo iterations and control MC simulations.

Example 1: run global & local (total) MC simulation together.
mc1 montecarlo numruns=200 seed=1 variations=all donominal=yes
savefamilyplots=yes {
analysisDC1 dc param=Vgg start=0 stop=1.1 step=0.01}
Example 2: run global MC simulation only
mc1 montecarlo numruns=200 seed=1 variations=process donominal=yes
savefamilyplots=yes {
analysisDC1 dc param=Vgg start=0 stop=1.1 step=0.01}
Example 3: run local simulation only
mc1 montecarlo numruns=200 seed=1 variations=mismatch donominal=yes
savefamilyplots=yes {
analysisDC1 dc param=Vgg start=0 stop=1.1 step=0.01}
Example 4: run local MC simulation on global corners.
include "./ModelFileName.lib.scs" section= ff_g ( or ss_g, fnsp_g, snfp_g )
mc1 montecarlo numruns=200 seed=1 variations=mismatch donominal=yes
savefamilyplots=yes {
analysisDC1 dc param=Vgg start=0 stop=1.1 step=0.01}

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Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

For Mentor Graphics ELDO

- Include library file and select section.

Example 1: .lib " l40lp_rvt1p1_v141_mc _corner.lib.eldo" MC
Example 2: .lib " l40lp_rvt1p1_v141_mc _corner.lib.eldo" FF
Example 3: .lib " l40lp_rvt1p1_v141_mc _corner.lib.eldo" FF_G

- Define sigma value for MC simulation.

Example: .param sigma=3

- Add the following statement in the input file to the simulator for 90% dimension
shrinkage.
.Option scale=0.9
.lib "./ModelFileName.lib.eldo" CaseName
, where CaseName could be MC,TT, FF, SS, FNSP, or SNFP.

-Define device condition by 'Xxx' statement.

Example: For Finger Number device (Refer to Figure 1-2)
X1 Vdd Vgg Vss Vbb DeviceName W='W1*NF1' L=L1 NF=NF1
+ SA=SA1 SB=SB1 SD=SD1 SCA=SCA1 SCB=SCB1 SCC=SCC1
+ NF_ODD='NF-2*INT(NF/2)' NF_EVEN='1-NF_ODD'
+ A_UNIT='SD*W/NF' P_UNIT='2*(SD+W/NF)'
A_SA_EDGE='SA*W/NF' P_SA_EDGE='2*(SA+W/NF)'
+ A_SB_EDGE='SB*W/NF' P_SB_EDGE='2*(SB+W/NF)'
+ AD='NF_ODD*(A_UNIT*((NF+1)/2-1)+A_SB_EDGE) +
NF_EVEN*(A_UNIT*NF/2)'
+ AS='NF_ODD*(A_UNIT*((NF+1)/2-1)+A_SA_EDGE) +
NF_EVEN*(A_UNIT*(NF/2-1)+A_SA_EDGE+A_SB_EDGE)'
+ PD='NF_ODD*(P_UNIT*((NF+1)/2-1)+P_SB_EDGE) +
NF_EVEN*(P_UNIT*NF/2)'
+ PS='NF_ODD*(P_UNIT*((NF+1)/2-1)+P_SA_EDGE) +
NF_EVEN*(P_UNIT*(NF/2-1)+P_SA_EDGE+P_SB_EDGE)'
+ SGA=SGA1 SGB=SGB1 SG2A=SG2A1 SG2B=SG2B1

- Define the control of Monte-Carlo simulation.

Indicator:
PROCESS: 1 to turn on the global MC simulation
0 to turn off the global MC process simulation
MISMATCH: 1 to turn on the local MC simulation
0 to turn off the local MC simulation
Example 1:
run global & local (total) MC simulation together.
.lib "./ModelFileName.lib.eldo" MC
.PARAM PROCESS=1 MISMATCH=1

Example 2:
run global MC simulation only.
.lib "./ModelFileName.lib.eldo " MC
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design of products manufactured by UMC.

.PARAM PROCESS=1 MISMATCH=0

Example 3:
run local MC simulation only.
.lib "./ModelFileName.lib.eldo " MC
.PARAM PROCESS=0 MISMATCH=1

Example 4:
run local MC simulation on global corners.
.lib "./ModelFileName.lib.eldo " FF_G (or SS_G, FNSP_G,SNFP_G)
.PARAM PROCESS=0 MISMATCH=1

- Define the number of Monte Carlo iterations to run MC simulations.

Example: .DC Vgg 0 Vcc 1.1 Sweep Monte=200

The noiflag is used for 1/f noise corner simulation (1 for worst case; 0 for typical case;
-1 for best case), which will be turned off when 1/f noise Monte Carlo simulation is
turned on.
noiflag_mc is used for 1/f noise Monte Carlo simulation (1:turn on 0: turn off).
noisigma is the standard deviation at the sigma level (noisigma= 3 is recommended) for 1/f
noise corner or Monte Carlo simulation.

Benchmark Model: l40lp_rvt1p1_v151

DeviceName for 1.1V n-ch MOSFET: n_11_lprvt, n_bpw_11_lprvt,
n_bpw5t_11_lprvt
DeviceName for 1.1V p-ch MOSFET: p_11_lprvt

As stated above that one global model is provided and this model is valid within the
following geometry, voltage, and temperature ranges. Device behavior beyond these
ranges may not be well described by the model and is not guaranteed.

Geometry range (Before shrinkage):

For both 1.1 V n-ch and p-ch MOSFET:
0.04 μm <=LDES <=20 μm
0.12 μm <= WDES <= 50 μm
0.11 μm <=SA, SB
0.14 μm <=SD (NF>1)
0.08 μm <= SC ( for well edge is perpendicular to poly )
0.19 μm <= SC ( for well edge is parallel to poly )
0.14 μm <=SGA, SGB (for poly pitch)
0.32 μm <=SG2A, SG2B (for 2nd poly pitch)

Note: It is recommended to adopt multi-finger structures if WDES > 10 μm.

SAREF=SBREF=0.29μm and SCREF=2μm are the reference dimension
of STI-stress (LOD) effect and Well Proximity Effect (WPE).

Voltage range:
For 1.1V n-ch MOSFET:

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0V <= VGS <= 1.1V (*1.1)

0V <= VDS <= 1.1V (*1.1)
-1.1V(*1.1) <= VBS <= 0V
For 1.1V p-ch MOSFET:
0V>= VGS>= -1.1V (*1.1)
0V>= VDS>= -1.1V (*1.1)
1.1V(*1.1)≧ VBS>= 0V

Temperature range:
-40 ℃ ~ +125 ℃

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2 Monte Carlo DC Simulation Results for Process Variation

Two hundred Monte Carlo iterations are performed in the following simulation
conditions, and the following corner points show TT, SS, FF, SNFP and FNSP values
individually.
A reasonable number of Monte Carlo iterations is 30. The statistical significance of 30
iterations is quite high. If the circuit operates correctly for all 30 iterations, there is 99%
probability that over 80% of all possible component values operate correctly. The relative
error of a quantity determined through Monte Carlo analysis is proportional to (iteration
times)^(-1/2).

2.1 Threshold voltage in linear region VTLIN

The following figures show the Monte Carlo simulation results (process=1, mismatch=1)
of linear threshold voltage extracted at ID =10nA*WDES*0.9/(LDES*0.9+0.006um) for
NMOS and ID =-10nA*WDES*0.9/(LDES*0.9+0.006um) for PMOS at 25 ℃.

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

Vtlin(W=0.9um,L=0.9um) Vtlin(W=0.270um,L=0.036um)
3.20E-01 4.60E-01
_Corners _Corners
3.10E-01 4.40E-01
_MC_points _MC_points
4.20E-01
3.00E-01
4.00E-01
2.90E-01
Vtp(V)

Vtp(V)
3.80E-01
2.80E-01
3.60E-01
2.70E-01
3.40E-01
2.60E-01
3.20E-01
2.50E-01 3.00E-01
2.40E-01 2.80E-01
2.10E-01

2.20E-01

2.30E-01

2.40E-01

2.50E-01

2.60E-01

2.70E-01

2.60E-01
2.80E-01
3.00E-01
3.20E-01
3.40E-01
3.60E-01
3.80E-01
4.00E-01
4.20E-01
Vtn(V) Vtn(V)
Vtlin(W=0.9um,L=0.036um) Vtlin(W=0.108um,L=0.9um)
4.60E-01 3.20E-01
_Corners _Corners
4.40E-01 _MC_points 3.00E-01 _MC_points
4.20E-01
2.80E-01
4.00E-01
2.60E-01
Vtp(V)

Vtp(V)

3.80E-01
2.40E-01
3.60E-01
2.20E-01
3.40E-01

3.20E-01 2.00E-01

3.00E-01 1.80E-01
3.20E-01

3.40E-01

3.60E-01

3.80E-01

4.00E-01

4.20E-01

1.40E-01

1.60E-01

1.80E-01

2.00E-01

2.20E-01

2.40E-01
Vtn(V) Vtn(V)

Vtlin(W=0.54um,L=0.036um) Vtlin(W=0.108um,L=0.036um)
4.60E-01 4.60E-01
_Corners 4.40E-01 _Corners
4.40E-01
_MC_points _MC_points
4.20E-01
4.20E-01
4.00E-01
4.00E-01
3.80E-01
Vtp(V)

Vtp(V)

3.80E-01 3.60E-01
3.60E-01 3.40E-01
3.20E-01
3.40E-01
3.00E-01
3.20E-01
2.80E-01
3.00E-01 2.60E-01
2.80E-01 2.40E-01
2.80E-01

3.00E-01

3.20E-01

3.40E-01

3.60E-01

3.80E-01

4.00E-01

4.20E-01

2.50E-01

3.00E-01

3.50E-01

4.00E-01

4.50E-01

Vtn(V) Vtn(V)

Figure 2-1 Monte Carlo plots of threshold voltage at low drain bias

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

2.2 Threshold voltage in saturation region VTSAT

The following figures show the Monte Carlo simulation results (process=1, mismatch=1)
of saturation threshold voltage extracted at ID =10nA*WDES*0.9/(LDES*0.9+0.006um) for
NMOS and ID =-10nA*WDES*0.9/(LDES*0.9+0.006um) for PMOS at 25℃.
Vtsat(W=0.9um,L=0.9um) Vtsat(W=0.270um,L=0.036um)
3.10E-01 3.40E-01
_Corners 3.20E-01 _Corners
3.00E-01
_MC_points _MC_points
3.00E-01
2.90E-01
2.80E-01
2.80E-01
2.60E-01
Vtp(V)

Vtp(V)
2.70E-01 2.40E-01
2.60E-01 2.20E-01
2.00E-01
2.50E-01
1.80E-01
2.40E-01
1.60E-01
2.30E-01 1.40E-01
2.20E-01 1.20E-01
1.90E-01

2.00E-01

2.10E-01

2.20E-01

2.30E-01

2.40E-01

2.50E-01

1.60E-01
1.80E-01
2.00E-01
2.20E-01
2.40E-01
2.60E-01
2.80E-01
3.00E-01
3.20E-01
3.40E-01
Vtn(V) Vtn(V)
Vtsat(W=0.9um,L=0.036um) Vtsat(W=0.108um,L=0.9um)
3.20E-01 3.00E-01
_Corners _Corners
3.00E-01 _MC_points 2.80E-01 _MC_points
2.80E-01
2.60E-01
2.60E-01
2.40E-01
Vtp(V)

Vtp(V)

2.40E-01
2.20E-01
2.20E-01
2.00E-01
2.00E-01

1.80E-01 1.80E-01

1.60E-01 1.60E-01
2.20E-01

2.40E-01

2.60E-01

2.80E-01

3.00E-01

3.20E-01

1.20E-01

1.40E-01

1.60E-01

1.80E-01

2.00E-01

Vtn(V) Vtn(V)

Vtsat(W=0.54um,L=0.036um) Vtsat(W=0.108um,L=0.036um)
3.40E-01 4.00E-01
3.20E-01 _Corners _Corners
_MC_points 3.50E-01 _MC_points
3.00E-01
2.80E-01
3.00E-01
2.60E-01
Vtp(V)

Vtp(V)

2.40E-01
2.50E-01
2.20E-01
2.00E-01
2.00E-01
1.80E-01
1.60E-01 1.50E-01
1.40E-01
1.20E-01 1.00E-01
2.00E-01

2.20E-01

2.40E-01

2.60E-01

2.80E-01

3.00E-01

3.20E-01

1.50E-01

2.00E-01

2.50E-01

3.00E-01

3.50E-01

Vtn(V) Vtn(V)

Figure 2-2 Monte Carlo plots of threshold voltage at high drain bias
-19-
UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

2.3 Linear Current IDLIN

The following figures show the Monte Carlo simulation results (process=1, mismatch=1)
of linear current at 25℃.
Idlin(W=0.9um,L=0.9um) Idlin(W=0.270um,L=0.036um)
3.90E+00 5.00E+01
_Corners _Corners
3.80E+00 4.80E+01
_MC_points _MC_points
3.70E+00
4.60E+01
3.60E+00
4.40E+01
Idp(uA/um)

Idp(uA/um)
3.50E+00
4.20E+01
3.40E+00
4.00E+01
3.30E+00
3.80E+01
3.20E+00
3.10E+00 3.60E+01

3.00E+00 3.40E+01
1.15E+01

1.20E+01

1.25E+01

1.30E+01

9.00E+01

9.50E+01

1.00E+02

1.05E+02

1.10E+02

1.15E+02
Idn(uA/um) Idn(uA/um)
Idlin(W=0.9um,L=0.036um) Idlin(W=0.108um,L=0.9um)
4.30E+01 5.60E+00
4.20E+01 _Corners _Corners
_MC_points 5.40E+00 _MC_points
4.10E+01
4.00E+01 5.20E+00

3.90E+01 5.00E+00
Idp(uA/um)

Idp(uA/um)

3.80E+01
4.80E+00
3.70E+01
3.60E+01 4.60E+00
3.50E+01 4.40E+00
3.40E+01
4.20E+00
3.30E+01
3.20E+01 4.00E+00
9.00E+01

9.50E+01

1.00E+02

1.05E+02

1.10E+02

1.50E+01
1.55E+01
1.60E+01
1.65E+01
1.70E+01
1.75E+01
1.80E+01
1.85E+01
1.90E+01

Idn(uA/um) Idn(uA/um)

Idlin(W=0.54um,L=0.036um) Idlin(W=0.108um,L=0.036um)
4.80E+01 6.00E+01
_Corners _Corners
4.60E+01 _MC_points _MC_points
5.50E+01
4.40E+01

4.20E+01
Idp(uA/um)

Idp(uA/um)

5.00E+01
4.00E+01

3.80E+01 4.50E+01

3.60E+01
4.00E+01
3.40E+01

3.20E+01 3.50E+01
9.00E+01

9.50E+01

1.00E+02

1.05E+02

1.10E+02

9.50E+01

1.00E+02

1.05E+02

1.10E+02

1.15E+02

1.20E+02

1.25E+02

1.30E+02

1.35E+02

Idn(uA/um) Idn(uA/um)

Figure 2-3 Monte Carlo plots of linear current

-20-
UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

2.4 Saturation Current IDSAT

The following figures show the Monte Carlo simulation result (process=1, mismatch=1)
of saturation current at 25℃
Idsat(W=0.9um,L=0.9um) Idsat(W=0.270um,L=0.036um)
2.80E+01 4.00E+02
_Corners _Corners
2.70E+01 _MC_points 3.80E+02 _MC_points

2.60E+01 3.60E+02
Idp(uA/um)

Idp(uA/um)
2.50E+01 3.40E+02

2.40E+01 3.20E+02

2.30E+01 3.00E+02

2.20E+01 2.80E+02

2.10E+01 2.60E+02
7.40E+01

7.60E+01

7.80E+01

8.00E+01

8.20E+01

8.40E+01

8.60E+01

5.00E+02

5.50E+02

6.00E+02

6.50E+02

7.00E+02
Idn(uA/um) Idn(uA/um)
Idsat(W=0.9um,L=0.036um) Idsat(W=0.108um,L=0.9um)
3.40E+02 4.40E+01
3.30E+02 _Corners _Corners
_MC_points 4.20E+01 _MC_points
3.20E+02
3.10E+02 4.00E+01

3.00E+02 3.80E+01
Idp(uA/um)

Idp(uA/um)

2.90E+02
3.60E+01
2.80E+02
2.70E+02 3.40E+01
2.60E+02 3.20E+01
2.50E+02
3.00E+01
2.40E+02
2.30E+02 2.80E+01
4.80E+02

5.00E+02

5.20E+02

5.40E+02

5.60E+02

5.80E+02

6.00E+02

6.20E+02

1.10E+02

1.15E+02

1.20E+02

1.25E+02

1.30E+02

1.35E+02

1.40E+02

Idn(uA/um) Idn(uA/um)

Idsat(W=0.54um,L=0.036um) Idsat(W=0.108um,L=0.036um)
3.80E+02 4.80E+02
_Corners 4.60E+02 _Corners
3.60E+02 _MC_points _MC_points
4.40E+02
3.40E+02 4.20E+02
3.20E+02 4.00E+02
Idp(uA/um)

Idp(uA/um)

3.80E+02
3.00E+02
3.60E+02
2.80E+02 3.40E+02

2.60E+02 3.20E+02
3.00E+02
2.40E+02
2.80E+02
2.20E+02 2.60E+02
4.80E+02
5.00E+02
5.20E+02
5.40E+02
5.60E+02
5.80E+02
6.00E+02
6.20E+02
6.40E+02
6.60E+02

5.00E+02

5.50E+02

6.00E+02

6.50E+02

7.00E+02

7.50E+02

8.00E+02

Idn(uA/um) Idn(uA/um)

Figure 2-4 Monte Carlo plots of saturation current

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

2.5 Transfer Conductance GM

The following figures show the Monte Carlo simulation results (process=1, mismatch=1)
of transfer conductance at 25℃.
Gm(W=0.9um,L=0.9um) Gm(W=0.270um,L=0.036um)
1.20E-05 9.00E-05
_Corners _Corners
1.10E-05 _MC_points 8.00E-05 _MC_points
1.00E-05 7.00E-05

9.00E-06 6.00E-05
Gmp(S)

Gmp(S)
8.00E-06 5.00E-05

7.00E-06 4.00E-05

6.00E-06 3.00E-05

5.00E-06 2.00E-05

4.00E-06 1.00E-05
1.00E-05

1.20E-05

1.40E-05

1.60E-05

1.80E-05

2.00E-05

2.20E-05

2.00E-05

4.00E-05

6.00E-05

8.00E-05

1.00E-04

1.20E-04

1.40E-04
Gmn(S) Gmn(S)
Gm(W=0.9um,L=0.036um) Gm(W=0.108um,L=0.9um)
2.00E-04 2.40E-06
_Corners 2.20E-06 _Corners
1.80E-04 _MC_points _MC_points
2.00E-06
1.60E-04
1.80E-06
1.40E-04 1.60E-06
Gmp(S)

Gmp(S)

1.20E-04 1.40E-06

1.00E-04 1.20E-06
1.00E-06
8.00E-05
8.00E-07
6.00E-05 6.00E-07
4.00E-05 4.00E-07
1.00E-04

1.50E-04

2.00E-04

2.50E-04

3.00E-04

3.50E-04

1.00E-06

1.50E-06

2.00E-06

2.50E-06

3.00E-06

3.50E-06

4.00E-06

4.50E-06

Gmn(S) Gmn(S)

Gm(W=0.54um,L=0.036um) Gm(W=0.108um,L=0.036um)
1.60E-04 4.50E-05
_Corners _Corners
4.00E-05
1.40E-04 _MC_points _MC_points
3.50E-05
1.20E-04
3.00E-05
Gmp(S)

Gmp(S)

1.00E-04 2.50E-05

8.00E-05 2.00E-05
1.50E-05
6.00E-05
1.00E-05
4.00E-05
5.00E-06
2.00E-05 0.00E+00
5.00E-05

1.00E-04

1.50E-04

2.00E-04

1.00E-05

2.00E-05

3.00E-05

4.00E-05

5.00E-05

6.00E-05

7.00E-05

Gmn(S) Gmn(S)

Figure 2-5 Monte Carlo plots of transfer conductance

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

2.6 Output Conductance GDS

The following figures show the Monte Carlo simulation results (process=1, mismatch=1)
of output conductance at 25℃.
Gds(W=0.9um,L=0.9um) Gds(W=0.270um,L=0.036um)
2.00E-07 9.00E-06
_Corners _Corners
8.00E-06
1.80E-07 _MC_points _MC_points
7.00E-06
1.60E-07
6.00E-06
Gdsp(S)

Gdsp(S)
1.40E-07 5.00E-06

1.20E-07 4.00E-06
3.00E-06
1.00E-07
2.00E-06
8.00E-08
1.00E-06
6.00E-08 0.00E+00
1.50E-07

2.00E-07

2.50E-07

3.00E-07

3.50E-07

1.00E-06

2.00E-06

3.00E-06

4.00E-06

5.00E-06

6.00E-06

7.00E-06

8.00E-06
Gdsn(S) Gdsn(S)
Gds(W=0.9um,L=0.036um) Gds(W=0.108um,L=0.9um)
2.00E-05 5.00E-08
_Corners _Corners
1.80E-05 4.50E-08
_MC_points _MC_points
1.60E-05 4.00E-08
1.40E-05 3.50E-08
Gdsp(S)

Gdsp(S)

1.20E-05 3.00E-08
1.00E-05 2.50E-08
8.00E-06 2.00E-08
6.00E-06 1.50E-08
4.00E-06 1.00E-08
2.00E-06 5.00E-09
4.00E-06

6.00E-06

8.00E-06

1.00E-05

1.20E-05

1.40E-05

1.60E-05

1.80E-05

1.00E-08

2.00E-08

3.00E-08

4.00E-08

5.00E-08

6.00E-08

Gdsn(S) Gdsn(S)

Gds(W=0.54um,L=0.036um) Gds(W=0.108um,L=0.036um)
1.80E-05 5.00E-06
_Corners 4.50E-06 _Corners
1.60E-05
_MC_points _MC_points
1.40E-05 4.00E-06
3.50E-06
1.20E-05
3.00E-06
Gdsp(S)

Gdsp(S)

1.00E-05
2.50E-06
8.00E-06
2.00E-06
6.00E-06
1.50E-06
4.00E-06 1.00E-06
2.00E-06 5.00E-07
0.00E+00 0.00E+00
2.00E-06

4.00E-06

6.00E-06

8.00E-06

1.00E-05

1.20E-05

5.00E-07
1.00E-06
1.50E-06
2.00E-06
2.50E-06
3.00E-06
3.50E-06
4.00E-06
4.50E-06

Gdsn(S) Gdsn(S)

Figure 2-6 Monte Carlo plots of output conductance

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

3 Monte Carlo Dynamic Simulation Results for Process

Variation

3.1 Ring Oscillator Circuit

To assess the dynamic performance of these devices, a ring oscillator circuit with the
following configuration is adopted

Figure 3-1 Ring oscillator netlist diagram

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

Table 3-1 Ring oscillator (inverter) structure description for SA=0.099um

R.O. (Inverter) Structure description

Contact size 0.054 um X 0.054 um

Polysilicon gate to contact spacing 0.036 um

Contact to diffusion edge spacing 0.009 um

Without RC loading R = 0 ohm C = 0 fF

Inverter

Logic gate type Inverter

Channel width for n-ch MOSFET 0.27 um X 2

Channel length for n-ch MOSFET 0.036 um

Channel width for p-ch MOSFET 0.405 um X 2

Channel Length for p-ch MOSFET 0.036 um

Inverter Tpd
9.00E-12
_Corners
8.50E-12 _MC_points

8.00E-12
Tpd(second)

7.50E-12

7.00E-12

6.50E-12

6.00E-12

5.50E-12
6.50E+03

7.00E+03

7.50E+03

8.00E+03

8.50E+03

1/Idn+1/Idp(1/A)

Figure 3-2 Corner plot of ring oscillator

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

4 Monte Carlo Simulation Results for Mismatch

4.1 Threshold voltage in linear region VTLIN

The following figures show the Monte Carlo mis-matching simulation results of linear
threshold voltage extracted at ID =10nA*WDES*0.9/(LDES*0.9+0.006um) for NMOS and ID
=-10nA*WDES*0.9/(LDES*0.9+0.006um) for PMOS at 25℃.

Vt-Mismatch
1.20E-01
L=0.9um,y=(6.47e-3)x
L=0.18um,y=(4.50e-3)x
L=0.045um,y=(3.34e-3)x
1.00E-01 L=0.036um,y=(3.25e-3)x

8.00E-02
d(delta Vt)

6.00E-02

4.00E-02

2.00E-02

0.00E+00
0.00E+00

2.00E+00

4.00E+00

6.00E+00

8.00E+00

1.00E+01

1.20E+01

1.40E+01

1.60E+01

1/sqrt(W*L*MF)
Figure 4-1 VTLIN mis-matching simulation of 1.1V n-ch MOSFET

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Vt-Mismatch
6.00E-02
L=0.9um,y=(3.44e-3)x
L=0.18um,y=(2.74e-3)x
L=0.045um,y=(2.35e-3)x
5.00E-02 L=0.036um,y=(2.50e-3)x

4.00E-02
d(delta Vt)

3.00E-02

2.00E-02

1.00E-02

0.00E+00
0.00E+00

2.00E+00

4.00E+00

6.00E+00

8.00E+00

1.00E+01

1.20E+01

1.40E+01

1.60E+01
1/sqrt(W*L*MF)
Figure 4-2 VTLIN mis-matching simulation of 1.1V p-ch MOSFET

4.2 Saturation Current IDSAT

The following figures show the Monte Carlo mis-matching simulation results of
saturation current at 25℃.

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

Id-Mismatch
2.00E-01
L=0.9um,y=(1.19e-2)x
1.80E-01 L=0.18um,y=(0.76e-2)x
L=0.045um,y=(0.68e-2)x
L=0.036um,y=(0.6e-2)x
1.60E-01

1.40E-01

1.20E-01
d(delta Id/Id)

1.00E-01

8.00E-02

6.00E-02

4.00E-02

2.00E-02

0.00E+00
0.00E+00

2.00E+00

4.00E+00

6.00E+00

8.00E+00

1.00E+01

1.20E+01

1.40E+01

1.60E+01
1/sqrt(W*L*MF)
Figure 4-3 IDSAT mis-matching simulation of 1.1V n-ch MOSFET

Id-Mismatch
1.20E-01
L=0.9um,y=(0.7e-2)x
L=0.18um,y=(0.7e-2)x
L=0.045um,y=(0.7e-2)x
1.00E-01 L=0.036um,y=(0.7e-2)x

8.00E-02
d(delta Id/Id)

6.00E-02

4.00E-02

2.00E-02

0.00E+00
0.00E+00

2.00E+00

4.00E+00

6.00E+00

8.00E+00

1.00E+01

1.20E+01

1.40E+01

1.60E+01

1/sqrt(W*L*MF)

Figure 4-4 IDSAT mis-matching simulation of 1.1V p-ch MOSFET

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UMC Confidential - Do Not Copy 40nm Logic and Mixed-Mode Low Power with Regular Threshold Voltage 1.1V MOSFET
Monte Carlo SPICE Model Document. This document is the property of UMC. Its use is authorized only for
design of products manufactured by UMC.

5 Appendix

5.1 HSPICE Warning Message

Table 5-1 HSPICE warning message

Item Warning Message Explanation
1. Moin is too small for n/p mos. A small value of parameter Moin is
necessary to get good fitting in inversion
region of CV curve but would cause a
harmless warning in HSPICE.

5.2 ELDO Warning Message

Table 5-2 ELDO warning message

Item Warning Message Explanation
1. MOIN is too small for n/p mos. A small value of parameter Moin is
necessary to get good fitting in inversion
region of CV curve but would cause a
harmless warning in HSPICE.

5.3 SPECTRE Warning Message

Table 5-3 SPECTRE warning message

Item Warning Message Explanation
1. `Moin' is unusually small for n/p mos. A small value of parameter Moin is
necessary to get good fitting in inversion
region of CV curve but would cause a
harmless warning in HSPICE.

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