ELECTRONICS AND SUBJECT: CEC370

COMMUNICATION LOW POWER IC DESIGN

ENGINEERING

YEAR SEMESTER UNIT NO. : 03

III V LOW-VOLTAGE LOW-POWER
ADDERS

Downloadable at
Ms.G VIJAYAKUMARI,AP/ ECE
tiny.cc/npsb-elearning
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

OUTLINE

Introduction, Standard Adder Cells, CMOS Adder’s Architectures – Ripple

Carry Adders, Carry Look-Ahead Adders, Carry Select Adders, Carry Save
Adders, Low Voltage Low Power Design Techniques –Trends of Technology
and Power Supply Voltage, Low Voltage Low-Power Logic Styles.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 2

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Introduction

➢Addition is an obligatory operation that is crucial for processing the fundamental

arithmetic operations.
➢It is used extensively in many VLSI designs paradigms and is by far the most
frequently used operation in a general-purpose system and in application specific
processors.
➢The adder therefore which lies in the critical delay path, effectively determines the
systems overall speed.
➢On the other hand, the option of reducing the power consumption of the designed
adder, which for many years has been a narrow specialty, has been gaining
prominence.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 3

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Standard Adder Cells

Standard adder cells as a basic building blocks are used in designing and fabricating
of different kinds of adder architectures.
Half Adders:

➢The half adders are the simplest and most fundamental kind of adders.
➢It consists of two binary operands (A&B) that have a pair of single-bits as inputs

and produces a two-bit binary number (SC) as its resultant.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 4

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Half Adders:
Truth Table of a Half Adder

A B Sum (S) Cout (C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

➢ The low order bit of the resultant is known as “sum”.

➢ The higher bit of the resultant is known as “cout”.
➢ From the truth table,

Sum = A xor B
Cout = A.B

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 5

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

A full adder adds two binary numbers with a carry-in.

logic circuit of the conventional CMOS full adder.

➢ It is constructed using two half adders and an OR gate. There is a total of three
inputs for the full adder, two for the input numbers A and B, and one for the carry-
in Cin.
➢ The outputs are the sum and carry-out.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 6

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

Cin A B Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 0 0 1
1 0 1 1 0
1 0 0 0 1
1 1 1 0 1
1 1 0 1 1

Table: Truth Table Of A Full Adder

Sum = A xor B xor Cin

Cout = (A xor B).Cin + A.B

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 7

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

Conventional CMOS Full Adder

➢ The transistor level implementation of a conventional CMOS full-adder cell

design using a total of 32 transistors shown in below figure.
➢ It is modified version, based on CMOS transmission gates and inverters use only
20 transistors.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 8

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

Modified Conventional CMOS Full Adder

➢ The modified conventional CMOS full adder configuration has been widely
accepted and utilized in numerous applications; it often exhibits a critical delay
that actually limits the systems total performance.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 9

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

Logical Structure of a fast-full adder

➢ There is an alternative implementation of the full adder cell that does not use
XOR gates but instead use 28 transistors.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 10

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

Full adder without XOR gates; (a) logic diagram (b) transistor diagram

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 11

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

Transmission Function Full Adder (TFA

➢ TFA consists of 16 transistors and dissipates less power than conventional CMOS full
adder reported so far.
➢ Another schematic configuration of the full adder that ensures both low power and

high-speed performance is exemplified.

It is a combination of an XOR gate and a no. of transmission gates. It has 14 transistors
and occupies 30 and 20 percent less area than the modified conventional CMOS full
adder
UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 12
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

The 17-Transistor Full adder (17-T FA)

➢ Next a low power CMOS full adder cell consisting of 17 transistors is described. It
is based on XOR and XNOR gates and the pass transistors. Comparative analysis
has shown that it consumes 10 to 15 percent less power than either the T.F.A. or the
14-transistor full adder.
➢ These power savings are due to the fact that this cell has no short circuit power and
that its dynamic power, relative to the other two cells is lower.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 13

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full adders and their various schematic configurations:

The 10-Transistor Full adder (10-T FA)

Using a power supply voltage of 3.3v the critical path delay of the 10 transistor full
adder measures at 0.086ns while in the T.F.A it measures at 0.12ns. also, with the same
supply voltage and running a clock frequency of 1ghz the 10 transistor full adder has
an average dissipation of 81µw of power, where as the T.F.A dissipates about 170µw.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 14

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

CMOS ADDERS ARCHITECTURES

CMOS adders architectures consists of

a) R.C.A (ripple carry adder)

b) C.L.A (carry look ahead adders)
c) C.S.L (carry select adders)
d) C.S.A (carry save adders)
e) C.S.K (carry skip adders)
f) C.O.S (conditional sum adders)

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 15

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

RIPPLE CARRY ADDER

➢ The basic unit of a ripple carry adder is a full adder

➢ It can be extended indefinitely to any number by connecting the carry out of the
previous 1- bit full adder to the carry in for the next 1-bit full adder.
➢ the RCA occupies the smallest area and offers good performance for random
input data, but it is unfavorable choice for circuits with non-random inputs
because of delay characteristics, it depends heavily on the length of carry
propagation path.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 16

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

RIPPLE CARRY ADDER

➢ Since all the full adders are connected together by the carry chain a worst-case
addition will require the carry to ripple from the position of the least significant
bit to that of the most significant bit.
➢ The worst-case delay increases linearly with the length of carry propagation path
which depends on the no. of bits processed by the operand’s “n”.
➢ However, carry propagation can be enhanced by exploiting faster logic circuit
technologies and faster full adder designs RCA is subjected to a glitching
problem.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 17

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

RIPPLE CARRY ADDER

Static simulation of the 4- Delay time versus power supply voltage

bit RCA

Power Consumption of 4-bit RCA

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 18

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Carry Look- Ahead Adders (CLA)

➢ Carry ripple delays grow linearly with the size of the input operand for the RCA,
but these delays can be shortened by generating the carries of each stage in
parallel.
➢ It is an adder with time propagation duration in 0(logn) and whose area size
requirement is in 0(n*log n)
➢ The delay time of the CLA architecture therefore exhibits logarithmic dependency
on the size of the adder, which allows the propagation delay of the carry signal to
be minimized.
➢ In the CLA, however a carry does not depend explicitly on the preceding one. It
can, however, be expressed as a function of the relevant propagate and general
signals, Pi and Gi as well as the initial carry in Cin. Therefore, the CLA comes in
handy for better delay reduction performance.
➢ In addition, the CLA consumes more area and power because of its large number
of logic gates.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 19

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Carry Look- Ahead Adders (CLA)

➢ For particular combinations of inputs AI and BI the propagate signal PI determines

whether the carry in to the ith block would propagate to the output, where as the
generate signal GI determines if a carry out would be set from inside the block
independently from the inputs.
Gi = Ai .Bi Pi = Ai xor Bi
➢ Carry generation occurs when Ai= Bi = 1, a carry of 1 is produced at the ith position,

yet when Ai = Bi = 0, a carry of 0 gets generated.

➢ On the other hand, carry propagation occurs when Ai ≠ Bi for some i = 0, 1, 2,3,4,5,

then Cin is said to propagate to the fifth bit position.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 20

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Logic schematic of a 4-bit carry generator

Block diagram of a 4-bit CLA

➢ Besides the Pi and Gi signals, the Boolean variables for the CLA adder are
Si = Pi xor Ci
Ci+1 = Gi +Pi .Ci

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 21

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

VARIATION OF BASIC CLA

A Variation of basic CLA addition algorithm, namely the ELM adder will be
analyzed. The ELM addition algorithm incorporates a binary tree of simple
processors running 0 (log n) time and it is also based on the concept of carry
propagate and carry generate. The fig. shows the block diagram of 8- bit ELM
adder.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 22

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

VARIATION OF BASIC CLA

PERFORMANCE EVOLUTION
The 32-bit CLA and ELM adders have been simulated using the static CMOS
circuit design methodology.
Below table shows a clear explanation of the relative aspects of the adders. Note
that even though the CLA has more transistors than the ELM adder, it has shorter
interconnects and hence occupies a smaller area.

Adder type Area (*106 λ2) No. of transistors Delay Avg. power dissipation per
addition(mW)

CLA 2.27 2132 15 114.6

ELM 2.36 2078 10 104.1
RCA 0.80 1204 55 87.2

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 23

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Manchester Carry Chain (MCC) and Manchester Adder

Carry Generate: Gi = Ai. Bi
Carry Propagate: Pi = Ai xor Bi
Carry Annihilate: ANI = Ai . Bi = (Ai +Bi) 1
1 1

The Manchester adder uses the MCC as its carry network. The conceptual
representation and CMOS realization of a one stage MCC are depicted in fig. referring
to fig(a), a one stage MCC can be conceptually analyzed as having three switches each
manipulated by controlling signals Gi, Pi And ANi from the above equations. It is clear
that at any time, only one of the three signals Gi,Pi and ANi is at logic at 1.the carry out
signal Ci-1 is connected to 0. If ANi is high or to 1 if Gi is high, and to the incoming
carry Cin, if Pi is high.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 24

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Carry Select Adders

➢ The carry select adder provides a substantial compromise between the RCA,
which occupies a small area and has a longer delay, and the CLA, which occupies
a larger area and has a shorter delay.
➢ In the CSL both the n-bit operand, Ai and Bi are divided into k blocks of possibly
different sizes.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 25

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Carry Select Adders-Performance Evaluation

Layouts for the RCA and CSL adders were generated for the following sizes 8-
bit,16-bit,32- bit,64-bit and 128-bit.
The comparisons of the area sizes and performance delays for both types of
adders are summarized in below table.
No.of bits Area,λ2 Delay,ns
% change %change

RCA CSL RCA CSL

8 154624 290160 87.6 11.5 8.5 -26.0
16 382720 717889 87.5 25.0 11.5 -54.0
32 914400 1779904 94.6 52.5 21.5 -59.0
64 2439168 4667608 91.3 108.0 33.0 -69.4
128 7115072 13536432 90.2 226.0 54.0 -76.1
average 90.2 -56.9

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 26

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Hybrid Carry Look Ahead / Carry Select Adder

Hybrid adders which refer to the elementary combination of two or more design
pure design methods aim to reduce power dissipation improve cost effectiveness
and achieve other performance enhancements as well.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 27

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Carry save adders

• The RCA makes use of a row of cascaded binary F.A’S to compute the
summation of two operands. In fact, with slight modification this row of
F.A’S can also be viewed as a mechanism to reduce three binary numbers
into two binary numbers in multi operand addition.
• This method is used in the carry save adder where it is indeed an RCA with
its carries saved rather than propagated, therefore, the CSA operator is often
called a 3:2 counter.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 28

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Carry save adders

A CSA tree consists of CSA operators and one adder at the root of the tree. The
CSA operators are used to transform an arbitrary number of operands in the
addition process to produce two adding operands, after which the adder at the root
of the CSA tree computes the final sum.

T = (K-2).TCSA +TCPA

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 29

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Carry save adders

Performance Evolution:
Best timing ns Cell area under the best timing(λ2)

Number 8 24 40 56 64 8 24 40 56 64
of bits n
Without 3.12 8.46 13.16 17.17 19.33 802 1337 2245 3412 3873
CSA

With 2.72 8.06 12.77 15.57 18.12 364 1186 1993 2934 3341
CSA

Reduction 13 5 3 9 6 9 11 11 14 14

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 30

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Low-Voltage Low-Power Design Techniques

Trends of Technology and Power Supply Voltage

Most of the process technology studies for low voltage and low-power applications
converge to the conclusion that scaled BiCMOS/ CMOS technology will remain the
dominant solution in the future. The technology was at 95nm in 2001 and it is reduced to
65nm in 2003. It is conceivable that once the problem in manufacturing yield is
overcome, by 2016, the gate length will reduce to 13nm. As for the power supply
voltage, it was at 1.2V in 2001 and it is expected to experience a ladder like reduction to
0.9V by 2007. In the long term, it is predicted that it will continue to reduce to 0.6V by
2016due to probability and reliability issues.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 31

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Low-voltage low-power Logic Styles

High speed adder that uses low power consumption became a most crucial component
of processor, because it is heavily used in Arithematic Logic Unit, Floating Point Unit,
and for address generation during cache or memory access.
The relentless drive for adders with low power dissipation can be addressed at various
design levels, namely
a.Architecture level
b.Circuitlevel
c.Layout level
d.Device level and
e.Process Technology Level

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 32

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Static logic Style

Basic features of Static CMOS logic are

• Very low static power dissipation
• High noise margins (full rail to rail swing)
• Low output impedance, high input impedance
• No steady state path between VDD and GND
• Delay is function of load capacitance and transistor resistance
• Comparable rise and fall times (under the appropriate transistor sizing conditions)

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 33

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Static logic Style

Basic features of Static CMOS logic are

• Very low static power dissipation
• High noise margins (full rail to rail swing)
• Low output impedance, high input impedance
• No steady state path between VDD and GND
• Delay is function of load capacitance and transistor resistance
• Comparable rise and fall times (under the appropriate transistor sizing conditions)

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 34

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Dynamic logic Style

• The operation of all dynamic logic gates depends upon on temporary storage of
charge in parasitic.
• This operational property necessitates periodic updating of internal node voltage
levels, since stored charge in capacitor cannot retain indefinitely.
• Consequently, dynamic logic circuits require periodic clock signals in order to
control charge refreshing.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 35

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Dynamic logic Style

• In the following, a dynamic CMOS circuit technique which allows us to

significantly reduce the number of transistors used to implement any logic
function is introduced.
• The circuit based on first precharging the output node capacitance and
subsequently, evaluating the output level according to the applied inputs.
• The precharge phase is setting the circuit at a predefined initial state while the
actual logic response is determined during the evaluation phase.
• Static CMOS offers good performance but cannot keep up with dynamic logic
styles in terms of propagation delay.
• The shorter delays mostly have to be traded off for increased power dissipation.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 36

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

XOR/ XNOR Gate Implementation of Different logic styles

5 different logic styles namely

a. Full Static CMOS logic

b. Complementary Pass-transistor Logic (CPL)
c. Double Pass-transistor Logic (DPL)
d. Dual-rail Domino Dynamic Logic

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 37

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Full Static CMOS logic

The serial connection of pMOS or nMOS require increased width in order to acquire
a reasonable conducting current to drive capacitive loads. This is because
connecting pMOS or Nmos devices in series can be visualized as a number of
cascaded transistors. The delay time imposed by these devices is defined by

C- capacitance, R- Resistance,
W- Channel Width, L- Channel Length

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 38

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Complementary Pass-transistor Logic (CPL)

This logic style eliminates the problem of vigilantly sizing the series transistors,
there by requiring one half as many transistors as compared to the static CMOS
XOR gate. When the output of the nMOS pass transistor network at node X is
logically high, at (VDD – Vth), where Vth is the threshold voltage, it causes a
major setback by inducing an incomplete turnoff of the pMOS in the inverter,
thus resulting a high short circuit current. To restrain this current, a pMOS
device is then coupled across the output of the inverter gate in order to pull up
the output node X to full VDD

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 39

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Double Pass-transistor Logic (DPL)

By using both the pMOS and nMOS devices, the DPL prevents the problem of the
nMOS threshold voltage dropping in CPL logic design.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 40

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Dual-rail Domino Dynamic Logic

• Dynamic techniques require a precharge and evaluation phase.

• The precharge stage occurs when the CLK signal is at a low value, while the
evaluation stage takes place when the clock signal is at high value.
• Because of the precharge and evaluation phases dynamic design abolishes all the
spurious transitions and its corresponding power consumption, which is
intrinsically present in any static logic designs.

UNIT 3 LOW-VOLTAGE LOW-POWER ADDERS Ms. G VIJAYAKUMARI, AP/ ECE 41