DEPARTMENT OF ELECTRONICS & COMMUNICATION
8EC4.2: VHDL
UNIT-1 TUTORIAL SHEET NO.: 01(A)
Q1. Explain any five VHDL statements using example for each. (RU 2009) Q2. Explain package and entity declaration. (RU 2009) Q3. Explain dataflow style and structural style of modeling with suitable example. (RU 2011) Q4. Explain entity declaration in VHDL. (RTU 2011) Q5. Describe and write the syntax for the packages in connection with VHDL. Q6. Explain the lexical elements? Q7. Explain signals and variables in VHDL. Mention out the differences between them with suitable example. Q8. Explain different type of operators available in VHDL. Q9. Write short note on modeling with Hardware Description Language. DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 1 TUTORIAL SHEET NO.: 1(B) Q1. Explain architecture declaration in VHDL. (RTU 2011) Q2. Explain different modeling styles used in VHDL. A synthesis output will be in which kind of modeling style? Q3. What are FPGA ? Q4. What data types are available in VHDL? Explain in brief. Q5. What types of port modes are available in VHDL? Explain briefly. Q6. In which case will you prefer a buffer port opposed to an inout port and why? DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL UNIT 1 TUTORIAL SHEET NO.: 01(C) Q1. Write short note on concurrent assignment statements. (RU 2008) Q2. Define synthesis, simulation and testbench in VHDL and also differentiate them with example (at least five points) (RU 2008 back) (RU 2006) Q3. Draw the schematic of ASIC design flow and explain every step in brief. (RTU 2011) Q4. Explain the history of various hardware description languages. (RTU 2011) Q5. Differentiate between floor planning and placement. Q6. Differentiate between FPGA and CPLD.
Q7. Explain Gajskis Chart. DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 2 TUTORIAL SHEET NO.: 01(A) Q1. Write VHDL code for 16:1 mux using 4 x 1 MUX with package style. Draw the circuit in the block diagram form. (RU 2006) Q2. Implement F(A,B,C)= using a multiplexer. (RU 2009) Q3. Write VHDL code for the multiplexer in the above code. (RU 2009) Q4. Apply Shannons expansion theorm to implement the function: Using 4 to 1 mux. (RU 2008) Q5. Write VHDL code for implementation of f(A,B,C)= using MUX. (RU 2006) Q6. Explain multiplexer synthesis using Shannons expansion and prove Shannons expansion theorm. (RTU 2011) Q7. Write VHDL code for 2 to 1 multiplexer specified using if then else statement. (RTU 2011) Q8. Draw the digital logic diagram for a VHDL code for architecture given as follows: ARCHITECTURE logic OF fa IS BEGIN s <= x XOR y XOR cin; c <= (x AND y) OR (y AND cin) OR (x AND cin); END logic; [RU-2005] Q9. Write VHDL code for a 4 x 1 mux using selected signal assignment statement. Q10. Write the VHDL code for 8 x 1 multiplexer using case statements. DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 2 TUTORIAL SHEET NO.: 01(B) Q1. Implement a 4 to 16 binary decoder using 2 to 4 decoder, write its VHDL using GENERATE statement. (RU 2006) Q2. Show that the function Can be implemented using a 3 to 8 binary decoder and an OR gate. (RU 2008 back) Q3. Write VHDL code for the circuit derived in question above. (RU 2008) Q4. Write VHDL code for the BCD to 7-segment decoder. (RU 2009) Q5. Implement a 3 to 8 binary decoder using 2 to 4 decoder, write its VHDL code.
Q6. Write the VHDL code for 4 x 2 priority encoder. [ RU-2007 ] Q7. Write VHDL code for Binary to gray converter. Q8. Write VHDL code for Gray to binary converter. DEPARTMENT OF ELECTRONICS & COMMUNICATION 8EC4.2: VHDL Unit 2 TUTORIAL SHEET NO.: 01(C) Q1. Write short note on Code converter. (RU 2009) Q2. Write VHDL code for BCD to 7-segment decoder using CASE statement. (RU 2008) Q3. Write a package declaration fulladd-package which provides component declaration for fulladd entity. Then write VHDL code for a four bit ripple carry adder using the component fulladd defined in the above package. (RU 2008) Q4. Draw the structural diagram of a serial adder and explain each block of it with waveform. (RU 2008 back) Q5. Using conditional signal assignment statement write VHDL code for 8 to 3 encoder. (RU 2007) Q6. How will you implement a serial adder in VHDL? (RU 2007) Q7. Write VHDL code for Binary to BCD encoder. (RU 2006) Q8. Write VHDL code for: (RU 2006)
Data O/P Clk
