Fall 2024 CA Lab-9
Namal University, Mianwali
Department of Electrical Engineering
EE-459L – Computer Architecture (Lab)
Lab -9
Assembler-Driven Testing for Single-Cycle RISC-V Processor
Student’s Name
Roll No.
Date Performed
Marks Obtained
Course Instructor: Lab Instructor:
Dr. Tassadaq Hussain Engr. Majid Ali
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Fall 2024 CA Lab-9
Document History
Rev. Date Comment Author
1.0 23/10/2023 Initial draft Engr. Maria Rehman
1.1 06/10/2024 Modified Engr. Majid Ali
Instructions
Read the manual carefully before start of any tasks / experiments.
Carefully handle all equipment available in the lab.
Carefully write your particulars at first page on the manual.
In case of simulation at PC, try to avoid opening of unnecessary tabs.
Submit PDF report of each lab at Q-OBE, attach all findings in report properly.
Write precise conclusion of every lab.
Submission time is end of respective lab session for each manual, late submission of
manual is not acceptable.
Fill manual individually even in case of group work.
Plagiarism will be dealt with strict consequences.
Objectives
At the end of this lab, students will understand how an assembler works and will learn that
they no longer need to manually initialize the program memory. Instead, they will use the
assembler to convert the assembly program into a compatible hex file.
Learning Outcomes
This lab satisfies the following learning outcomes of the course:
CLO2: Assembles components of microprocessors using various tools.
CLO3: Present concise and comprehensive technical reports.
Equipment & Components
Computer with Ubuntu OS installed.
Icarus Verilog for simulation.
GTKWave for waveform analysis.
RISC-V Assembler for converting assembly code to hex file.
Introduction
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Fall 2024 CA Lab-9
In the previous lab, you saw how we manually initialized the program memory by directly
inputting machine instructions. However, in this lab, we will streamline the process by using
the RISC-V assembler. Instead of manually loading instructions into memory, the assembler
will convert assembly code into a compatible hex file. This hex file will then be used to
initialize the program memory automatically. By the end of this lab, you will understand how
an assembler works and how to leverage it to simplify the process of loading programs into
the RISC-V processor.
Fig.1: Single Cycle Datapath
Use the RISC-V Toolchain:
Ensure you have the RISC-V GNU toolchain installed (riscv64-unknown-elf-as and riscv64-
unknown-elf-objcopy).
Assemble the Code: Assemble the program.s file into an object file:
riscv64-unknown-elf-as -march=rv32i -o program.o program.s
Convert the Object File to a Flat Binary: Convert the object file into a hex format:
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Fall 2024 CA Lab-9
riscv64-unknown-elf-objcopy -O verilog program.o program.hex
Prepare the Hex File: The program.hex file will now contain the hexadecimal instructions
compatible with readmemh. i.e.,
Assembly Program:
li t0, 21 # t0 = 21
addi x22, t0, 3 # x22 = t0 + 3
li t0, 8 # t0 = 8
ori x9, t0, 1 # x9 = t0 | 1
li t1, 15 # t1 = 15
lw x8, 15(t1) # x8 = Mem[t1 + 15]
li t1, 3 # t1 = 3
lw x9, 3(t1) # x9 = Mem[t1 + 3]
li t0, 15 # t0 = 15
li t1, 12 # t1 = 12
sw t0, 12(t1) # Mem[t1 + 12] = t0
li t0, 14 # t0 = 14
li t1, 10 # t1 = 10
sw t0, 10(t1) # Mem[t1 + 10] = t0
li t0, 9 # t0 = 9
li t1, 9 # t1 = 9
beq t0, t1, end # if t0 == t1, jump to end
end:
nop # no operation
Hex File:
@00000000 93 02 00 01 13 03 90 01 B3 86 62 00 93 02 80 00 13 03 30 00 B3 82 62 40 93 02
20 00 13 03 30 00 B3 F0 62 00 93 02 30 00 13 03 50 00 33 E2 62 00 93 02 50 01 13 8B 32 00
93 02 80 00 93 E4
Load into Verilog Instruction Memory: The resulting hex file can be loaded into instruction
memory using:
initial begin
$readmemh("program.hex", IMemory);
end
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Fall 2024 CA Lab-9
Fig.2: Turning source code.
Lab Task 1:
Use the RISC-V assembler to convert your assembly program into a hex file, modify the
instruction memory setup to load the hex file and verify that the program is correctly loaded
into memory and ready for execution.
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Fall 2024 CA Lab-9
Conclusion
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Fall 2024 CA Lab-9
CLO2: Assembles components of microprocessors using various tools.
CLO3: Present concise and comprehensive technical reports.
Domain Criteria Excellent (10) Good (8-9) Satisfactory (6- Improvement(4-5) Marks
7) Obtained
Successfully Successfully Had difficulty Did not complete tasks
Building completed tasks with completed tasks completing tasks and and struggled with lab
Psychomotor Processor understanding and but with some used lab equipment equipment
(P4) (CLO-2) good use of understanding with errors.
equipment. gaps
Presented outstanding Presented Provided basic Unable to answer
Report and detailed reports. comprehensive answers in reports questions and had
Writing
reports with some with limited significant knowledge
Affective (A2)
(CLO-3)
minor gaps. knowledge gaps. gaps.
Answered questions Answered Answered questions Unable to answer
confidently and questions with basic questions and was not
Lab Viva showed exceptional comprehensively understanding and confident.
(CLO-3) knowledge and and exhibited limited knowledge.
comprehension. strong knowledge
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