Communication Engineering 2
DIGITAL MODULATION
(Phase-Shift Keying)
ENGR. JOMER V. CATIPON
“ Even though I walk through the valley
of the shadow of death, I will fear no
evil, for you are with me; your rod and
your staff, they comfort me.”
- Psalm 23:4
PHASE SHIFT KEYING
Another form of angle – modulated, constant amplitude digital modulation.
PSK is a M-ary digital modulation scheme similar to conventional phase
modulation except that with PSK, the input is a binary digital signal and
there are limited number of output phases possible.
Binary PSK – the simplest form of PSK where N =1 and M = 2
Quaternary PSK - Is a M-ary encoding scheme where N = 2 and M = 4.
8-PSK - Is a M-ary encoding scheme where N = 3 and M = 8.
16-PSK - Is a M-ary encoding scheme where N = 4 and M = 16.
1. BINARY PHASE - SHIFT KEYING
The simplest form of PSK where N = 1 and M = 2. Therefore BPSK
has two phases, 2N = 21 = 2, are possible for the carrier. One phase
represents logic 0, the other, logic 1.
As the input digital signal changes state, the phase of the output carrier
shifts between two angles separated by 180 degrees.
Another name is phase - reversal keying, PRK and biphase
modulation.
BPSK is a form of square wave modulation of a continuous wave, CW
signal.
BPSK TRANSMITTER
The balanced modulator acts as a phase reversing switch.
Depending on the logic condition of the digital input, the carrier is transferred
to the output either in phase or 180 degrees out of phase with the reference
carrier oscillator.
BALANCED RING MODULATOR
The balanced ring modulator has two inputs:
a carrier that is in phase with the reference oscillator
and the binary digital data.
For the balanced modulator to function properly, the digital input voltage must be much
greater than the peak carrier voltage.
This ensures that the digital input controls the on/off state of diodes D1 to D4.
If the binary input is logic 1 ( a positive voltage), diodes D1 and D2 are
forward biased and ON. While diodes D3 and D4 are reverse biased
and OFF.
A carrier voltage is created across transformer T2 that is in phase with the
carrier voltage across T1.
Consequently, the output signal is in phase with the reference oscillator.
If the binary input is logic 0 ( a negative voltage), diodes D1 and D2 are
reverse biased and OFF. While diodes D3 and D4 are forward biased
and ON.
A carrier voltage is created across transformer T2 that is 180 degrees out
of phase with the carrier voltage across T1.
Consequently, the output signal is 180 degrees out of phase with the
reference oscillator.
BPSK truth table, phasor diagram and constellation diagram
Truth table
constellation diagram ( also called
signal state – space diagram
Phasor diagram
BANDWIDTH CONSIDERATIONS OF BPSK
A balanced modulator is a product modulator. The output signal is the product of two
input signals.
Mathematically, the output of a BPSK modulator is proportional to:
BPSK output = [sin(2fat) X sin(2fct)]
Where:
fa – maximum fundamental frequency of binary input in Hertz
fc – reference carrier frequency in Hertz
Solving for the trigonometric identity for the product of two sine functions,
Thus, the minimum double-sided Nyquist bandwidth, B is:
And because fa = fb/2, where fb = input bit rate,
Where B is the minimum double sided Nyquist bandwidth
OUTPUT PHASE VS TIME RELATIONSHIP FOR A BPSK MODULATOR
Note that the time of one BPSK signaling element (ts) is equal to the time of one
information bit (tb) which indicates that the bit rate equals the baud.
EXAMPLE:
For a BPSK modulator with a carrier frequency of 70 MHz and an input
bit rate of 10 Mbps, determine the maximum and minimum upper and
lower side frequencies, draw the output spectrum, determine the
minimum Nyquist bandwidth and calculate the baud.
For a BPSK modulator with a carrier frequency of 70 MHz and an
input bit rate of 10 Mbps, determine the maximum and minimum
ANSWER: upper and lower side frequencies, draw the output spectrum,
determine the minimum Nyquist bandwidth and calculate the baud.
Using BPSK output = [sin(2fat) X sin(2fct)]
= [sin 2(5 MHz)t][sin2(70 MHz)t)]
= ½ cos 2(70 MHz - 5 MHz)t – ½ cos 2 (70 MHz + 5 MHz)t
lower side frequency upper side frequency
Minimum lower side frequency(LSF)
LSF = 70 MHz – 5 MHz = 65 MHz
Maximum upper side frequency(USF)
USF = 70 MHz + 5MHz = 75 MHz
The minimum Nyquist bandwidth is B = 75 MHz – 65 MHz = 10 MHz
Baud = fb = 10 Mbaud
BPSK RECEIVER
The input signal may be +sin ct or -sin ct.
The coherent carrier recovery circuit detects and regenerates a carrier signal that is
both frequency and phase coherent with the original transmit carrier.
The balanced modulator is a product detector, the output is a product of the two
inputs, the BPSK signal and the recovered carrier.
The low pass filter LPF separates the recovered binary data from the complex
demodulated signal.
For a BPSK input signal of +sin ct, logic 1, the output of the balanced
modulator is:
Or:
Leaving:
The LPF has a cut off frequency much lower than 2c and thus, blocks the
second harmonic of the carrier and passes only the positive constant
coefficient. A positive voltage represents a demodulated logic 1.
For a BPSK input signal of –sin ct, logic 0, the output of the balanced
modulator is:
Or:
Leaving:
The output of the balanced modulator contains a negative voltage
(-[1/2] V) and a cosine wave at twice the carrier frequency 2c . Again,
the LPF blocks the second harmonic of the carrier
QUARTERNARY PHASE - SHIFT KEYING
QPSK, or quadrature PSK, is another form of angle modulated, constant
amplitude digital modulation.
Is a M-ary encoding scheme where N = 2 and M = 4.
With QPSK, four output phases are possible for a single carrier frequency.
In the modulator, each dibit code generates one of the four possible output
phases, +45, +135, -45 and -135 degrees.
For each two bit dibit clocked into the modulator, a single output change
occurs, and the rate of change at the output (baud) is equal to one-half the
input bit rate
QPSK TRANSMITTER
Two bits ( a dibit) are clocked into a bit splitter. After both bits have been
serially inputted, they are simultaneously parallel outputted. One bit is
directed to the I channel and the other to the Q channel. The I bit
modulates a carrier that is in phase with the reference oscillator, hence the
name “I” for in phase channel, and the Q bit modulates a carrier that is 90
degrees out of phase or in quadrature with he reference carrier, hence the
name “Q” for quadrature channel. Once a dibit has been split into the I
and Q channels, the operation is the same as the BPSK modulator. A
QPSK modulator is essentially two BPSK modulators combined in parallel.
For logic 1 = +1 V and logic 0 = -1 V, two phases are possible at the output of
the I balanced modulator and that is +sin ct and -sin ct .
Two phases are possible at the output of the Q balanced modulator, +cos ct
and -cos ct
When the linear summer combines the two quadrature signals, there are 4
possible resultant phasors: +sin ct +cos ct, +sin ct -cos ct, -sin ct
+cos ct and -sin ct -cos ct.
EXAMPLE
For the QPSK modulator shown below, construct the truth table, phasor
diagram and the constellation diagram.
ANSWER:
For a binary data input of Q = 0 and I = 0, the two inputs to the I
balanced modulator are -1 and sin ct and the two inputs to the Q
modulator are -1 and cos ct .
The outputs are:
I balanced modulator = (-1)(sin ct ) = -1 sin ct
Q balanced modulator = (-1)(cos ct ) = -1 cos ct
And the output of the linear summer is:
-1 sin ct -1 cos ct = 1.414 sin(ct -135)
Truth table
Phasor diagram
Constellation diagram
OUTPUT PHASE VERSUS TIME RELATIONSHIP FOR A QPSK
MODULATOR
BANDWIDTH CONSIDERATIONS OF QPSK
With QPSK, because the input data are divided into two channels, the bit rate
in either the I or the Q channel is equal to one-half of the input data rate,
fb/2.
The highest fundamental frequency present at the data input to the I or the Q
balanced modulator is equal to ¼ of the input data rate.
The output of the I and Q balanced modulators requires a minimum double-
sided Nyquist bandwidth equal to ½ of the incoming bit rate, fN = twice
fb/4 = fb/2
