Reg. No.
:
Name :
Continuous Assessment Test II – October 2023
Programme : B.Tech (ECM) Semester : FS 2023-24
Course : Code : BCSE205L
Class Nbr : CH2023240100476
Computer Architecture and Organization
CH2023240100479
CH2023240100481
Faculty : Dr. Manimaran Slot :
Dr. Saravana Kumar R G2+TG2
Dr. Sivakumar S
Time : 90 Minutes Max. Marks : 50
Answer ALL the questions
Sub.
Q.No. Questions Marks
Sec.
1. A program is run on a 60 MHz processor. The executed program consists of
the following instruction and clock count. Determine
(i) Cycles Per Instruction
(ii) Millions of Instruction Per Second
(iii) Execution time for the program.
Type of operation Instruction Clock Cycles for
Count executing each
instruction 6
Arithmetic 32,000 3
Logical 28,000 2
Data transfer 13,000 1
Branching 6000 2
2. i) Consider a scenario where a computer processor needs to execute
instructions allowing for a fewer instruction set with no control memory
requirements? Identify the type of control unit which would be more suitable
for this scenario and justify your choice based on the requirements of the given
task? (3 marks)
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(ii) Consider Computers M1 and M2 are two implementations of the same
instruction set. M1 and M2 are having the clock rates of 100 MHz and 50 MHz
respectively. M1 has a CPI of 3.8 and M2 has a CPI of 4.2 for a given program.
Find the Instruction per second of M1 and M2 computers and Identify which
computer is faster. (3 marks)
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3. The memory unit has the following:-
Main memory size = 8 GB
Cache memory size = 2 MB
The block size = 8 KB
The above memory structure is mapped by Fully associative and Direct
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mapping method.
(i) Find the physical address split up and tag directory size for the above
mapping. (7 Marks)
(ii) Analyse the performance of the above mapping techniques based on the
number of comparisons in tag address and Hit ratio. (3 Marks)
4. For a scalable RAM configuration, if the basic RAM size = 64 x 8 and the
required RAM size = 512 x 8. Find the following:-
i) Number of 64 x 8 RAM chips required to design 512 x 8
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RAM
ii) Number of address bits.
iii) Decoder size.
5. i) In many computers the cache block size is in the range 32 to 128
bytes. What would be the main advantages and disadvantages of
making the size of the cache blocks larger or smaller? Analyse due
to cache memory how the processing speed of the system will be
increased. (6 marks) 10
ii) In a computer system the memory unit has a 15-bit address line and
memory is byte addressable. Find
a. The total number of address locations in the memory unit
b. The size of the total memory unit. (4 marks)
6. (i) The size of the word count register of a DMA controller is 32 bits.
The processor needs to transfer a file of 29,154 MB from disk to
main memory. The memory is byte addressable. Find the minimum
number of times the DMA controller needs to get control of the
system bus from the processor to transfer the file from disk to main
memory. (2 Marks)
(ii) The given scenario discusses two methods for transferring 8 KB of
data from a pen drive to main memory: interrupt-driven method and
DMA method.
In the interrupt-driven method, the instructions are executed as per
Figure.1. Instruction that takes 3 clock cycles to execute if it is a
non-LOAD/STORE instruction. The LOAD/STORE instructions
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take 6 clock cycles to execute. The total performance of the
interrupt-driven method depends on the total number of clock cycles
required to transfer 8 KB data.
On the other hand, the DMA method involves a DMA controller,
which requires 25 clock cycles for initialization and overheads.
Each DMA transfer cycle takes 2 clock cycles to transfer a byte of
data from the pen drive to main memory. In order to analyze the
performance of both methods, it would be needed to compare the
total number of clock cycles by each method to transfer the 8 KB of
data. Additionally, you may want to calculate the efficiency and
speed of each method to determine which approach is more
effective for this specific data transfer task. (5 Marks)
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Figure 1
7. An interrupt in a microprocessor is like an urgent signal, diverting the
processor's attention to handle a priority task through an interrupt service
routine (ISR). It's a quick pause in regular operations for immediate action. As
per below scenarios, identify the type of the interrupt occurred.
1. Pressing the "D" key on the keyboard of your computer.
2. When restarting a mobile/computer, it takes 30 to 40 seconds to power on.
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During this time, pressing any keys.
3. In the event of a car collision with another vehicle, the pressure sensor
gives the interrupt to the processor to open the airbag inside the car.
4. When an interrupt occurs, the processor holds the address of the
Interrupt Service Routine (ISR).
5. To type "DDDDDDDDDD" (10 times) on a mobile phone, You should press
and release the “D” key 10 times.
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