UNIT I - MOS TRANSISTOR PRINCIPLES

MOS logic families (NMOS and CMOS), Ideal and Non Ideal IV Characteristics, CMOS
devices, MOS(FET) Transistor Characteristic under Static and Dynamic Conditions,
Technology Scaling, power consumption.

INTRODUCTION (VLSI):

The level of integration of chips is classified as

• Small Scale Integration (SSI)

• Medium Scale Integration (MSI)
• Very Large Scale Integration (VLSI)
• Ultra Large Scale Integration (ULSI)

Small scale Integration:

• Small-Scale Integration (SSI) circuits have less than 10 gates. Example: 7404 inverter.

Medium scale Integration:

• Medium-Scale Integration (MSI) circuits have up to 1000 gates. Example: 74161 counter.

Large scale Integration:

• Large-Scale Integration (LSI) circuits have up to 10,000 gates. Example: 8-bit

microprocessor (8085).

Very large scale Integration:

• Very large scale Integration (VLSI) with gates counting up to lakhs. Example: 16-bit
microprocessor (8086).
• The feature size of a CMOS manufacturing process refers to the minimum dimension of a
transistor that can be reliably built.

Ultra large scale Integration:

Ultra Large-Scale Integration (ULSI) is the process of integrating millions of transistors on a

single silicon semiconductor microchip.
1. MOS logic families (NMOS and CMOS):

nMOS and pMOS transistor:

• A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing layers of

conducting and insulating materials.
• CMOS technology provides two types of transistors. They are n-type transistor (nMOS)
and p- type transistor (pMOS).
• As transistor operation is controlled by electric fields, the devices are also called Metal
Oxide Semiconductor Field Effect Transistors (MOSFETs).
• The transistor consists of a stack of the conducting gate, an insulating layer of silicon
dioxide (SiO2) and the silicon wafer, also called as substrate, body or bulk.
• A pMOS transistor consists of p-type source and drain region with an n-type body.
• An nMOS transistor consists of n-type source and drain region with a p-type body.

Figure 1: (a) n-MOS transistor (b) p-MOS transistor

nMOS Transistor:

• In an nMOS transistor, the body is grounded and the p–n junction of the source and drain
to body are reverse-biased.
• As the gate is grounded, no current flows through junction. Hence, the transistor is OFF.
• If the gate voltage is raised, it creates an electric field, that start to attract free electrons to
the underside of the Si–SiO2 interface.
• If the voltage is raised more, a thin region under the gate called the channel is inverted.
• Since a conducting path of electron carriers is formed from source to drain, current starts
to flow. So, the transistor is said to be ON.

pMOS Transistor:

• For a pMOS transistor, the body is held at a positive voltage.

• When the gate terminal has a positive voltage, the source and drain junctions are reverse-
biased and no current flows. So, the transistor is said to OFF.
 • When the gate voltage is lowered, positive charges are attracted to the underside of the
Si– SiO2 interface.
• When a sufficient low gate voltage is applied, the channel inverts and a conducting path
of positive carriers is formed from source to drain, which makes the transistor ON.

NOTE:

• The symbol for the pMOS transistor has a bubble on the gate, indicating that the
transistor behavior is opposite to nMOS.
• When the gate of an nMOS transistor is 1, the transistor is ON. When the gate is 0, the
nMOS transistor is OFF.
• A pMOS transistor is ON when the gate is low(0) and OFF when the gate is high(1).

Modes of MOS TRANSISTOR:

• The MOS transistor is a majority-carrier device, in which the current in a conducting

channel
is controlled by gate voltage.
• In an nMOS transistor, the majority carriers are electrons.
• In a pMOS transistor, the majority carriers are holes.
• Figure 2 shows a simple MOS structure. The top layer of the structure is a good
conductor called the gate.
• Transistor gate is polysilicon, i.e., silicon formed from many small crystals. The middle
layer is a very thin insulating film of SiO2, called the gate oxide. The bottom layer is the
doped silicon body.
• The figure 2 shows a p-type body, in which the carriers are holes. The body is grounded
and voltage is applied to the gate.
• The gate oxide is a good insulator, so almost zero current flows from the gate to the body.

Accumulation (Enhancement) mode:

• In Figure 2(a), when a negative voltage is applied to the gate, negative charges are
formed on the gate.
• The positively charged holes are attracted to the region under the gate. This is called the
accumulation mode.

Depletion mode:

• In Figure 2(b), when a small positive voltage is applied to the gate, positive charges are
formed on the gate.
• The holes in the body are repelled from the region directly under the gate, resulting in a
depletion region forming below the gate.
Inversion layer:

• In Figure 2(c), when a higher positive potential greater than threshold voltage (Vt) is
applied, more positive charges are attracted to the gate.
• The holes are repelled and some free electrons in the body are attracted to the region
under the gate. This conductive layer of electrons in the p-type body is called the
inversion layer.
• The threshold voltage depends on the number of dopants in the body and the thickness tox
of the oxide.

Figure 2: MOS structure demonstrating (a) accumulation, (b) depletion, and (c) inversion layer

Operating regions of MOS transistor:

The MOS transistor operates in cutoff region, linear region and saturation region

Cutoff region:

• In Figure 3(a), the gate-to-source voltage (Vgs) is less than the threshold voltage (Vt) and
source is grounded.
 • Junctions between the body and the source or drain are reverse biased, so no current
flows. Thus, the transistor is said to be OFF and this mode of operation is called cutoff.
• If Vgs < Vt , the transistor is cutoff (OFF).

Linear (Active) Region:

• In Figure 3(b), the gate voltage is greater than the threshold voltage.
• An inversion region of electrons, called the channel connects the source and drain,
creating a conductive path and making the transistor ON.
• If Vgs > Vt , the transistor turns ON. If Vds is small, the transistor acts as a linear resistor,
in which the current flow is proportional to Vds.
• The number of carriers and the conductivity increases, with the gate voltage.
• The voltage between drain and source is Vds = Vgs – Vgd. If Vds = 0 (i.e., Vgs = Vgd), there
is no electric field to push current from drain to source.
• When a small positive voltage Vds is applied to the drain (Figure 3(c)), current Ids flows
through the channel from drain to source.
• This mode of operation is termed as linear, resistive, triode, non-saturated, or unsaturated.

Figure 3: nMOS transistor demonstrating cutoff, linear, and saturation regions of operation
 Saturation region:

• The current increases with increase in both the drain voltage and gate voltage.
• If Vds becomes sufficiently large that Vgd < Vt , the channel is no longer inverted near
the drain and becomes pinched off (Figure 3(d)).
• As electrons reach the end of the channel, they are injected into the depletion region
near the drain and accelerated toward the drain.
• Above this drain voltage, current Ids are controlled only by the gate voltage. This
mode is called saturation.
• If Vgs > Vt and Vds is large, the transistor acts as a current source, in which the current
flow becomes independent of Vds.

• The pMOS transistor in Figure 4 operates in just the opposite fashion. The n-type
body is tied to high potential, junctions of p-type source and drains are normally
reverse-biased.
• When the gate has high potential, no current flows between drain and source.
• When the gate voltage is lowered by a threshold Vt, holes are attracted to form a p-
type channel beneath the gate, allowing current to flow between drain and source.

2. IDEAL I-V CHARACTERISTICS OF MOS TRANSISTOR:

MOS transistor has three regions of operation

• Cutoff (or) sub threshold region

• Linear region (or) Non saturation region
• Saturation region
• The current through an OFF transistor is zero. When a transistor turns ON (Vgs > Vt), the
gate attract electrons to form a channel.
• Current is measured from the amount of charge in the channel.
• The charge on each plate of a capacitor is Q = CV. Thus, the charge in the channel
Qchannel is
Qchannel = Cg (Vgc – Vt)
 where Cg : Capacitance of the gate to the channel
Vgc - Vt : Amount of voltage attracting charge to the channel.
If the source is at Vs and the drain is at Vd ,
Average channel voltage is Vc = (Vs + Vd)/2 = Vs + Vds /2.
Gate and channel voltage Vgc is Vg – Vc = Vgs – Vds /2,

If the gate has length L and width W and the oxide thickness is tox, as shown in Figure , Then the
capacitance Cg is
𝑊𝐿
Cg= Kox ɛo
𝑡𝑜𝑥

𝑊𝐿
= ɛox
𝑡𝑜𝑥
Cg=CoxWL (2)

Where,

ɛo is the permittivity of free space, 8.85 × 10-14 F/cm,

Permittivity of SiO2 is kox = 3.9 times as great.

The ɛox/tox term is called as Cox. Capacitance (Cox) is a per unit area of the gate oxide.

Average velocity (v) of carrier is proportional to the lateral electric field (field between source
and drain). The constant of proportionality µ is called the mobility.

v = µE (2)

The electric field E is the voltage difference between drain and source (Vds) divided by the
channel length (L).
 𝑉𝑑𝑠
E= (3)
𝐿

The time required for carriers to cross the channel is L divided by v.The current between source
and drain is the total amount of charge in the channel divided by the time required to cross.

(4)

• Equation (4) is called linear or resistive, because when Vds << VGT, Ids increases linearly
with Vds, like an ideal resistor.
• k’ is the k prime, k’ = µCox.
• If Vds > Vdsat = VGT, the channel is no longer inverted in the drain region. Channel is
pinched off.
• Beyond this point (called the drain saturation voltage), increasing the drain voltage has no
further effect on current.
• Substituting Vds = Vdsat in Eq (4), we can find an expression for the saturation current
(Ids) that is independent of Vds.
𝛽
Ids= V2 GT (5)
2

This expression is valid for Vgs > Vt and Vds > Vdsat .

Summarizes the current in the three regions:

 3. NON IDEAL I-V EFFECTS:

MOS characteristics degrade with temperature. It is useful to have a qualitative understanding of

non ideal effects to predict their impact on circuit behavior.

Mobility Degradation and Velocity Saturation:

• Current is proportional to the lateral electric field Elat = Vds /L between source and drain.
• A high voltage at the gate of the transistor attracts the carriers to the edge of the channel,
causing carriers collision with the oxide interface that slows the carriers. This is called
mobility degradation.
• Carriers approach a maximum velocity (vsat) when high fields are applied. This
phenomenon is called velocity saturation.

Channel Length Modulation:

• Current Ids is an independent of Vds for a transistor in saturation.

• The p–n junction between the drain and body forms a depletion region with a width Ld
that increases with Vdb , as shown in Figure.
• The depletion region effectively shortens the channel length to Leff = L – Ld
• To avoid the body voltage into calculations, assume the source voltage is close to the
body voltage i.e Vdb = Vds.
• Hence, increasing Vds decreases the effective channel length.
• Shorter channel length results in higher current. Thus, Ids increases with Vds in
saturation, as shown in Figure .
In Saturation region, Ids is,
𝛽 𝑉𝑑𝑠
Ids= V2 GT (1+ )
2 𝑉𝐴

Hence, VA is proportional to channel length. This channel length modulation model is a gross
oversimplification of nonlinear behavior.

Threshold Voltage (Vt) Effects:

Threshold voltage Vt increases with the source voltage, decreases with the body voltage,
decreases with the drain voltage and increases with channel length.

Body Effect:

• When a voltage Vsb is applied between the source and body, it increases the amount of
charge required to invert the channel. Hence, it increases the threshold voltage.
• The threshold voltage can be modeled as

Where,

Vt0 is the threshold voltage when the source is at the body potential,
Фs is the surface potential at threshold and γ is the body effect coefficient.
Leakage:

• Even when transistors are OFF, transistors leak small amounts of current.
• Leakage mechanisms include sub threshold conduction between source and drain,
gate leakage from the gate to body and junction leakage from source to body and
drain to body.
• Sub threshold conduction is caused by thermal emission of carriers over the
potential barrier set by the threshold.
• Gate leakage is a quantum-mechanical effect caused by tunneling through the
extremely thin gate dielectric.
• Junction leakage is caused by current through the p-n junction between the
source/drain diffusions and the body.
4. CMOS device:

The four main CMOS technologies are

• n-Well process
• p-Well process
• Twin-tub Process
• Silicon on Insulator

(1) n-well process (n-tub process):

1. p-substrate (lightly doped) is taken initially. It is shown in Fig.1.17(a) then layer of

SiO2 is deposited above wafer.

2. n-well is created in p-substrate. That's why, this process is named as n-well process. It
is shown in Fig. 1.17(b). This n-well is formed by Ion Implantation and Diffusion. Depth of this
n-well depend upon level of diffusion. Shallow well is necessary for closely spaced structure.

3. Active mask is placed above substrate, it defines places for gate, source, drain
implantation. It is shown in Fig.1.17(c), thin layer of SiO2 is deposited above substrate. It is used
as masking layer.
 4. Now, n-well is protected with resist material. Because, it should not be affected by
Boron implantation. Then Boron is implanted in area except n-well. It is done using photoresist
mask. This type of implantation is known as channel-stop implantation. It is shown in
Fig.1.17(d).
 5. Then, thick oxide layer is deposited above p-substrate. So, conduction between
unrelated transistor source and drains will be avoided. It is shown in Fig.1.17(e). This oxide
construction is known as LOCOS (LOCal Oxidation of Silicon). The figure shown in Fig1.17(e)
due to LOCOS is known as bird's beak. To reduce the bird's beak effect, the technique which is
known as SWAMI (Side WAll MAsked Isolation) is employed.

6. In this n-well process, normally doped n+ is used as polysilicon gate. VT (Threshold

voltage) of n-devices is approximately 0.5 to 0.7 volts. Now, substrate is coated with polysilicon
layer. Then by using photo-etching process, the required pattern is generated. Each polysilicon
leads to self-aligned source and drain structure. It is shown in Fig.1.17(f).

7. The next process is occurrence of n+ diffusion. First n-well is protected. Then, in the
remaining portion of n-substrate, n+ diffusion occur. The region beneath the polysilicon will not
be affected by n+ diffusion. Now, source and drain are formed. It is shown in Fig.1.17(g).
8. The next process is implantation of n-. It is used to avoid the hot electron effect. The
fig.1.17(h) shows the implantation of n- using LDD(Lightly Doped Drain Structure). The effect
of heavy implantation is shown in Fig.1.17(i).

9. The next process is shifted to n-well. In n-well, p+ diffusion occur. Here, LDD is not
necessary, because hot carrier effect is less in p-transistor. The region beneath the portion of
polysilicon is not affected. It is shown in 1.17(j).

10. The next process is metallization. Metal one is shown in Fig.1.17(k) and metal contacts are
created.
(2) p-well process (p-tub process):

The p-well process starts with a n type substrate. The n type substrate can be used to implement
the pMOS transistor, but to implement the nMOS transistor we need to provide a p- well, hence
we have provided he place for both n and pMOS transistor on the same n-type substrate.

Mask sequence. Mask 1:

Mask 1 defines the areas in which the deep p-well diffusion takes place.
Mask 2:

It defines the thin oxide region (where the thick oxide is to be removed or stripped and thin oxide
grown)

Mask 3:

It‘s used to pattern the polysilicon layer which is deposited after thin oxide.

Mask 4:

A p+ mask (added with mask 2) to define areas where p-diffusion is to take place.

Mask 5:

We are using the –ve form of mask 4 (p+ mask) It defines where n-diffusion is to take place.

Mask 6:

Contact cuts are defined using this mask.

Mask 7:

The metal layer pattern is defined by this mask.

Mask 8:

An overall passivation (over glass) is now applied and it also defines openings for accessing
pads.

The cross section below shows the CMOS pwell inverter.

(3) Twin-tub process:

In, Twin tub process, two tubs are used (tub means well). So this process is known as twin tub
process.Threshold voltage, body effect of n and p devices are independently optimized by using
twin-tub process.

Steps involved in twin-tub process:

Step 1:

n+ substrate is taken initially, which is shown in Fig.1.19(a).

Step 2:

Next step is epitaxial layer deposition. Lightly doped epitaxial layer is deposited above n+
substrate. Electrical properties of layer is fixed by dopant and its concentration. It is shown in
Fig.1.19(b). The aim of this step is to deposit high-purity silicon layer. Concentration of dopant
distributed throughout the layer.

Step 3:

The next step is tub formation. Two wells are formed namely n-well and p-well. Polysilicon
layer is formed above the overall substrate.

Step 4:

Polysilicon gates are formed for n-well and p-well by using photo-etching process.
Step 5:

n+ diffusion is formed in n-well, p+ diffusion is formed in p-well. These are used for VDD
contact and Vss contact. These are known as substrate formation. It is shown in Fig.1.19(c).

Step 6:

Then, contact cuts are defined as in n-well process. Then, metallization is processed.

Advantages of Twin Tub Method:

• Separate optimized wells are available.

• Balanced performance of n and p-transistor is obtained. This is the speciality of this

Method.

(4) Silicon On Insulator (SOI) Process:

The steps involved in SOI process are given below.

Step 1:

Sapphire or SiO2 is used as the insulator. It is shown in Fig.1.20(a).

Step 2:

Thin film of lightly doped n-type Si is grown over an insulator. It is shown in Fig. 1.20(b). Then
photoresist material is deposited.

Step 3:

The next step is creation of n-island (Fig. 1.20c)). It is done by anisotropic etch.

Step 4:

One island is masked (n-island). Then p-island is formed by boron implantation. (Fig.1.20(d)).
Step 5:

p-islands are protected with photoresist. Then phosphorous is implanted in island which is not
protected. (Fig.1.20(e)).

Step 6:

Thin oxide is deposited over entire structure by using thermal oxidation process. Then
polysilicon layer is deposited above thin oxide (Fig.1.20(f)) and (Fig 1.20(g)).

Step 7:

Then by masking and etching process, polysilicon gate is formed. It is shown in (Fig 1.20(h)).
Step 8:

In p-island, n-doped source and drain are formed by phosphorous implantation. It is shown in
(Fig.1.20(i)).

Step 9:

After that, p-island is masked then in n-island, Boron implantation occur. (Fig.1.20(j)(i)) and (ii).

Step 10:

SiO2 layer is formed over entire structure. (Fig.1.20(k)).

Step 11:

Contact cuts are defined by etching SiO2 layer. Aluminium flows through cuts to create contact
with diffusion.

Step 12:

Final passivation layer of phosphorous glass used to eliminate leakage. current.(Fig. 1.20(l)).

Etching Process in SOI:

Various Etching process used in SOI process are given below.

1. Isotropic etching process

2. Anisotropic etching process

3. Preferential etching process

1. Isotropic etching process :

In Isotropic etching process, the condition a = b should be satisfied. It is shown in Fig.1.21.

2. Fully Anisotropic etching process:

In this process, b = 0 is the condition to be satisfied. This process is used in SOI process.

3. Preferential etching process:

In this process, tapered etching is done.

Advantages of SOI:

• There is no well formation in this process.

• There is no field-inversion problem.

• There is no latch up problem.

• There is no body-effect problem.

• There is no enhanced radiation tolerance.

Disadvantages:

• It is very difficult to protect inputs.

• Device gain is low.

• The coupling capacitance (Cc) between wires always exist.

5. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions:

DC TRANSFER CHARACTERISTICS:

The DC transfer characteristics of a circuit relate the output voltage to the input voltage.

(i) Static CMOS inverter DC Characteristics:

The DC transfer function (Vout Vs. Vin) for the static CMOS inverter shown in Figure.

A Static CMOS inverter

• Table 2, shows various regions of operation for the n and p transistors.

• In this table, Vtn is the threshold voltage of the n-channel device, and Vtp is
the thresholdvoltage of the p-channel device. Vtp is negative.
• The equations are given both in terms of Vgs /Vds and Vin /Vout.
• As the source of the nMOS transistor is grounded, Vgsn = Vin and Vdsn = Vout.
• As the source of the pMOS transistor is tied to VDD, Vgsp = Vin – VDD and
Vdsp = Vout – VDD.

Table 2: Relationships between voltages for the three regions of operation of a CMOS
inverter
 • Figure 12(a), shows Idsn and Idsp in terms of Vdsn and Vdsp for various values of Vgsn and
Vgsp.
• Figure 12(b), shows the same plot of Idsn and |Idsp| in terms of Vout for various values of
Vin.
• Operating points are plotted on Vout vs. Vin axes in Figure 12(c) to show the inverter DC
transfer characteristics.
• The supply current IDD = Idsn = |Idsp| is plotted against Vin in Figure 13(d) showing that
both transistors are momentarily ON as Vin.
• The operation of the CMOS inverter can be divided into five regions as indicated on
figure 12(c).

CMOS inverter DC characteristic

The state of each transistor in each region is shown in Table 3.

 • In region A, the nMOS transistor is OFF and the pMOS transistor pulls the output to
VDD.
• In region B, the nMOS transistor starts to turn ON. It is pulling the output down.
• In region C, both transistors are in saturation.
• In region D, the pMOS transistor is partially ON.
• In region E, PMOS is completely OFF, making the nMOS transistor to pull the output
down to GND.

(ii) Beta ratio Effects:

• For βp = βn, the inverter threshold voltage Vinv is VDD/2.

• It allows a capacitive load to charge and discharge in equal times by providing equal
current source and equal sink capabilities.
• Inverter with different beta ratios r = βp /βn is called skewed inverter.
• If r > 1, the inverter is HI-skewed. If r < 1, the inverter is LO-skewed. If r = 1, the
inverter has normal skew or is unskewed.
• Figure, shows the impact of skewing the beta ratio on the DC transfer characteristics.
• As the beta ratio is changed, the switching threshold is varied.

Fig:Transfer characteristics of skewed inverters

(iii) Noise Margins:

• Noise margin (Noise immunity) is related to the DC voltage characteristics.

• Noise Margin allows determining the allowable noise voltage on the input of a
gate, so that the output will not be corrupted.
• Two parameters of the noise margin are LOW noise margin (NML), and the
HIGH noise margin (NMH).
 •NML is defined as the difference in maximum LOW input voltage VIL and the
maximum LOW output voltage VOL. NML = VIL - VOL
•The value of NMH is the difference between the minimum HIGH output voltage
VOH and the minimum HIGH input voltage VIH. i.e., NMH = VOH - VIH
•Inputs between VIL and VIH are said to be in the indeterminate region or
forbidden zone.

(iv)Pass Transistor DC Characteristics:

• The nMOS transistors pass 0’s well but 1’s poorly. Figure, shows an nMOS transistor
with the gate and drain tie to VDD.
• Initially at Vs = 0. Vgs > Vtn, so the transistor is ON and current flow.
• Therefore, nMOS transistors attempting to pass a 1 never pull the source above VDD –
Vtn. This loss is called a threshold drop.
• The pMOS transistors pass 1’s well but 0’s poorly.
• If the pMOS source drops below |Vtp|, the transistor cuts off.
• Hence, pMOS transistors only pull down to a threshold above GND, as shown in Figure.

Fig:Pass Transistor threshold drops

6.Technology Scaling:

• In VLSI design, the transistor size has reduced by 30% every two to three years.
Scaling is reducing feature size of transistor.
• Nowadays, transistors become smaller, switch faster, dissipate less power and
cheaper.
• Designers need to predict the effect of feature size scaling on chip performance to
plan future products and ensure existing products for cost reduction.

Transistor scaling:

• Dennard’s Scaling Law predicts that the basic operational characteristics of a MOS
transistor can be preserved and the performance can be improved.
• Parameters of a device are scaled by a dimensionless factor S.

These parameters include the following:

• All dimensions (in the x, y, and z directions)

• Device voltages

• Doping concentration densities

Constant field scaling (Full Scaling):

• In constant field scaling, electric fields remain the same as both voltage and distance
shrink.
• 1/S scaling is applied to all dimensions, device voltages and concentration densities.
• Ids per transistor are scaled by 1/S.
• No. of transistors per unit area is scaled by S2.
• Current density is scaled by S and power density remains constant.
1 1
Ex: ( * )*𝑆 2
𝑆 𝑆

Lateral scaling (gate-shrink):

• Another approach is lateral scaling, in which only the gate length is scaled.
• This is commonly called as gate shrink, because it can be done easily to an existing
mask database for a design.
• Ids per transistor are scaled by S.
• No. of transistors per unit area is scaled by S.
• Current density is scaled by S2 and power density is scaled by S2.
• The industry generally scales process generations with 30% shrink.
• It reduces the cost (area) of a transistor by a factor of two.
 • A 5% gate shrink (S = 1.05) is commonly applied as a process, becomes mature to
boost the speed of components in that process.
• Constant voltage scaling: V DD is held constant, while process is scaled.
• Constant voltage scaling (Fixed scaling) offers quadratic delay improvement as well
as cost reduction.
• It is also maintaining continuity in I/O voltage standards. Constant voltage scaling
increases the electric fields in devices.
• Ids per transistor are scaled by S.
• No. of transistors per unit area is scaled by S2.
• Current density is scaled by S3 and power density is scaled by S3.
• A 30% shrink with Dennard scaling improves clock frequency by 40% and cuts
power consumption per gate by a factor of 2.
• Maintaining a constant field has the further benefit, that many nonlinear factors and
wear out mechanisms are unaffected.
• From 90nm generation technology, voltage scaling is dramatically slowed down due
to leakage. This may ultimately limit CMOS scaling.

Interconnecting Scaling:

• Wires to be scaled equally in width and thickness to maintain an aspect ratio close to
2.
• Wires can be classified as local, semiglobal and global.
• Local wires run within functional units and use the bottom layers of metal.
• Semiglobal wires run across larger blocks or cores, typically using middle layers of
metal.
• Both local and semiglobal wires are scaling with feature size.
• Global wires run across the entire chip using upper levels of metal.
• Global wires do not scale with feature size. Indeed, they may get longer (by a factor
of DC, on the order of 1.1) because, die size has been gradually increasing.
• When wire thickness is scaled, the capacitance per unit length remains constant.
7. Power consumption:

Reduction of power consumption makes a device more reliable. The need for devices that
consume a minimum amount of power was a major driving force behind the development of
CMOS technologies. As a result, CMOS devices are best known for low power consumption.
However, for minimizing the power requirements of a board or a system, simply knowing
that CMOS devices may use less power than equivalent devices from other technologies does
not help much. It is important to know not only how to calculate power consumption, but
also to understand how factors such as input voltage level, input rise time, power-dissipation
capacitance, and output loading affect the power consumption of a device.

The main topics discussed are:

• Power-consumption components

• Static power consumption

• Dynamic power consumption

Power-Consumption Components:

High frequencies impose a strict limit on power consumption in computer systems as a

whole. Therefore, power consumption of each device on the board should be minimized.
Power calculations determine power-supply sizing, current requirements, cooling/heatsink
requirements, and criteria for device selection. Power calculations also can determine the
maximum reliable operating frequency.

Two components determine the power consumption in a CMOS circuit:

• Static power consumption

• Dynamic power consumption

❖ CMOS devices have very low static power consumption, which is the result of
leakage current.
❖ This power consumption occurs when all inputs are held at some valid logic level and
the circuit is not in charging states.
❖ But, when switching at a high frequency, dynamic power consumption can contribute
significantly to overall power consumption.
❖ Charging and discharging a capacitive output load further increases this dynamic
power consumption. This application report addresses power consumption in CMOS
logic families (5 V and 3.3 V) and describes the methods for evaluating both static
and dynamic power consumption.
 ❖ Additional information is also presented to help explain the causes of power
consumption, and present possible solutions to minimize power consumption in a
CMOS system.
❖ Static Power Consumption Typically, all low-voltage devices have a CMOS inverter
in the input and output stage. Therefore, for a clear understanding of static power
consumption, refer to the CMOS inverter modes shown in Figure

Figure: CMOS Inverter modes

• As shown in above Figure, if the input is at logic 0, the n-MOS device is OFF, and the p-
MOS device is ON (Case 1).

• The output voltage is VCC, or logic 1. Similarly, when the input is at logic 1, the
associated n- MOS device is biased ON and the p-MOS device is OFF.

• The output voltage is GND, or logic 0. Note that one of the transistors is always OFF
when the gate is in either of these logic states.

• Since no current flows into the gate terminal, and there is no dc current path from VCC to
GND, the resultant quiescent (steady-state) current is zero, hence, static power consumption (Pq)
is zero.

• However, there is a small amount of static power consumption due to reverse-bias

leakage between diffused regions and the substrate.

The leakage current (Ilkg) of the diode is described by the following equation:

Ilkg = is (eqv/kt - 1)……….(1)

Where:

Is= reverse saturation current

V = diode voltage
k = Boltzmann’s constant (1.38 × 10–23 J/K) q = electronic charge (1.602 × 10–19 C)

T = temperature

Static power consumption:

Static power consumption is the product of the device leakage current and the supply voltage.
Total static power consumption, PS, can be obtained as shown in equation 2.

Ps = Σ (leakage current) x (supply voltage)……..(2)

Most CMOS data sheets specify an ICC maximum in the 10-µA to 40-µA range, encompassing
total leakage current and other circuit features that may require some static current not
considered in the simple inverter model.

The leakage current ICC (current into a device), along with the supply voltage, causes static
power consumption in the CMOS devices.

This static power consumption is defined as quiescent, or Ps, and can be calculated by equation 3.
Ps = Vcc x Icc ……… (3)

Where:

Vcc = supply voltage

Icc = current into a device (sum of leakage currents as in equation 2)

Another source of static current is ∆Icc. This results when the input levels are not driven all the
way to the rail, causing the input transistors to not switch off completely.

Dynamic Power Consumption:

The dynamic power consumption of a CMOS IC is calculated by adding the transient power
consumption (PT), and capacitive-load power consumption (PL).

❖ Transient Power Consumption Transient power consumption is due to the current that
flows only when the transistors of the devices are switching from one logic state to
another.
❖ This is a result of the current required to charge the internal nodes (switching current)
plus the through current (current that flows from VCC to GND when the p-channel
transistor and n- channel transistor turn on briefly at the same time during the logic
transition).
❖ The frequency at which the device is switching, plus the rise and fall times of the input
signal, as well as the internal nodes of the device, have a direct effect on the duration of
the current spike.
 ❖ For fast input transition rates, the through current of the gate is negligible compared to
the switching current. For this reason, the dynamic supply current is governed by the
internal capacitance of the IC and the charge and discharge current of the load
capacitance.

Transient power consumption can be calculated using equation 4.

PT = Cpd x Vcc2 x fI x NSW………….(4)

Where:

PT = transient power consumption VCC = supply voltage

FI = input signal frequency

NSW = number of bits switching

Cpd = dynamic power-dissipation capacitance

In the case of single-bit switching, NSW in equation 4 is 1.

Dynamic supply current is dominant in CMOS circuits because most of the power is consumed
in moving charges in the parasitic capacitor in the CMOS gates.

As a result, the simplified model of a CMOS circuit consisting of several gates can be viewed as
one large capacitor that is charged and discharged between the power-supply rails.

Therefore, the power–dissipation capacitance (Cpd) is often specified as a measure of this

equivalent capacitance and is used to approximate the dynamic power consumption.

Cpd is defined as the internal equivalent capacitance of a device calculated by measuring

operating current without load capacitance.

Depending on the output switching capability, Cpd can be measured with no output switching
(output disabled) or with any of the outputs switching (output enabled).

Capacitive-Load Power Consumption:

Additional power is consumed in charging external load capacitance and is dependent on

switching frequency.The following equation can be used to calculate this power if all outputs
have the same load and are switching at the same output frequency.

PL = CL x Vcc2 x fO x NSW (CL is the load per output)……….. (5)

Where:

PL= capacitive-load power consumption VCC = supply voltage

FO = output signal frequency

CL = external (load) capacitance

NSW = total number of outputs switching

In the case of different loads and different output frequencies at all outputs, equation 6 is used to
calculate capacitive-load power consumption.

PL= Σ (CLn x fOn) x Vcc2………(6)

Where:

Σ = sum of n different frequencies and loads at n different outputs

FOn = all different output frequencies at each output, numbered 1 through n (Hz)

Vcc = supply voltage (V)

CLn = all different load capacitances at each output, numbered 1 through n.

Therefore, dynamic power consumption (PD) is the sum of these two power consumptions and
can be expressed as shown in equation 7, equation 8 (single-bit switching), and equation 9
(multiple-bit switching with variable load and variable output frequencies).

PD= PT + PL……….(7)

PD = (Cpd x fI x Vcc2 ) + (CL x fO x Vcc2 )………..(8)

PD = [(Cpd x fI x NSW) + Σ (CLn x fOn)] x Vcc2………(9)

Where:

Cpd = power-consumption capacitance (F)

fI = input frequency (Hz)

FOn = all different output frequencies at each output, numbered 1 through n (Hz)

NSW = total number of outputs switching

Vcc = supply voltage (V)

CLn = all different load capacitances at each output, numbered 1 through n.

Total power consumption is the sum of static and dynamic power consumption.

Ptot = P(static) + P(dynamic)………(10)

 UNIT II - COMBINATIONAL LOGIC CIRCUITS

Propagation delays, Stick diagram, Layout diagrams, Examples of combinational logic

design, Elmore’s constant, Static logic gates, Dynamic logic gates, Pass transistor logic,
Power Dissipation, Low power design principles.

I.Propagation delays:

1.Delay Estimation:

In most designs, there exist many logic paths called critical paths. These paths are recognized
by a timing analyzer or circuit simulator. Critical paths are affected by the following four
levels.

i.Architectural Level.

ii. Logic Level.

iii. Circuit Level.

iv. Layout Level.

Architectural Level- This requires board level knowledge of both algorithms and the
technology being implemented. Also, the number of pipeline stages, the number of execution
units and size of memories are required.

Logic Level - This include types of functional blocks, the number of stages of gates in the
cycle, and fan-in and fan-out of the gates.

Circuit Level - This includes the tuning of delay by choosing transistor sizes.

Layout Level - Delay is dependent on the layout. Also, the floor plan determines the wire
lengths that can dominate delay.

To design critical path, quick delay estimation is required. Delay is estimated by the use of
RC delay model. Few terms involved in delay estimation are:

Rise time (tr) - The time required for a waveform to rise from 20 % to 80% of its steady-
state value.

Fall time (tf) - The time required for a waveform to fall from 80% to 20% of its steady-state

value.

Edge rate (trf)=(tr+tf)/2

Propagation delay time (tpd) or max-time - The maximum time from the input crossing

50% to the output crossing 50%.

Contamination delay time (tcd) or min-time - The minimum time from the input crossing
50% to the output crossing 50 %.

Driver - The gate that charges or discharges a node.

Load - The gates and wires being driven.

The delay can be estimated by the following ways;

i. RC Delay Models.

ii. Linear Delay Models.

iii. Logic Efforts.

iv. Parasitic Delay.

i. RC Delay Models:

The delay of logic gate is computed as the product of RC, where R is the effective driver
resistance and C the load capacitance. Logic gates use minimum-length devices for least
delay, area, and power consumption. The delay of a logic gate depends on the transistor
width in the gate and the capacitance of the load.

Effective Resistance and Capacitance:

An nMOS transistor with width of one unit has effective resistance R. A PMOS transistor
with width of one unit has effective resistance 2R. Wider transistors have lower resistance. If
multiple transistors are in series, their effective resistance is the sum of each individual
resistance. If multiple transistors are in parallel, their effective resistance is equal to the
resistance of the single transistor, which is in ON condition.Capacitance consists of gate
capacitance (Cg) and source/diffusion capacitance (Cdiff). In most processes, Cg, is equal to
Cdiff. Cg, and Cdiff are proportional to transistor width.

Diffusion Capacitance Layout Effects:

To reduce the diffusion capacitance in the layout, diffusion nodes are shared. Uncontacted
diffusion nodes between series transistors are smaller than the contacted nodes. Uncontacted
nodes have less capacitance. Diffusion capacitance depends on the layout.
Elmore Delay Model:

Elmore delay model estimates the delay of an RC ladder. This is equal to the sum over each
node in the ladder of the resistance between the node and a supply multiplied by the
capacitance on the node.

ii. Linear Delay Model:

The propagation delay of a gate is

d =f+p where,

f= effort delay or state effort, which depends on the complexity and fan out of the gate

p = parasitic delay, inherent to the gate when no load is attached

Again, f=gh . g = logical effort,h = fan out or electrical effort= Co/Cin

where, Co= Capacitance of the external load being driven, Cin = Input capacitance of the gate

iii. Logic Efforts:

Logical effort is defined as the ratio of the input capacitance of the gate to the input
capacitance of an inverter that deliver the same output current. Figure 1.55 shows an inverter,
NAND and NOR gates with transistor widths chosen to achieve unit resistance, assuming
pMOS transistors have twice the resistance of nMOS transistors.

The inverter has 3 units of input capacitance. NAND has 4 units of capacitance on each
input, so logical effort is 4/3. NOR has 5 units of capacitance on each input, and so logical
effort is 5/3. NAND gates are better than NOR gates because the series transistors are nMOS
rather than pMOS. Table 1.13 lists the logical effort of common gates.
iv. Parasitic Delay:

Parasitic delay is defined as the delay of the gate when it drives zero load. This can be
estimated with RC delay models. The inverter has 3 units of diffusion capacitance on the
output. So, the parasitic delay is 3RC=τ. So the normalized parasitic delay (Pin) is 1. Pinv is
defined as the ratio of diffusion capacitance to gate capacitance. NAND and NOR have 6
units of diffusion capacitance on the output, so the parasitic delay is twice (2Pinv or 2). Table
1.14 lists the parasitic delay of common gates.

2. Logical Effort and Transistor Sizing:

Logical effort provides a simple method to choose the best topology and number of stages of
logic for a function. This quickly estimates the minimum possible delay for the given
topology and to choose gate sizes that achieve this delay.
II. Layout diagrams and Stick diagram:

Layout diagrams:

Figure 1.63(a) shows the layout for an inverter. The input for the inverter A is connected
from the top, bottom, or left in polysilicon. The output for the inverter Y is obtained at the
right side of the cell in metal. The p-substrate and n-well is tied to ground and V,
respectively. Figure 1.63(b) shows the layout of the inverter with well and substrate taps
placed under the V and ground rails respectively.

Figure 1.64 shows the layout for a 3-input NAND gate. In this the nMOS are connected in
series and the PMOS are connected in parallel. The gate connections are made from the top
or bottom in polysilicon.

Disadvantage:

i. Layout is time consuming.

Stick Diagrams:

Stick diagrams are easy to draw because they do not need to be drawn to scale. Figure 1.65
(a) and (b) shows the stick diagrams for an inverter and 3-input NAND gate respectively.
From the stick diagram the area of layout can be easily estimated.

III. Elmore’s constant:

Figure 2.19 shows an RC circuit with a fan-out of two. Let the initial voltage at each node be
VDD assuming it to be 1 volt. At time, t =0 sec, the node 0 is connected to ground, so V0 = 0
volt. We need to find the voltages from V1, to V4, as a function of time. Elmore obtained
some delay in voltage reduction from V1, to V4, as shown in figure 2.20. The current in
branch k of the network is given by,
The node voltages have different values at each point in time. But the waveforms are similar,
so assume the slopes of the waveforms are related to each other. Now the slope of node
voltage V4 be a constant ak, times the slope of Vi, then,
IV. Pass Transistor Logic:

Pass transistor logic is used to reduce the number of transistors needed to implement logic by
primary inputs to drive the gate terminals as well as source-drain terminals. The logic is
widely used and is in contrast to logic families. The signal strength is measured by how
closely the value approximates an ideal voltage source. A stronger signal can source or sink
more current. Power supplies are the source of the strongest 1's and O's. This is represented
by VDD and GND.

An nMÓS transistor will act as a perfect switch when passing 0 and is imperfect when
passing a 1. That is, this passes a strong O and weak or degraded 1. Weak 1 represents a
voltage level less than VDD. Figure 2.21 shows the transistor symbols, and behaviors of pass
transistor strong and degraded outputs. A pass transistor is obtained when an nMOS or
PMOS is used as an imperfect switch.
V. Power Dissipation:

Static CMOS gates are very power-efficient and they dissipate nearly zero power while idle.
Some definitions related to power are given below.

Instantaneous Power (Pt) - Instantaneous power drawn from the power supply is
proportional to the supply currentiDD(t) and the supply voltage VDD.

P(t)=iDD(t)VDD

Energy (E) – The energy consumed over the time interval T is the integral of the
instantaneous power.

Average Power (Pavg) - The average power is given by

Static Dissipation:

Static dissipation occurs due to the following factors.

i. Sub-threshold condition through OFF transistors.

ii. Tunneling current through gate oxide.
iii. Leakage through reverse-biased diodes.
iv. Contention current in ratioed circuits.

Figure 2.75 shows a static CMOS inverter. If input is 0, then nMOS is OFF and pMOS is
ON, and the output is 1. If input is 1, then nMOS is ON and pMOS is OFF, and the output is
0. In both the cases, one of the transistors is OFF. Ideally, no current flows through the OFF
transistor. But sub-threshold condition, tunneling, and leakage lead to small amounts of static
current flow through the OFF transistor. The static power dissipation is the product of the
total leakage current (Iststic) and the supply voltage (VDD).

Figure 2.75 CMOS Inverter Model for Static Power Dissipation Evaluation

Dynamic Dissipation:

Dynamic dissipation occurs due to the following factors:

i. Charging and discharging of load capacitance.

ii. Short circuit current while both pMOS and nMOS networks are partially ON.

If we consider a load C, switched between GND and VDD at an average frequency of fsw over
a given interval of time T, then the load will charge and discharge Tfsw times. During
charging, current flows from VDD to the load and while discharging, current flows from the
load to GND. In one complete charge/discharge cycle, the total charge Q = CV DD is
transferred from VDD to GND. The average power dissipation is
VI. Low power design principles:

Dynamic power dissipation is greater than static power dissipation when systems are active
For high-performance systems such as workstations and servers, dynamic power
consumption per chip is limited to 150 W. For battery-based systems such as laptops, cell
phones, and PDAs, power consumption sets the battery life of the product. Commonly used
metrics in low- power design are power, power-delay product and energy-delay product.
There are two power reduction techniques:

i. Dynamic Power Reduction.

ii. Static Power Reduction.

i.Dynamic Power Reduction:

Dynamic power can be reduced by decreasing the following factors:

i. Activity Factor.

ii. Switching Capacitance.

iii. Power Supply.

iv. Operating Frequency.

Activity Factor - Static logic has a low activity factor. Clocked nodes have an activity factor
of 1. Clock gating can be used to stop portions of the chip that are idle. Turn off the clock
network wherever possible. Sense the chip temperature and cut back activity, if the
temperature becomes too high. Due to activity factor reduction, spike may occur and this will
lead to inductive noise in the power supply.

Switching Capacitance - This is reduced by choosing small transistors. Small gates can be
used on non-critical paths. Buffer driving I/O pads and long wires use a stage effort of range
8-12 to reduce the buffer size. Interconnect switching capacitance can be reduced by proper
floor planning.

Power Supply - Choosing low power supply reduces power consumption. Voltage can be
adjusted on operating mode. A laptop processor operates at high voltage and high speed,
when plugged into an AC adapter.

Operating Frequency - In a digital signal processing system, two multipliers running at half
speed can be replaced by a single multiplier at full speed to reduce power consumption.
ii. Static Power Reduction:

This involves minimizing Istatic. Analog current sources and pseudo-nMOS gates are turned
off when they are not needed. In low-power battery operated devices, leakage specifications
may be given at 40° C rather than 110° C.

Sub-threshold leakage can be controlled through the body voltage using the body effect.
Reverse Body Bias (RBB) can be used during the idle mode to reduce leakage. Forward
Body Bias (FBB) can be used during the active mode to increase the performance. An
Adaptive Body Bias (ABB) can compensate and achieve more uniform transistor
performance. Too much reverse body bias leads to greater junction leakage through a
mechanism called band-to-band tunneling, while too much forward body bias leads to
substantial current through the body to source diodes.

Another method to reduce idle leakage current is to turn off the power supply entirely. This is
done externally with the voltage regulator or internally with a series transistor. Multiple
Threshold CMOS (MTCMOS) circuits use low-Vt, transistors for computation and a high-Vt,
transistor as a switch to disconnect the power supply during idle mode.

VII. Static logic gates:

i. Bubble Pushing:

By using De-Morgan's Rule, we can see the concept of bubble pushing.

The above p-MOS network is equivalent to the symbol given here. In the logical OR gate, 2
bubbles are pushed in the input side. This concept is known as bubble pushing. It is shown in
Fig.4.46.

Now, we can see the series network of p-MOS given in Fig.4.47.

ii. Compound Gates:

By using AND-OR-INVERT gate, various functions can be computed in a single

stage. For example, we can consider the function given below. It is implemented by

using AOI concept which is shown in Fig.

• Logical effort of compound gates is different for different inputs.

• Logical effort of each input is the ratio of the input capacitance of that input to the
input capacitance of the inverter.
• The parasitic delay is calculated from the total diffusions capacitance on the output
node by summing the sizes of the transistors attached to the output.
• For example, we can see CMOS inverter logic diagram.
iii. Skewed Gates:

• If one input transition is more important than the other, then skewed gates are
used.
• HI-skew gates are used to rising output transition.
• LO-skew gates are used to falling output transition. It can be done by
decreasing the transistor size of the non-critical transistors.
HI-skew inverter is shown in Fig.4.51. It is formed by decreasing the size of
n-MOS.
Unskewed Inverter (equal rise resistance) is shown in Fig.4.52.

Unskewed Inverter (equal fall resistance) is shown in Fig.4.53

iv. P/N Ratios:

HI-Skew NAND Gate:
 𝑃
• ratio means ratio of pMOS to nMOS transistor width.
𝑁
𝑃
• ratio (of a library of cells) is to be chosen on the basis of area, power,
𝑁
reliability not average delay.

VIII. Dynamic logic gates:

i. Domino Logic:

• The monotonicity problem can be solved by connecting a static CMOS inverter

between the dynamic gates.
• It is used to convert monotonically falling output into a monotonically rising signal
suitable for the next gate.
• The dynamic static pair is known as domino gate. It is shown in Fig.4.60. HI-Skew gate
is used as static inverter.
 ii. Dual-Rail Domino Logic:

• It is a dynamic form of cascade voltage switch logic.

• It encodes each signal with a pair of wires. The input and output signal pairs are –
h and - 1. If the output is '1', then - h is asserted. If the output is '0', then - 1 is
• asserted.
• General logic diagram of dual-rail domino logic is shown in Fig.4.61.
• Now, we can see the implementation of AND and NAND gates by using dual-rail
domino logic. It is shown in Fig.4.62.

iii. Keepers:

• Leakage and noise margin problems are addressed by Keeper circuit.

• If a dynamic node is precharged high and left floating, then the voltage on the dynamic
node will drift over time due to gate, sub threshold junction leakages.
• Now, we can see the general keeper circuit. It is shown in Fig.4.63.
• If dynamic node N is high, y is low and keeper circuit is ON to prevent N from floating.
If N falls, the keeper circuit initially opposes the transition. So, it must be much weaker
than the pull down network.
• The keeper must be wide to compensate for any leakage current drawn when the output is
floating and pull down network is OFF. Noise margin can be improved by using strong
keepers.

• Long keeper transistors increase the capacitive load on the output. It can be avoided by
splitting the keeper.
iv. Multiple Output Domino Logic:
If one function is a subfunction of another subfunction, then multiple output domino logic
(MODL) is needed. It saves area by combining all the functions into a multiple output
gate.
v. NP Domino:

NP Domino logic is shown in Fig.4.68. NP Domino is also known as NORA Domino

(NORACE Domino). It is shown in Fig.4.69.
IX. Examples of combinational logic design:

The combinational logic circuits are designed based on some procedure as given as follows

• Create truth table from specification

• Generate K-maps & obtain logic equations
• Draw logic diagram (sharing common gates)
• Simulate circuit for design verification
• Circuit optimization for area and/or performance
• Re-simulate & verify optimized design

i. CMOS Two input NOR Gate:

The circuit consists of a parallel-connected n-net and a series-connected complementary p-net.

The input voltages VX and VY are applied to the gates of one nMOS and one pMOS transistor.

When either one or both inputs are high, i.e., when the n-net creates a conducting path between
the output node and the ground, the p-net is cut-off.

If both input voltages are low, i.e., the n-net is cut-off, then the p-net creates a conducting path
between the output node and the supply voltage.

For any given input combination, the complementary circuit structure is such that the out- put is
connected either to VDD or to ground via a low-resistance path and a DC current path between
the VDD and ground is not established for any input combinations.

The output voltage of the CMOS, two inputs NOR gate will get a logic-low voltage VOL=0 and a
logic-high voltage of VOH=VDD.
The figure shows a sample layout of CMOS 2-input NOR gate, using single-layer metal and
single-layer polysilicon. The features of this layout are:

• Single vertical polylines for each input

• Single active shapes for N and P devices, respectively
• Metal buses running horizontal

ii. CMOS Two-input NAND Gate:

The circuit diagram of the two input CMOS NAND gate is given in the figure below.

The principle of operation of the circuit is exact dual of the CMOS two input NOR operation.

The n-net consisting of two series connected nMOS transistor creates a conducting path between
the output node and the ground, if both input voltages are logic high.

Both of the parallelly connected pMOS transistor in p-net will be off.

For all other input combination, either one or both of the pMOS transistors will be turn ON,
while p - net is cut off, thus, creating a current path between the output node and the power
supply voltage.

The features of this layout are as follows:

• Single polysilicon lines for inputs run vertically across both N and P active regions.
• Single active shapes are used for building both nMOS devices and both pMOS devices.
• Power bussing is running horizontal across top and bottom of layout.
• Output wires runs horizontal for easy connection to neighboring circuit.