Raghavendra B S, PG student

02 August 2024 22:37

What is System verilog Assertions(SVA)?

• Assertions are used to check design rules or specifications and ensures certain design specifications covered in verification and generate warnings or errors in case of
assertion failures. The methodology that uses assertions is commonly known as “Assertion Based Verification” (ABV). Assertions can be written in the design as well
as the verification environment.
• Assertions are the declarative code which checks the relationships between signals in design either once or over a period of time.

▪ Practical consequences:
1. If a design requests for grant signal and expected to receive the acknowledgement signal within 4 cycles then assertion passes else fails.
2. If a invalied instruction fetched by the processor from the memory then also assertion failure may happen.
3. Deadlock condition in FSM or any illegal state transition in FSM can also be detected by assertion mechanism.

▪ Explain the system verilog scheduling regions?

while proceeding through each time step the simulator undergoes several intermediate stages dedicated to certain operations. Which is shown in the figure below

Scenario-1: (Data Transfer between two modules)

• Consider an example, Here DUT is driven by inputs from test module and response from DUT is captured by test module both modules are in sync with external clock
and both modules are instantiated at the top level module. Its complete code is shown in Fig-2.
• Problem: One always block at DUT, two initial blocks at test module gets triggered simultaneously by the same positive clock edge which creates race condition(because
of Non blocking assignment).
Solution-1: Using Non blocking assignment races are eliminated
Solution-2: The code for testing block is defined under program, endprogram instead of module, endmodule then this is executed in reactive stage of scheduling
region thus the scenario become predictable(Racefree).
• Program endprogram block is non synthesizable it cant supports always but it can support forever, initial, begin-end.
• Practically It takes some time delay for test module to originate the data and transfer across the channel upon receiving the clock edge, similar case is observed at the
DUT also (Fig.1)

Concept: If the procedural block has mixture of blocking and non blocking assignments, then order of execution is different in module endmodule and program
endprogram block.

7.Assertions Page 1
 Advantages of assertion?
• Assertions checks design intension and reports error/warning incase of assertion failure(0,X,Z) in less time( formal verification).
• Reusability across designs, testbench components, covergroups, properties, interfaces etc.. with parameterization.
• can be selectively turnon/off as per requirement.
• Assertions can be checked Dynamically(by simulation), or statically(Formal verification tool) Based on assertions furthur actions(debugging) can be taken in verification
environment.

Terminologies of Assertion:
assert: Specifying the property to be true in simulation.
assume: specifying the property as an assumption and used by formal tools to generate input stimulus.
cover: Evaluating the property during functional coverage.
restrict: It imposes the restrictions on formal verification computations.

What are Sequences in Assertion?

• complex behaviour spans over simulation time can be modelled by series of sequences.
• One clock cycle delay is specified using ## from end of the first sequence to begining of the second sequence. If clocking event is not specified within the sequence, th en
clocking will be inferred from the property where it is called.
• Sequences can be declared within interface, clocking, program, module blocks.

Types of Assertion
 Immediate Assertion(Permanent):
▪ It checks a condition at the point where we want to check the behaviour in the current simulation time, (like if else statement). In the below example, if the expression
evaluates true(Logic-1) then Pass statement gets executed, else(Logic0,X,Z) fail statement gets executed (if else not specified, then by default tool call $error).
▪ Both pass and fail statement in the below code are optional.
Syntax: <label>: assert(expression) <pass_statement> else <fail_statement>

Note:
▪ Labelling the assertion helps while debugging.
▪ both pass and fail statement in assertions are optional.

Example-0.a: write an immidiate assertion within a design to detect Example-0.b: write an assertion to ensure reset condition is met
that the input data must not be zero when reset pin is not high.
module my_testbench;
module my_module(input logic clk, reset, input logic [3:0] data); logic clk, reset;
always @(posedge clk or posedge reset) begin logic [3:0] data;
if (reset) begin // Instantiate DUT
// Reset logic my_module uut (.clk(clk), .reset(reset), .data(data));
end
else begin initial begin
// Assertion within the module // Test stimulus
assert (data != 4'b0000) else $error("Data must not be reset = 1;
data = 4'b1010;
zero!"); #10 reset = 0;
end
end // Assertion to verify that the reset condition was met
endmodule assert (reset == 0) else $error("Reset did not go low in time.");
end
endmodule

Example-1
module design(input clk,rq1,rq2);
time t;

always @(posedge clk)

if(state==req)
assert (rq1 || rq2) else $error("assertion failed %0t", $time);
else;
(Failure of Assertion results in certain severity levels)

endmodule

//Other varients
assert (myfunc(a,b)) count++; else begin
flag=1
#5 ->event;
end

endmodule
always @(state)
assert (state==$onehot) else $fatal;

7.Assertions Page 2
 Example-2(Immediate assertion in Design)
In the below example, Immediate assertion specified in the design which ensures that fifo is not full when push=1 then assertion passes else fails, ie the condition
specified within the assert statement evaluates true, then first block executed, else second one. The port connections to the Design is specified through the interface code Fig-2.

Example-3(Assertion for Rapid debugging)

 Concurrent Assertion(Temporal):

Example:1
• In the below example, two sequences are combined in a property p1.
• Property p1 is evaluated at the rising edge of the clock.
module tb();
bit a,clk;
bit c,d;

sequence s1;
a ##1 c; //If a=1 after delay of 1 cycle c=1 then s1 passes.
endsequence

sequence s2;
c ##2 !d ##3 $stable(a); //c=1, d=0(after 2 cycles delay), (after 3 cycle) "a" must not changed from last event to current event.
endsequence

property p1 //Multiple sequences are combined together to describe complex property.

@(posedge clk) (s1 ##2 s2) or (s2); //(Two cycles after s1 has happened s2 should happen) or (s2 should happen alone) then property passes.
endproperty

assert property(p1) else $fatal;

7.Assertions Page 3
 always #5 clk=~clk;

initial begin
repeat(4) begin
#3 a=$random;
$display("%0t,%0d",$time,a); //assertions evaluated in the preponed region display gets "a" value at that region.
end
#2 $finish();
end

endmodule

Note: clock may be menctioned either at property/sequence/ procedural block etc... It is mandatory to menction clock in concurrent assertion else the statement
becomes illegal.

Example:(Using Property Keyword): A property can be used for verification as an assumption, checker or coverage specification.
• can be declared within module, interface, clocking block, package etc.

• In the example given below two signals a and b are driven with some random values at every positive edge of the clock. The as sertion is executed at every pos-edge of the
clock and is expected to be true, It evaluates the value by sampling the variables at preponed region(Delta cycle before the clock edge).
• This code can also be modified for OR, XOR NOR operators.

Operation on Sequences:
• NOT Operation: Intersection Operator: Here the resulting sequence matches if both operand sequences must be of same length, both begins and
property p; ends at same instant.
Example:
@(posedge clk) disable iff(rq)
a|-> not(i1 ##1 i2); (a1 ##[1:4] a2) intersect (a3 ##1 a4 ##2 a5)
endproperty

AND(Conjunction) operation:

7.Assertions Page 4
AND(Conjunction) operation:
The AND operation between two sequences will match if
• Both sequences must start simultaneously but their end times may be different.
• The end time of the resultant or composite sequence is the end time of the operand that finishes last.
syntax: <seq1> and <seq2>

Example: Example:
(a1 ##1 a2) and (a3 ##1 a4 ##2 a5) (a1 ##[1:4] a2) and (a3 ##1 a4 ##2 a5)

Exercise:
property p;
@(posedge clk) a[*2]|-> ((##[1:3]b) and (c|=>d));
endproperty

OR operator: The OR operation between two sequences will match if

• Both operand sequences should start at the same time and either seq1 or seq2 matches.
• The end time of the resultant or composite sequence is the end time of the operand sequence that finishes last.

Example: Example:
(a1 ##1 a2) or (a3 ##1 a4 ##2 a5) (a1 ##[1:4] a2) or (a3 ##1 a4 ##2 a5)

Some additional Concepts:

Multiple Clock Sequences: These are built by concatenating single clocked sequences
with ##1 operator only*.
Note: Note: and, or, intersect operations are not allowed in MCS
• The clock for an assertion is determined in the decreasing order of priority as Example:
shown below. The sequence evaluateion starts at posedge clk1 and checks for a1=1, and checks for a2
1. Explicitly specified for the assertion. =1 at the subsequent posedge of clk2.
2. Inferred from the context of code when embedded. sequence s1;
3. Default clock, if specified. @(posedge clk1) a1 ##1 @(posedge clk2) a2;
endsequence
• Clocks need to be explicitly specified in multi-cloked assertions(no code can
infer clock).
Multiple Clock Properties: These are similar to multi clock sequences.
Note:and, or and not operators are not allowed in multi-clock properties.

The property shown below is said to be matched if b and c are true at next clock edges
of clk1 and clk2 after a matches on an edge of clk0.
property p1;
@(posedge clk1) b ##1 @(posedge clk2) c;
endsequence

assert property (@(posedge clk0) a |=> p1) else $error;

7.Assertions Page 5
 assert property (@(posedge clk0) a |=> p1) else $error;

Note:
1. The default or inferred clock is not allowed in multi clock assertion
2. The multi-clock property can not be used in procedural and clocking blocks.
3. It is mandatory to use an explicit clock in the multi -clock assertion.

Explain the system Task $rose(), $fell() and $stable() ?

• The system task $rose(a) is used check for a=1 at a given time along with a=0 at the previous clock edge. It samples the value at preponed region(a=0) and it assumes (a=1) at
next clock edge to guess clock edge has happened.
• $fell(a) detect negetive edge. $stable(a) detects the stable value at the clock positive edge as per code. $changed() return True if the signal has changed its value at the
evaluation point.

Some Technical Terms:

Consecutive Repetition Operator: Goto repetition operator: Let's assume we want to assert that a signal a should be high at least
This operator used in assertions to specify that certain condition must be 3 times, but it doesn't need to be in consecutive cycles.
true for consecutive number of clock cycles. (a must be true for 3
consecutive cycles after b goes a) property a3;
property a3; @(posedge clk) a[*3:$]; //a[*3:$] means 3 to infinite cycles
@(posedge clk) b ##1 a[*3]; //a[*3:6] means 3 to 6 cycles
endproperty endproperty

assert property (a3); assert property (a3);

Implication Operator:
Types: 1) Overlapping 2)Non Overlapping Example:
• In overlapping req |-> ack mean, if req is high in a given clock property a3; //Property starts getting evaluated at posedge of clk
cycle, ack must be high either in the same cycle or in a @(posedge clk) a ##[3:$] (c+d); //(c+d=True after 3,4,5…)clock cycles after a=1.
subsequent cycles(later cycles.) endproperty

property p1; assert property (a3);

@(posedge clk) req |-> ack;
endproperty
Practical example(Request Grant Protocol Spec):
assert property (p1); Create an assertion where req=1(at clock edge) followed by grant=1(2 cycle delay)
followed by de-assertion of request and grant.
• In Non-overlapping req |=> ack means that if req is high in a given property a3;
clock cycle, ack must be high in the next cycle or later cycle. @(posedge clk) req ##2 gnt ##1 !req ##!gnt;
endproperty
property p1;
@(posedge clk) req |=> ack; assert property (a3) else $error("Req-Gnt Protocol violation");
endproperty

assert property (p1);

Example:

7.Assertions Page 6
Example:
sequence seq;
@(posedge clk) req1 ##1 req2[*2:4];
endsequence
In this example, if req1 is true then after 1 clock cycle, req2 must be true for
a minimum of 2 and a maximum of 4 consecutive clock cycles.

Usage of ## operator: It is used to provide the delay of clock cycles.

Typical Examples: 3. In the below example if rising is detected for a the assertion gets active, and if
rising also detected for b in next 3 to 5 cycles assertion passes else fails.
1. assert property (@(posedge clk) disable iff(rst)(req|=>ack));
This assertion checks whether req is high on the rising edge of clk, and ack must go high
in next clock cycle. However, when rst is high the assertion is disabled and not checked,
This is usefull in scenarios like during reset or other conditions where the assertions should
not be evaluated.

2. In the below example, the property is checked at positive clock edge and can be
disabled aswell if dis=1, when rising is detected for a, after 3 clcok cycles if rising is
detected for b. Then assertion passes else fails.

4. At posedge of clk (mem_en and req =1) is checked and after 2 cycles ack must
be 1 then property passes else fails.
property p1;
@(posedge clk) mem_en |-> req ##2 ack;
endproperty : p1

5. At posedge of clk (mem_en) is checked, after next cycle req=1 is checked and
after 2 cycles ack=1 is checked.
Note: property p1;
1. (a ##1 b)[*1:3] is equivalent to @(posedge clk) mem_en |=> req ##2 ack;
a ##1 b or endproperty : p1
a ##1 b ##1 b or
a ##1 b ##1 b ##1 b.
2. b[=3] mean b must be true for 3 clock cycles but need not be consecutive.
3. b[=m:n] mean b must be true for minimum m and maximum n non
consecutive cycles.

7.Assertions Page 7
 Recursive Property: A property is said to be recursive if it instantiates
itself within it.
Example:
property pe(p);
p and (1'b1 |=> pe(p)); //pe is called within pe
endproperty

Restrictions on Recursive Properties:

• not operator is not allowed within recursive properties.
• disable iff cannot be used within recursive property.
• overlapping operator make the recursive property get struck at infinite
loop.

• if expressions in property:
It is possible to select multiple property expressions using if-else condition within a property.
Example: Checking for cache lookup hit/miss.

• Detecting the end point of the sequence:

It returns true if the menctioned sequence reaches to an end else it will return false.

sequence s1;
@(posedge clk) $rose(a) ##1 b;
endsequence

sequence s2 @(posedge clk)

c ##1 s1.ended; //This sequence passes if end point of s1 is detected one cycle after c goes high
endsequence

Note: Assertions can be 1) embeded within the design, 2) defined outside the module. assertions can be binded to a design module or interfaces(one/ more)

7.Assertions Page 8
Note: Always label assertions(shows label during failure, helps significantly in debugging).

Exercise: 4. Write an assertion for the given fifo specification

1. Create a sequence such that once req is asserted we must get • Once the reset is de-asserted, the readPointer and writePointer
ack before asserting req again. are 0 and the empty signal is high and full signal is low.
• FIFO full should never asserted, if count of entries is less than
property p1; max-entries and asserted if count reaches maximum
@(posedge clk) $rose(req) |=>( not(!ack[*0:$] ##1 $rose(req) )); //ack=
0 followed by req=1 shouldnot happen forever property reset_check;
endproperty @(posedge clk) !rst_n->( rptr==0 && wptr==0 && empty==1
&& full==0 && cnt==0);
l_p1: assert property(p1) else $error("failed"); endproperty

2. create an assertion to detect fifo_write and fifo_read rst_chk: assert property(reset_check) else $error("failed");
happening in same cycle (as the number of entries in fifo not property fifo_not_full;
changed). @(posedge clk) disable iff(!rst_n)
property s1 @(posedge clk) (cnt<32|->!full);
fifo_read&fifo_write |=> num_entries==$past(num_entries) endproperty
endsequence
fifo_not_full_chk: assert property(fifo_not_full) else
assert property(s1) else $error("error"); $error("failed");

property fifo_full_check;
3. Write an Immediate assertion to check read_en and write_en @(posedge clk) disable iff(!rst_n)
for an SRAM are mutually exclusive. (cnt==32|->full);
endproperty
assert property (@(posedge clk) disable iff(rst_n) not(read_en & write_en))
else $error("read, write together"); fifo_full_chk: assert property(fifo_full_check) else
$error("failed");

5. Create a property that checks that a signal is asserted for no more

than 2 consecutive cycles

assert property @(posedge clk) disable iff(rst_n)

not(sig ##[1:2] sig)
else $error("error");

Explain compiler directives/ Pre processor directives in SV?

These are used for conditional compilation or It can manupulate the source code just before the actual execution of source co de begins. Verilog supports few compiler
directives which direct the compiler to treat the code in a certain way.

Example-1(using `ifdef/`ifndef)
`ifdef/`ifndef simply tells the compiler to include or not include a piece of code till `else/`endif is encountered, In the below code if a macro, FLAG is defined then the
corresponding code gets executed else it looks for other block.This concept is used to selectively include some code in the s ource code. This method minimal datapath and
hardware.

In the below testbench, rstn is included in the compilation of the design only if macro INCLUDE_RSTN is defined in any verilo g file which is a part of the compilation list of
files or passed through the command line of the compiler.

7.Assertions Page 9
files or passed through the command line of the compiler.

Example-2(using `include directive)

It is used to include multiple files in a single source file.

7.Assertions Page 10