Direct Memory Access (DMA)
Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or
receive data directly to or from the main memory, bypassing the CPU to speed up memory
operations. The process is managed by a chip known as a DMA controller (DMAC).
Direct Memory Access (DMA) means CPU grants I/O module authority to read from or write to
memory without involvement. DMA module itself controls exchange of data between main
memory and the I/O device. CPU is only involved at the beginning and end of the transfer and
interrupted only after entire block has been transferred.
Slow devices like keyboards will generate an interrupt to the main CPU after each byte is
transferred. If a fast device such as a disk generated an interrupt for each byte, the operating
system would spend most of its time handling these interrupts. So a typical computer uses direct
memory access (DMA) hardware to reduce this overhead.
For example, a sound card may need to access data stored in the computer's RAM, but since it
can process the data itself, it may use DMA to bypass the CPU. Video cards that support DMA
can also access the system memory and process graphics without needing the CPU.
Direct Memory Access needs a special hardware called DMA controller (DMAC) that
manages the data transfers and arbitrates access to the system bus. The controllers are
programmed with source and destination pointers (where to read/write the data), counters to
track the number of transferred bytes, and settings, which includes I/O and memory types,
interrupts and states for the CPU cycles.
Working principle of DMA controller: DMA controller is used with the microprocessor.
Which helps to generate the addresses for the data to be transferred from the I/O devices.
First step, the peripheral device sends the request signal (DMARQ) to the DMA controller.
Second step, the DMA controller in turn passes it to the microprocessor (HOLD signal).
Third step, on receipt of the DMA request, the microprocessor sends an acknowledge signal
(HLDA) to the DMA controller.
Fourth step, on receipt of this signal (HLDA), the DMA controller sends a DMA acknowledge
signal (DMACK) to the I/O device.
Fifth step, the DMA controller then takes over the control of the buses of microprocessor. And
it take controls the data transfer between RAM and I/O device.
Sixth and Final Step, when the data transfer is completed, DMA controller returns the control
over the buses to the microprocessor by disabling the HOLD and DMACK signals.
The operating system uses the DMA hardware as follows −
Ste Description
p
1 Device driver is instructed to transfer disk data to a buffer address X.
2 Device driver then instruct disk controller to transfer data to buffer.
3 Disk controller starts DMA transfer.
4 Disk controller sends each byte to DMA controller.
5 DMA controller transfers bytes to buffer, increases the memory address, decreases the
counter C until C becomes zero.
6 When C becomes zero, DMA interrupts CPU to signal transfer completion.
Advantages of DMA Controller
● Reduced CPU Overhead: DMA transfers offload data movement tasks from the CPU,
allowing it to focus on executing other instructions concurrently. This reduces CPU
overhead and improves overall system performance.
● Faster Data Transfer Rates: DMA controllers can achieve higher data transfer rates
compared to CPU-managed transfers, as they operate independently of the CPU's
processing speed and can access memory and peripherals more efficiently.
● Efficient Resource Utilization: By allowing concurrent data transfers between
peripherals and memory, DMA controllers optimize resource utilization and enhance
system throughput.
● Improved Real-time Processing: DMA transfers can be prioritized to ensure timely
processing of time-critical data, making them suitable for real-time applications where
latency is crucial.
Disadvantages of DMA Controller
● Complexity: Implementing DMA functionality requires additional hardware components
and software support, increasing system complexity and development effort.
● Limited Flexibility: DMA controllers may have limitations in terms of supported
transfer modes, address ranges, and peripheral compatibility, which can restrict their
applicability in certain scenarios.
● Potential for Bus Contention: DMA transfers may compete with CPU and other DMA
transfers for access to the system bus, leading to potential bus contention and
performance degradation under heavy load conditions.
● Debugging Challenges: Troubleshooting DMA-related issues can be challenging due to
the asynchronous nature of DMA transfers and the limited visibility into the transfer
process compared to CPU-managed operations.
