Microprocessors programming
and Interfacing
CS/EEE/ECE/INSTR F241
Prof.Meetha V Shenoy/Prof. Vinay Chamola
BITS Pilani
Pilani Campus BIU & EU
BITS Pilani, Pilani Campus
8086 Buses
16-bit processor
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Block Diagram of 8086
BIU- Fetches instruction & Data
EU- Executes Instruction
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8086 Buses
20 bit memory address
16 bit registers
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Segment Registers
• Memory Organization
– Each byte in memory has a 20 bit address starting with 0 to 220-1 or 1M of
addressable memory
– Addresses are expressed as 5 hex digits from 00000 – FFFFF
– Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!
– Solution: Memory Segment
• Block of 64K (65,536) consecutive memory bytes
• Within a segment, a particular memory location is specified with an offset
• An offset also ranges from 0000 to FFFF
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Block Diagram of 8086
The instruction
pointer (IP) in an
8086 microprocessor
is a 16-bit register
that points to the
address of the next
instruction to be
fetched
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Intel
Memory address generation
• The BIU has a dedicated adder for determining physical memory addresses
Offset Value (16 bits) IP
Segment Register (16 bits) 0000
CS
Adder
Physical Address (20 Bits)
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Example (Accessing a location)
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Segments in 8086
• The code segment is a section of memory that holds the
code (programs and procedures) used by the
microprocessor. The code segment (CS) register defines the
starting address of the section of memory holding code.
• The data segment is a section of memory that contains most
data used by a program.
• The extra segment is an additional data segment that is used
by some of the string instructions to hold destination data.
• The stack segment defines the area of memory used for the
stack.
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Segmentation
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Block Diagram of 8086
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Examples
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8086 Registers
Block Diagram of 8086
8086 Microprocessor
Architecture
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have BIU fetches instructions, reads data
already been fetched by the BIU. from memory and I/O devices,
writes data to memory and I/ O
devices.
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Dedicated Adder to generate
20 bit address
Four 16-bit segment
registers
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >> 17
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Facilitates
Segment Relocation
Registers
8086’s 1-megabyte The 8086 can directly Programs obtain access
memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Segment
Registers Code Segment Register
16-bit
CS contains the base or start of the current code segment;
IP contains the distance or offset from this address to the
next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically
shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the
contents of the CS register multiplied by 16 and then offset
is added provided by the IP.
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Segment Data Segment Register
Registers
16-bit
Points to the current data segment; operands for most
instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or
Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Segment Stack Segment Register
Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the
Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Segment Extra Segment Register
Registers
16-bit
Points to the extra segment in which data (in excess of
64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine the 20-
bit physical address for the destination.
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8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Segment Instruction Pointer
Registers
16-bit
Always points to the next instruction to be executed within
the currently executing code segment.
So, this register contains the 16-bit offset address pointing
to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution
of the next instruction takes place.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
16-bit ALU for
performing arithmetic
and logic operation
Four general purpose
registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer);
and
Index registers (Source
Index, Destination Index)
each of 16-bits
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Default segment-offset combinations
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
16-bit ALU for
performing arithmetic
and logic operation
Four general purpose
registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer);
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 26
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,
and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /
outputting 16 or 8 bit data to or from an I/O port.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,
and BH contains the high-order byte.
This is the only general purpose register whose contents
can be used for addressing the 8086 memory.
All memory references utilizing this register content for
addressing use DS as the default segment register.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the
contents of CX as a counter.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte of
the word, and DH contains the high-order byte.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU
Registers
Stack Pointer (SP) and Base Pointer (BP)
SP and BP are used to access data in the stack segment.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
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8086 Microprocessor
Architecture Execution Unit (EU)
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
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