EC5551 –

MICROPROCESSORS AND
MICROCONTROLLERS
8085 Microprocessor
 8085 Microprocessor - Introduction
 The 8085 microprocessor is an 8-bit microprocessor that was
developed by Intel in the mid-1970s.
 The architecture of the 8085 microprocessor consists of several key
components, including the accumulator, registers, program counter,
stack pointer, instruction register, flags register, data bus, address bus,
and control bus.
 The 8085 microprocessor has a 16-bit address bus, allowing it to
address up to 64 KB of memory.
 It also has an 8-bit data bus for transferring data between the
microprocessor and memory or I/O devices.
 Similarly, it employs an 8-bit bidirectional data bus for transferring data
between the microprocessor and memory or I/O devices.
 8085 Microprocessor - Introduction
Arithmetic Logic Unit (ALU)
 The ALU is responsible for performing arithmetic and logical operations on data.
 The ALU operates on 8-bit data and provides flags to indicate conditions such as
zero, carry, sign, and parity
 It is used to perform mathematical operations like addition, multiplication,
subtraction, division, decrement, increment, etc. Different operations are carried
out in ALU: Arithmetic Operations, Logical operations and Bit-Shifting
Operations.
Timing and Control Unit
 The Control Unit coordinates and controls the activities of the other functional
units within the microprocessor.
 It generates timing and control signals to synchronize the execution of
instructions and manage data transfer between different units.
 It produces signals such as RD (Read), WR (Write) and various control signals
required for instruction execution.
Instruction Decoder
 The Instruction Decoder decodes the instructions fetched from memory.
 It determines the type of instruction being executed and generates control
signals accordingly.
 The decoded instructions guide the microprocessor in executing the appropriate
operations.
 8085 Architecture
The 8085 microprocessor architecture has the following registers:

Accumulator (A):
 The accumulator is an 8-bit register used for arithmetic and logical operations. It holds one of the
operands during calculations and stores the result.
General-Purpose Registers (B, C, D, E, H, L):
 The 8085 microprocessor has six general-purpose registers, each of which is 8 bits. These registers
can be used for data manipulation and storage.
Stack Pointer (SP):
 The stack pointer is a 16-bit register that points to the top of the stack. The stack is used to store
return addresses during subroutine calls, as well as local variables and other data.
Program Counter (PC):
 Program counter is a 16-bit register that holds the memory address of the following instruction for
fetching and executing. It automatically increments after each instruction fetch, allowing programs to
execute the next instruction quickly.
Instruction Register (IR)
 The instruction register is an 8-bit register that contains the current instruction being executed. The
instruction register is used by the microprocessor to decode and execute instructions.
Temporary Register:
 It is an 8-bit register that holds data values during arithmetic and logical operations.
 8085 Architecture
Flag Register (F):
The flag register is a 8-bit register that contains several flags that indicate the status of
certain conditions after arithmetic and logical operations. The flags are as follows:

 Carry Flag (C): Set if there is a carry or borrow during arithmetic operations.

 Zero Flag (Z): Set if the result of an operation is zero.

 Sign Flag (S): Set if the result of an operation is negative (MSB set).

 Parity Flag (P): Set if the result of an operation has even parity.

 Auxiliary Carry Flag (AC): Set if there is a carry or borrow from bit 3 to bit 4 during
arithmetic operations.
8085 Architecture
 8085 Architecture
Interrupts:
The 8085 microprocessor supports 5 hardware interrupts as follows:
 INTR
 RST 5.5
 RST 6.5
 RST 7.5
 TRAP
Interrupts allow the microprocessor to respond to external events and handle
them in a prioritized manner.
Priorities of Interrupts: TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR
Interrupt control:
 Whenever a microprocessor is executing the main program and if suddenly an
interrupt occurs, the microprocessor shifts the control from the main
program to process the incoming request. After the request is completed, the
control goes back to the main program.
 8085 Architecture
Address bus and Data bus:
 The data bus is bidirectional and carries the data which is to be
stored. The address bus is unidirectional and carries the location where
data is to be stored.
 In the 8085 microprocessor, the address bus and data bus are two buses
that are used for communication between the microprocessor and
external devices.
 The Address bus is used to transfer the memory address of the data that
needs to be read or written. The address bus is a 16-bit bus, allowing the
8085 to access up to 65,536 memory locations.
 The Data bus is used to transfer data between the microprocessor and
external devices such as memory and I/O devices. The data bus is an 8-
bit bus, allowing the 8085 to transfer 8-bit data at a time. The data bus
can also be used for instruction fetch operations, where the
microprocessor fetches the instruction code from memory and decodes
it.
 The combination of the address bus and data bus allows the 8085 to
communicate with and control external devices, allowing it to execute its
program and perform various operations.
 8085 Architecture
Serial Input/Output control:
 It controls the serial data communication by using Serial input data and Serial output
data.

 Serial Input/Output control in the 8085 microprocessor refers to the communication of

data between the microprocessor and external devices in a serial manner, i.e., one bit at
a time.

 The 8085 has a serial I/O port (SID/SOD) for serial communication.

 The SID pin is used for serial input and the SOD pin is used for serial output.

 The timing and control of serial communication is managed by the 8085’s internal
circuitry.

 The 8085 also has two special purpose registers, the Serial Control Register (SC) and
the Serial Shift Register (SS), which are used to control and monitor the serial
communication.
 8085 Architecture
Instruction Cycle in 8085 Architecture :
 It fetches an instruction from the memory location pointed by Program Counter.

 For address fetching from the memory, multiplexed address/data bus acts as an address bus and after
fetching instruction this address bus will now acts as a data bus and extract data from the specified
memory location and send this data on an 8-bit internal bus. For multiplexed address/data bus Address
Latch Enable(ALE) Pin is used. If ALE = 1 (Multiplexed bus is Address Bus otherwise it acts as Data
Bus).

 The timing and control unit sends control signals all over the microprocessor to tell the microprocessor
whether the given instruction is for READ/WRITE and whether it is for MEMORY/I-O Device activity.

 Hence according to timing and control signal pins, logical and arithmetic operations are performed by
ALU and the flag registers will be updated.

 With the help of Serial I/O data pin(SID or SOD Pins) we can send or receive input/output to external
devices.

 While execution is going on if there is any interrupt detected then it will stop execution of the
current process and Invoke Interrupt Service Routine (ISR) function, which will stop the current
execution and do execution of the interrupt after that normal execution will be performed.
PIN Diagram of 8085 Microprocessor
 PINs of 8085
1.Address Bus and Data Bus:
The address bus is a group of sixteen lines i.e A0-A15. The
address bus is unidirectional, i.e., bits flow in one direction
from the microprocessor unit to the peripheral devices
and uses the high order address bus.
IO/M’ S1 S0 Data Bus Status
2. Control and Status Signals:
 ALE – It is an Address Latch Enable signal. It goes high 0 1 1 Opcode fetch
during first T state of a machine cycle and enables the lower
8-bits of the address, if its value is 1 otherwise data bus is
activated. 0 1 0 Memory read
 IO/M’ – It is a status signal which determines whether the
address is for input-output or memory. When it is high(1) 0 0 1 Memory write
the address on the address bus is for input-output devices.
When it is low(0) the address on the address bus is for the 1 1 0 I/O read
memory.
 SO, S1 – These are status signals. They distinguish the 1 0 1 I/O write
various types of operations such as halt, reading, instruction
fetching or writing.
Interrupt
 RD’ – It is a signal to control READ operation. When it is 1 1 1
acknowledge
low the selected memory or input-output device is read.
 WR’ – It is a signal to control WRITE operation. When it 0 0 0 Halt
goes low the data on the data bus is written into the
selected memory or I/O location.
 READY – It senses whether a peripheral is ready to
transfer data or not. If READY is high(1) the peripheral is
ready. If it is low(0) the microprocessor waits till it goes
high. It is useful for interfacing low speed devices.
 PINs of 8085
3. Power Supply and Clock Frequency:
Vcc – +5v power supply
Vss – Ground Reference
XI, X2 – A crystal is connected at these two pins. The frequency is internally divided by two, therefore, to operate
a system at 3MHZ the crystal should have frequency of 6MHZ.
CLK (OUT) – This signal can be used as the system clock for other devices.

4. Interrupts and Peripheral Initiated Signals:

The 8085 has five interrupt signals that can be used to interrupt a program execution.
(i) INTR
(ii) RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) TRAP

INTR – It is an interrupt request signal.

INTA’ – It is an interrupt acknowledgement sent by the microprocessor after INTR is received. The
microprocessor acknowledges Interrupt Request by INTA’ signal.

5. Reset Signals:
RESET IN’ – When the signal on this pin is low(0), the program-counter is set to zero, the buses are tristated and
the microprocessor unit is reset.
RESET OUT – This signal indicates that the MPU is being reset. The signal can be used to reset other devices.
 PINs of 8085
6. DMA Signals:

HOLD – It indicates that another device is requesting the use of the address and data bus. Having received
HOLD request the microprocessor relinquishes the use of the buses as soon as the current machine cycle is
completed. Internal processing may continue. After the removal of the HOLD signal the processor regains the
bus.

HLDA – It is a signal which indicates that the hold request has been received after the removal of a HOLD
request, the HLDA goes low.

7. Serial I/O Ports:

Serial transmission in 8085 is implemented by the two signals

SID and SOD – SID is a data line for serial input where as SOD is a data line for serial output.
 Instruction Set
The 8085 microprocessor has a comprehensive instruction set that covers a wide range of operations.
Here is an overview of the 8085 microprocessor instruction set categories
Data Transfer Instructions:
MOV: Copy data between registers, memory, and I/O ports.
MOV B,A - Copy data from A to B
MOV C,B – Copy data from B to C
MOV B,M – Copy the data byte from the memory specified by address in HL register to B register
MOV M,C – Copy the data byte from the C register to memory specified by address in HL register
MVI: Move immediate data into a register or memory location.
MVI B, 4FH – Move data to register B
LXI: Load immediate 16-bit data into a register pair.
LXI B, 2050H - Load 16-bit number in a register pair
LDA, STA: Load and store data between the accumulator and memory.
LDA 2050H – Copy the data byte into A from the memory specified by 16-bit address
STA 2070H – Copy the data byte from A into the memory specified by 16-bit address
LDAX B – Copy the data byte into A from the memory specified by the address in the register pair
STAX D – Copy the data byte from A into the memory specified by the address in the register pair
LHLD – Load HL pair direct
SHLD – Store HL pair direct
XCHG - Change the contents of H-L with D-E pair
 Instruction Set
The 8085 microprocessor has a comprehensive instruction set that covers a wide range of
operations.
Here is an overview of the 8085 microprocessor instruction set categories
Arithmetic Instructions:
ADD, ADC: Add data to the accumulator with or without carry.
ADD B – Add the contents of a register B to the contents of A
ADI 37H – Add 37H to the contents of Accumulator
ADD M – Add the contents of memory pointed by HL register to A
SUB, SBB: Subtract data from the accumulator with or without borrow.
SUB C – Subtract the contents of a register from the contents of A
SUI 7F H – Subtract 8-bit data from the contents of A
SUB M – Subtract the contents of memory from A
INR, DCR: Increment or decrement the value of a register or memory location.
INR D – Increment the contents of a register
INR M – Increment the contents of memory pointed by HL register
DCR E – Decrements the contents of a register
DCR M – Decrements the contents of a memory
INX H – Increments the contents of a Register Pair
DCX B – Decrement the contents of a Register Pair
DAD: Add register pair to HL pair. Eg: DAD B, DAD D, DAD H. rp = BC, DE or HL
 Instruction Set
Logic and Bit Manipulation Instructions:
AND, ORA, XOR: Perform bitwise logical operations on the accumulator with
data from registers, memory, or immediate values.
ANA B – Logical AND the contents of B register with the contents of A
ANI 2FH - Logical AND 8-bit data with the contents of A
ANA M – Logical AND the contents of Memory with the contents of A
ORA E – Logical OR the contents of Register with the contents of A
ORI 3FH – Logical OR 8-bit data with the contents of A
ORA M – Logical OR the contents of Memory with the contents of A
XRA B – Exclusive OR the contents of Register with the contents of A
XRI 6AH - Exclusive OR 8-bit data with the contents of A
XRA M – Exclusive OR the contents of memory with the contents of A

CMP: Compare the accumulator with data from registers, memory, or

immediate values.
CMP B – Compare the contents of register with the contents of A
CPI 4FH – Compare 8-bit data with the contents of A
 Instruction Set
Branching Instructions:
JMP: Unconditional jump to a specific memory address.
JMP 2050H – Change the program sequence to the specified 16-bit
address
Conditional Jumps
JC, JNC, JP, JM, JZ, JNZ: Conditional jumps based on the status of the
carry flag (C), parity flag (P), sign flag (M), zero flag (Z), etc.
JZ 2080H – Change the program sequence to the specified 16-bit
address if the Zero flag is set
JNZ 2070H - Change the program sequence to the specified 16-bit
address if the Zero flag is reset
JC 2025H - Change the program sequence to the specified 16-bit
address if the Zero flag is reset
JNC 2030H - Change the program sequence to the specified 16-bit
address if the Zero flag is reset
CALL: Call a subroutine at a specific memory address.
CALL 2075H – Change the program sequence to the location of a
subroutine
RET: Return from a subroutine.
RET – Return to the calling program after completing the
subroutine sequence
 Instruction Set
Stack Instructions:
PUSH, POP: Push and pop data onto and from the
stack.
XTHL: Exchange stack top with HL register pair.
I/O Instructions:
IN, OUT: Input and output data from/to I/O ports.
EI, DI: Enable and disable interrupts.
Machine Control Instructions:
HLT: Halt the microprocessor.
NOP: No operation.
Summary of Instruction Set
Summary of Instruction Set
 Addressing Modes
The 8085 microprocessor has several addressing modes that
are used to access memory locations. Some of the most commonly
used addressing modes in the 8085 microprocessor are:

1. Immediate Addressing Mode

In Immediate addressing mode, the source operand is always
data. If the data is 8-bit, then the instruction will be of 2 bytes, if the data is
of 16-bit then the instruction will be of 3 bytes.

Examples:
MVI B 45 (move the data 45H immediately to register B)
LXI H 3050 (load the H-L pair with the operand 3050H immediately)
JMP address (jump to the operand address immediately)
 Addressing Modes
2. Register Addressing Mode
In register addressing mode, the data to be operated is available inside the
register(s) and register(s) is(are) operands. Therefore the operation is performed
within various registers of the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result in register A)
INR A (increment the contents of register A by one)

3. Direct Addressing Mode

In direct addressing mode, the data to be operated is available inside a
memory location and that memory location is directly specified as an operand. The
operand is directly available in the instruction itself.
Examples:
LDA 2050 (load the contents of memory location into accumulator A)
LHLD address (load contents of 16-bit memory location into H-L register pair)
IN 35 (read the data from port whose address is 35)
 Addressing Modes
4. Register Indirect Addressing Mode
In register indirect addressing mode, the data to be operated is
available inside a memory location and that memory location is indirectly
specified by a register pair.
Examples:
MOV A, M (move the contents of the memory location pointed by the H-L pair to the
accumulator)
LDAX B (move contents of memory location pointed by B-C register to the
accumulator)
STAX B (store accumulator contents in memory pointed by register pair B-C)

5. Implied/Implicit Addressing Mode

In implied/implicit addressing mode, the operand is hidden and the data
to be operated is available in the instruction itself.
Examples:
CMA (finds and stores the 1’s complement of the contents of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
 Addressing Modes
6.Relative Addressing Mode:
In this mode, the operand is a memory location specified by the contents of the
program counter plus a constant value.
Example:
MOV R0,#05H
AGAIN:
MVI A,#55H
ADD A,R0
JMP AGAIN

7. Memory-mapped I/O addressing:

In memory-mapped I/O addressing mode, the processor accesses input/output
devices using memory addresses instead of specialized I/O instructions. Memory-
mapped I/O addressing mode is used for interfacing with peripherals such as displays,
keyboards, and printers.
 Interrupts
 In the 8085 microprocessor, an interrupt is a signal that temporarily suspends the normal
execution of a program and redirects the control to a specific interrupt service routine (ISR).
 Interrupts allow the microprocessor to respond to external events, such as user input, system
events, or hardware signals, without the need for constant polling.
 When microprocessors receive interrupt signals through pins (hardware) of microprocessor,
they are known as Hardware Interrupts.
 There are 5 Hardware Interrupts in 8085 microprocessor.
 They are INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Maskable and Non-Maskable Interrupts

Maskable Interrupts are those which can be disabled or ignored by the microprocessor. These
interrupts are either edge-triggered or level-triggered, so they can be disabled. INTR, RST 7.5, RST 6.5, RST
5.5 are maskable interrupts in 8085 microprocessor.

TRAP: The TRAP interrupt is a has the highest priority and cannot be disabled. It consists of both level as
well as edge triggering non-maskable interrupt that is generated by an external device, such as a power
failure or a hardware malfunction. The TRAP interrupt and is used in critical power failure conditions.
 Interrupts
RST 7.5: This is positive-edge sensitive and can be triggered with a short pulse. The request is stored
internally by the D flip-flop until the microprocessor responds to the request or until it is cleared by
Reset or by bit D4 in the SIM instruction. It has the second highest priority.
RST 6.5 and RST 5.5: These interrupts are level sensitive, meaning that the triggering level should be
on until the microprocessor completes the execution of the current instruction. If the microprocessor
is unable to respond to these requests immediately, they should be stored or held by external hardware.
INTR: The INTR interrupt is a maskable interrupt that is generated by an external device, such as a
keyboard or a mouse. It has the lowest priority and can be disabled.
EI : Enable Interrupts
MVI A,08H : Load bit pattern to enable RST 7.5,6.5 and 5.5
SIM : Enable RST 7.5, 6.5 and 5.5
 Interrupts
SIM Instruction: Set Interrupt Mask

This is a one-byte instruction and can be used for three different functions.

1. One function is to set mask for RST 7.5,6.5 and 5.5 interrupts. This instruction reads the
content of the Accumulator and enables or disables the interrupt according to the content of the
accumulator. Bit D3 is a control bit and should=1 for bits D0, D1 and D2 to be effective. Logic 0 on
D0,D1 and D2 will enable the corresponding interrupts and logic 1 will disable the interrupts.
2. The second function is to reset RST 7.5 flip-flop. Bit D4 is additional control for RST 7.5. If
D4=1, RST 7.5 is reset. This is used to override RST 7.5 without servicing it.
3. The third function is to implement serial I/O. Bits D7 and D6 of the accumulator are used
for serial I/O and do not affect the interrupts. Bit D6=1 enables the serial I/O and Bit D7 is used to
transmit (output) bits.

Enable all the interrupts in an 8085 system

EI Enable Interrupts
MVI A,08H Load bit pattern to enable RST 7.5, 6.5 and 5.5
SIM Enable RST 7.5, 6.5 and 5.5
 Interrupts
RIM – Read Interrupt Mask. This is a 1-byte instruction that can be used for the following functions.
To read interrupt masks
RIM Read Interrupt Mask
MOV B,A Save mask information
ANI 20H Check whether RST 6.5 is pending
This instruction loads the accumulator with 8 bits indicating the current status of the interrupt
masks.
To identify pending interrupts, bits D4,D5 and D6 identify the pending interrupts.
To receive serial data. Bit D7 is used to receive serial data.
 Interrupts
Software Interrupts or Restart Instructions
Software Interrupts are those which are inserted in between the
program which means these are mnemonics of microprocessor.
The 8085 instruction set includes eight RST (Restart) instructions. These
are 1-byte Call instructions that transform the program execution to a specific
location on Page 00H. The RST instructions are executed in a similar way to that
of Call instructions.
 They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
 Interrupts INTERRUPT
VECTOR
ADDRESS

Vectored and Non-Vectored Interrupts RST 0 00 H

RST 1 08 H
Vectored Interrupts are those which have fixed vector
address (starting address of sub-routine) and after RST 2 10 H

executing these, program control is transferred to RST 3 18 H

that address. Vector Addresses are calculated by the RST 4 20 H

formula 8 * TYPE RST 5 28 H

RST 6 30 H

Non-Vectored Interrupts are those in which vector RST 7 38 H

address is not predefined. The interrupting device VECTOR

INTERRUPT
ADDRESS
gives the address of sub-routine for these
TRAP (RST 4.5) 24 H
interrupts. INTR is the only non-vectored interrupt in
RST 5.5 2C H
8085 microprocessor.
RST 6.5 34 H

RST 7.5 3C H
 Timing diagrams
The 8085 instruction timing diagram represents the execution time
of each instruction in graphical format. Execution time is given in T-states.
The 8085 microprocessor has a set of control signals and data
signals that play an important role in the execution of instructions.

 Machine Cycle: The time required to access memory or input/output

devices is called a machine cycle. The 8085 has 5 basic machine cycles i.e.,
load opcode, read from memory, write to memory, read I/O, and write
I/O.
 T-State: A machine cycle and an instruction cycle take several clock
periods. The portion of an operation performed in one system clock
period is called a T-state.
 Control Signals: The control signal controls the operations. Common
signals are ALE (address block enable), RD (read), WR (write), and IO/M
(input/output) memory.
 Machine Cycle of 8085

The 8085 microprocessor has 5 basic machine cycles.

They are :
 Opcode Fetch {4T- state}

 Memory Read {3T- state}

 Memory Write {3T- state}

 I/O Read {3T- state}

 I/O Write {3T- state}

8085 Machine Cycle status and control
signals
Opcode Fetch Machine Cycle of 8085
 Each processor instruction has a one byte opcode.
 Operation codes are stored in memory. Thus, the processor performs an opcode load machine cycle
to load the opcode from memory.
 Thus, each instruction begins with a machine cycle of opcodes.
 The time the processor takes to perform an opcode load cycle is 4T.
 At this time, the first, 3T-states are used to load the opcode from memory, and the remaining T-states
are used for decoding.
Memory Read Machine Cycle of 8085
 A memory read machine cycle is executed by the processor to read a data byte from
memory.
 The processor takes 3T states to perform this cycle.
 Instructions that have more than one byte word will use machine cycle after machine cycle
to load the opcode.
Memory Write Machine Cycle of 8085
 A write-to-memory machine cycle is executed by the processor to write a data byte to
memory.
 The processor takes 3T states to perform this cycle.
 Instructions that have more than one byte word will use machine cycle after machine
cycle to load the opcode.
 I/O Read Machine Cycle
 A reader I/O cycle is performed by the processor to read a
data byte from an I/O port or peripheral that is I/O mapped in
the system.
 The processor needs 3T states to execute this machine cycle.
 I/O Write Machine Cycle
 A writer’s I/O cycle is executed by the processor to write a data byte to an
I/O port or peripheral that is I/O mapped in the system.
 The processor needs 3T states to execute this machine cycle.
 Timing diagram of an instruction
Timing Diagram of MVI A,32H
 Loading opcode 3EH from memory 2000H. (Operation Code Loading Machine Cycle)
 Read (move) data 32H from memory 2001H. (memory reading).

Address Mnemonics Opcode

2000H MVI A,45H 4EH

2001H 45H
 Timing diagram of an instruction
Timing Diagram of STA 8000H
 8085 – Memory Interfacing
Memory Interfacing
 The microprocessor needs to access the memory
for reading instruction codes and the data stored in
the memory.
 For this, both the memory and the microprocessor
requires some signals to read from and write to
registers.
 The interfacing process includes some key factors to
match with the memory requirements and
microprocessor signals.
 The interfacing circuit therefore should be designed
in such a way that it matches the memory signal
requirements with the signals of the microprocessor.
Basic concepts in Memory Interfacing

The primary function of memory interfacing is that the microprocessor should be able to
Read from or write into a given register of a memory chip.
The microprocessor should
1. Be able to select the chip
2. Identify the register
3. Enable the appropriate buffer
 8085 - Memory Interfacing
1. The 8085 places a 16-bit address on the address
bus, and with this address only one register
should be selected.
2. For the memory chip in figure, only 12 address
lines are required to identify 4096 registers.
3. Therefore, we can connect the low-order address
lines A11-A0 of the 8085 address bus to the
memory chip.
4. The internal decoder of the memory chip will
identify and select the register for the EPROM.
5. The remaining 8085 address lines (A15-A12)
should be decoded to generate a unique Chip
Select (CS) signal.
6. The 8085 provides two signals-IO/M and RD to
indicate that it is a memory read operation.
7. The IO/M and RD can be combined to generate
the MEMR control signal that can be used to
enable the output buffer by connecting to the
memory signal RD
 I/O Interfacing
 There are various communication devices like the
keyboard, mouse, printer, etc.
 Data can enter in groups of eight bits using the
entire data bus; this is called the parallel I/O mode
 The other method is the serial I/O, whereby one
bit is transferred using one data line.
 The microprocessor needs to identify I/O devices
with a binary number.
Identification of I/O devices
Memory mapped I/O
Peripheral mapped I/O
 Memory Mapped I/O Peripheral Mapped I/O

 These I/O devices can be  The 8085 microprocessor

interfaced using addresses has a separate 8-bit
(binary numbers) from the addressing scheme for I/O
memory space; this is called devices. This is called
memory mapped I/O. peripheral mapped I/O.
 A device is identified with a  The IO space ranges from
16-bit address and enabled 00H to FFH. A device is
by memory related control identified with an 8-bit
signals. address and enabled by I/O
 Data bytes are transferred related control signals.
using memory related LDA  Data bytes are transferred
, STA data transfer by using IN/OUT
instructions instructions
Memory Mapped I/O
OUTPUT PORT AND ITS ADDRESS

INPUT PORT AND ITS ADDRESS

Peripheral mapped I/O – Interfacing
LED Output port
Peripheral mapped I/O – Interfacing
LED Output port
Interfacing 7-segment LED Display
Interfacing 7-segment LED Display
8086 Microprocessor
 8086 Microprocessor - Introduction
 The 8086 microprocessor is an 8-bit/16-bit microprocessor designed by Intel in the late 1970s.

 It is the first member of the x86 family of microprocessors, which includes many popular CPUs used
in personal computers.

 The architecture of the 8086 microprocessor is based on a complex instruction set computer
(CISC) architecture, which means that it supports a wide range of instructions, many of which can
perform multiple operations in a single instruction.

 The 8086 microprocessor has a 20-bit address bus, which can address up to 1 MB of memory, and a
16-bit data bus, which can transfer data between the microprocessor and memory or I/O devices.

 The 8086 microprocessor has a segmented memory architecture, which means that memory is
divided into segments that are addressed using both a segment register and an offset.

 The segment register points to the start of a segment, while the offset specifies the location of a
specific byte within the segment. This allows the 8086 microprocessor to access large amounts of
memory, while still using a 16-bit data bus.
 8086 Microprocessor - Introduction
 A Microprocessor is an Integrated Circuit with all the functions of a CPU. However, it cannot be used
stand-alone since unlike a microcontroller it has no memory or peripherals.

 8086 does not have a RAM or ROM inside it.

 However, it has internal registers for storing intermediate and final results and interfaces with memory
located outside it through the System Bus.

 In the case of 8086, it is a 16-bit Integer processor in a 40-pin, Dual Inline Packaged IC.

 The size of the internal registers(present within the chip) indicates how much information the processor
can operate on at a time (in this case 16-bit registers) and how it moves data around internally within the
chip, sometimes also referred to as the internal data bus.

 8086 provides the programmer with 14 internal registers, each of 16 bits or 2 bytes wide. The main
advantage of the 8086 microprocessor is that it supports Pipelining.
 8086 Microprocessor - Architecture
 The 8086 microprocessor has two main execution units:

 the Execution Unit (EU) and the Bus Interface Unit (BIU).
 The BIU is responsible for fetching instructions from memory and decoding them,
while the EU executes the instructions.
 The BIU also manages data transfer between the microprocessor and memory or I/O
devices.

 The 8086 microprocessor has a rich set of registers, including general-purpose

registers, segment registers, and special registers.

 The general-purpose registers can be used to store data and perform arithmetic and
logical operations, while the segment registers are used to address memory segments.
 The special registers include the flags register, which stores status information about
the result of the previous operation, and the instruction pointer (IP), which points to
the next instruction to be executed.
8086 Microprocessor - Architecture
 8086 Microprocessor - Architecture
Memory segmentation:
 In order to increase execution speed and fetching speed, 8086 segments the memory.
 Its 20-bit address bus can address 1MB of memory, it segments it into 16 64kB segments.
 8086 works only with four 64KB segments within the whole 1MB memory.

The internal architecture of Intel 8086 is divided into 2 units:

The Bus Interface Unit (BIU), and
The Execution Unit (EU).

These are explained as following below.

1. The Bus Interface Unit (BIU):
 It provides the interface of 8086 to external memory and I/O devices via the System Bus. It
performs various machine cycles such as memory read, I/O read, etc. to transfer data between
memory and I/O devices.
 BIU performs the following functions are as follows:
 It generates the 20-bit physical address for memory access.
 It fetches instructions from the memory.
 It transfers data to and from the memory and I/O.
 Maintains the 6-byte pre-fetch instruction queue(supports pipelining).
 8086 Microprocessor - Architecture
1. Bus Interface Unit
 BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and
an Address Generation Circuit.
Instruction Pointer (IP):
 It is a 16-bit register. It holds offset of the next instructions in the Code Segment.
 IP is incremented after every instruction byte is fetched.
 IP gets a new value whenever a branch instruction occurs.
 CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
 The address of the next instruction is calculated by using the formula CS x 10H + IP.
Example:
 CS = 4321H IP = 1000H then CS x 10H = 43210H + offset = 44210H Here Offset = Instruction
Pointer(IP)This is the address of the next instruction.

Four Segment Registers

 Code Segment register: (16 Bit register): CS holds the base address for the Code Segment.
All programs are stored in the Code Segment and accessed via the IP.
 Data Segment register: (16 Bit register): DS holds the base address for the Data Segment.
 Stack Segment register: (16 Bit register): SS holds the base address for the Stack Segment.
 Extra Segment register: (16 Bit register): ES holds the base address for the Extra Segment.
 8086 Microprocessor - Architecture
Address Generation Circuit:

 The BIU has a Physical Address Generation Circuit.

 It generates the 20-bit physical address using Segment and Offset addresses using
the formula:

Physical Address = Segment Address x 10H + Offset Address

Example:
CS = 4321H
IP = 1000H
then CS x 10H = 43210H + offset = 44210H
Here Offset = Instruction Pointer(IP)
In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible
for the calculation unit which is used to calculate the physical address of an instruction
in memory.
 8086 Microprocessor - Architecture
6 Byte Pre-fetch Queue:
 It is a 6-byte queue (FIFO). Fetching the next instruction (by BIU from CS) while executing
the current instruction is called pipelining.
 Gets flushed whenever a branch instruction occurs.
 The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can
have in 8086 is 6 bytes. Hence to cover up all operands and data fields of maximum size
instruction in 8086 Microprocessor there is a Pre-Fetch queue is 6 Bytes.
 The pre-Fetch queue is connected with the control unit which is responsible for decoding
op-code and operands and telling the execution unit what to do with the help of timing and
control signals.
 The pre-Fetch queue is responsible for pipelining and because of that 8086 microprocessor
is called fetch, decode, execute type microprocessor. Since there are always instructions
present for decoding and execution in this queue the speed of execution in the
microprocessor is gradually increased.
 When there is a 2-byte space in the instruction pre-fetch queue then only the
next instruction will be pushed into the queue otherwise if only a 1-byte space is
vacant then there will not be any allocation in the queue. It will wait for a spacing of 2 bytes
in subsequent queue decoding operations.
 Instruction pre-fetch queue works in a sequential manner so if there is any branch condition
then in that situation pre-fetch queue fails. Hence to avoid chaos instruction queue is flushed
8086 Microprocessor - Architecture
3.The Execution Unit (EU):
 The main components of the EU are General purpose registers, the ALU,
Special purpose registers, the Instruction Register and Instruction Decoder,
and the Flag/Status Register.
 Fetches instructions from the Queue in BIU, decodes, and executes arithmetic
and logic operations using the ALU.
 Sends control signals for internal data transfer operations within the
microprocessor.(Control Unit)
 Sends request signals to the BIU to access the external module.
 It operates with respect to T-states (clock cycles) and not machine cycles.
 8086 Microprocessor - Architecture
 All instructions are stored in memory hence to fetch any instruction first task is to obtain the Physical address of the

instruction is to be fetched.

 Hence this task is done by Bus Interface Unit (BIU) and by Segment Registers. Suppose the Code segment has a

Segment address and the Instruction pointer has some offset address then the physical address calculator circuit

calculates the physical address in which our instruction is to be fetched.

 After the address calculation, instruction is fetched from memory and it passes through C-Bus (Data bus) as shown in

the figure, and according to the size of the instruction, the instruction pre-fetch queue fills up. For example MOV AX,

BX is 1 Byte instruction so it will take only the 1st block of the queue, and MOV BX,4050H is 3 Byte instruction so it

will take 3 blocks of the pre-fetch queue.

 When our instruction is ready for execution, according to the FIFO property of the queue, instruction comes into the

control system or control circuit which resides in the Execution unit. Here instruction decoding takes place. The

decoding control system generates an opcode that tells the microprocessor unit which operation is to be performed.

So the control system sends signals all over the microprocessor about what to perform and what to extract from

General and Special Purpose Registers.

 8086 Microprocessor - Architecture
 Hence after decoding microprocessor fetches data from GPR and according to instructions like ADD,

SUB, MUL, and DIV data residing in GPRs are fetched and put as ALU’s input. After that addition,

multiplication, division, or subtraction whichever calculation is to be carried out.

 According to arithmetic, flag register values change dynamically.

 While Instruction was decoding and executing, the Bus interface Unit doesn’t remain idle. it

continuously fetches an instruction from memory and put it in a pre-fetch queue and gets

ready for execution in a FIFO manner whenever the time arrives.

 So in this way, unlike the 8085 microprocessor, here the fetch, decode, and execution process happens

in parallel and not sequentially. This is called pipelining, and because of the instruction pre-fetch queue,

all fetching, decoding, and execution process happen side-by-side.

 Hence there is partitioning in 8086 architecture like Bus Interface Unit and Execution Unit to support

Pipelining phenomena.
8086 Microprocessor - Architecture

 6 conditional flags and 3 control flags

 6 conditional flags are set or reset by EU on the basis of the results
of some arithmetic or logic operation.
 3 control flags are set or reset with specific instructions
Memory in 8086 Microprocessor
Physical address in code segment
Physical address in stack segment
Physical address in data segment
 Addressing Modes in 8086
The different ways in which a processor can access data are referred to as its
addressing modes.
MOV Destination, Source
a) Immediate Addressing Mode
MOV CX, 437BH
MOV CL, 48H
b) Register Addressing Mode
MOV CX,AX
MOV CH,AL
c) Direct Addressing Mode
MOV BX, [437AH]
The byte at a displacement of 437A from the data segment base -> BL and
437BH will be copied to BH
MOV [437AH],BX
The contents of BL will be copied to the memory location at a
displacement of 437AH and the contents of BH will be copied to memory
location at a displacement of 437BH.
 Instruction set and Programming
Data transfer instructions in 8086
microprocessor
 Data transfer instructions in the 8086 microprocessor are used to move data
between memory locations, registers, and input/output (I/O) devices.

 These instructions are essential for manipulating data within a program, as well
as for communicating with external devices.

 Data transfer instructions are a fundamental part of programming in the 8086

microprocessor, and are used extensively in applications ranging from simple
data manipulation to complex I/O device communication and string processing.

 Data transfer instructions are the instructions which transfers data in the
microprocessor. They are also called copy instructions.
Instruction set and Programming
Instruction set and Programming
Instruction set and Programming
Instruction set and Programming
Instruction set and Programming
Instruction set and Programming
Instruction set and Programming
Instruction set and Programming
Conditional Instructions:
These instructions are often used after a
compare instruction.
The terms below and above refer to
unsigned binary numbers.
Above means larger in magnitude.
The terms greater than or less than refer to
signed binary numbers.
Greater than means more positive.
Instruction set and Programming
Instruction set and Programming
Instruction set and Programming
 Instruction set and Programming
Algorithm for Addition program

1. Load 0000H into CX register (for carry)

2. Load the data into AX(accumulator) from

memory 3000

3. Load the data into BX register from memory

3002

4. Add BX with Accumulator AX

5. Jump if no carry

6. Increment CX by 1

7. Move data from AX(accumulator) to memory

3004

8. Move data from CX register to memory 3006

9. Stop
Instruction set and Programming
Program to move the string from one address to another
address
MOV AX, 7000H Assign source segment address to AX
MOV DS, AX Load source segment address into DS
MOV AX, 8000H Assign destination segment address to AX
MOV ES,AX Load source segment address into ES
MOV CX, 0E0H Move the length of the string to the counter register CX
MOV SI, 3000H Assign source index address to SI
MOV DI, 4000H Assign destination index address to DI
CLD Ensure auto-increment mode is set by clearing the
direction flag
REP MOVSB Repeat the move byte from source to destination
instruction CX times
 Instruction set and Programming
Program for comparison of string

MOV AX, SEG_STRING1 Move the segment address of STRING1 to AX

MOV DS, AX Load it to DS
MOV AX, SEG_STRING2 Move the segment address of STRING2 to AX
MOV ES, AX Load it to ES
MOV SI, OFFSET_STRING1 Move the offset of STRING1 to SI
MOV DI, OFFSET_STRING2 Move the offset of STRING2 to DI
MOV CX, 020H Move the length of the strings to CX
CLD Clear the direction flag, set auto-increment
mode
REPE CMPSB Compare the 020H bytes of STRING1 and
STRING2,while they are equal, If mismatch is
found modify the flags and proceed with
further Execution
NOTE: If Both Strings are equal, CX becomes ZERO, the ZF is set otherwise ZF is
reset
 Instruction set and Programming

Program for Match of a Character

MOV AX, SEGMENT_STR Move the segment address of the String to AX

MOV ES, AX Load it to ES
MOV DI, OFFSET_STR Move the offset of String to DI
MOV CX, 020H Move the length of the String to CX
MOV AL, CHAR_TO_FIND The word to be scanned for is loaded into AL
CLD Clear the direction flag
REPNE SCASB Scan the 020H words of the String until a match to
the byte is found
8086 – Pin Diagram
 8086 – Pin Diagram
 AD0-AD15: Address/Data bus. These are low order address bus. They are
multiplexed with data. When AD lines are used to transmit memory address the
symbol A is used instead of AD, for example A0-A15. When data are transmitted
over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15
or D0-D15.
 A16-A19: High order address bus. These are multiplexed with status signals.

Status Signals: The four most significant

address lines A16 through A19 of the 8086 are
multiplexed with status signals S3 through S6.
These status bits are output on the bus at the
same time that data are transferred over the
other bus lines.
S4, S3: together indicates which segment
register is presently being used for memory
access.
The status of the Interrupt Enable Flag (IF) bit
(displayed on S5) is updated at the beginning of
each clock cycle.
S6: It is always low.
 8086 – Pin Diagram
 S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to
passive state (1,1,1 during T3 or Tw (when ready is inactive). These are used by the 8288
bus controller for generating all the memory and I/O operation) access control signals. Any
change in S2, S1, S0 during T4 indicates the beginning of a bus cycle.
 BHE’/S7:
◦ 8086 has Memory Banks. 2 banks of 512KB each. These banks are called as lower Bank (even) and
higher Bank (odd)
◦ It goes low for the data transfers over D15 – D8 and is used to derive chip selects of odd address
memory bank or peripherals.
◦ BHE is low during T1, whenever a byte is to be transferred on the higher byte of the data bus.
◦ The status information is available during T2, T3 and T4.
◦ It is low during T1 for the first pulse of the interrupt acknowledge cycle. S7 is not currently used.
 8086 – Pin Diagram
 RD’: This is used for read operation. It is an output signal. It is active when low.
 READY : This is the acknowledgement from the memory or slow device that
they have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the
microprocessor. The signal is active high(1).
 INTR : Interrupt Request. This is triggered input. This is sampled during the last
clock cycles of each instruction for determining the availability of the request. If
any interrupt request is found pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked after resulting the interrupt
enable flag. This signal is active high(1) and has been synchronized internally.
 NMI : Non maskable interrupt. This is an edge triggered input which results in a
type II interrupt. A subroutine is then vectored through an interrupt vector
lookup table which is located in the system memory. NMI is non-maskable
internally by software. A transition made from low(0) to high(1) initiates the
interrupt at the end of the current instruction. This input has been synchronized
internally.
 INTA : Interrupt acknowledge. It is active low(0) during T2, T3 and Tw of each
interrupt acknowledge cycle.
 8086 – Pin Diagram
 MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will
operate in.
 RQ’/GT1′, RQ’/GT0′ :
 These pins are used by other local bus masters in maximum mode, to force the processor to
release local bus at the end of processor’s current bus cycle.
 Each of the pins is bidirectional with RQ/GT0 having the higher priority than RQ/GT1.
 The request and grant pulses are active low.
 LOCK’ : Its an active low pin. It indicates that other system bus masters have not
been allowed to gain control of the system bus while LOCK’ is active low(0). The
LOCK signal will be active until the completion of the next instruction.
 TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution
will continue, else the processor remains in an idle state. The input is internally
synchronized during each of the clock cycle on leading edge of the clock.
 CLK : Clock Input. The clock input provides the basic timing for processing operation
and bus control activity. Its an asymmetric square wave with a 33% duty cycle.
 RESET : This pin requires the microprocessor to terminate its present activity
immediately. The signal must be active high(1) for at least four clock cycles.
 Vcc : Power Supply( +5V D.C.)
 GND : Ground
 8086 – Pin Diagram
 QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according to
the table shown below:

 M/IO’: This signal is used to distinguish between memory and I/O operations. The M Signal is Active high
whereas the IO’ Signal is Active Low. When this Pin is High, the memory operations takes place. On the other
hand, when the Pin is low, the Input/Output operations from the peripheral devices takes place.
 DT/R : Data Transmit/Receive. This pin is required in minimum systems, that want to use an 8286 or 8287 data
bus transceiver. The direction of data flow is controlled through the transceiver.
 DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system which
uses transceiver. DEN is active low(0) during each memory and input-output access and for INTA cycles.
 HOLD/HOLDA: HOLD indicates that another device has been requesting a local bus .This is an active
high(1). The microprocessor receiving the HOLD request will issue HLDA (high) as an acknowledgement in
the middle of a T4 or T1 clock cycle.
 ALE : Address Latch Enable. ALE is provided by the microprocessor to latch the address into the 8282 or
8283 address latch. It is an active high(1) pulse during T1 of any bus cycle.
Minimum and Maximum Mode Configurations
In the 8086 microprocessor, there are two modes of operation:
1. Minimum mode
2. Maximum mode.

Minimum Mode
Minimum mode is used when the 8086 microprocessor is operating as a standalone
processor without any external coprocessors or support chips.

The minimum mode requires a minimum set of support chips, such as clock
generator, address latch, and decoder.
When MN/MX’ = 1, the 8086 microprocessor runs in the minimum mode. All the
control signals required for memory operations and I/O interfaces are provided by the
system’s only processor running in minimum mode, the 8086, alone.
 Minimum Mode Configuration
 The circuit in this case is simple, but it does not permit multiprocessing.
 In this mode, the microprocessor chip itself transmits all control signals.
The system’s latches, transceiver, clock generator, memory, and I/O
devices make up the remaining parts.
 Minimum Mode Configuration
 8282 (8 bits) latch :
The latches are buffered D FF. They are used to separate the valid address from the multiplexed
Address/data bus by using the control signal ALE, which is connected to strobe(STB) of 8282.The ALE is
active high signal. Here three such latches are required because the address is 20 bits.

 8286 (8 bits) transceivers :

They are bidirectional buffers and also known as data amplifiers. They are used to separate the valid data
from multiplexed add/data bus. Two such transceivers are needed because the data bus is 16 bits long. 8286
is connected to DT/R’ and DEN’ signals. They are enabled through the DEN signal .The direction of data on
the data bus is controlled by the DT/R’ signal. DT/R’ is connected to T and DEN’ is connected to OE’.
 Minimum Mode Configuration
 8284 clock generator is used to provide the clock.
 M/IO’= 1,then memory transfer is performed over the bus. and when M/IO’ = 0, then I/O
operation is performed.
 The signals RD’ and write WR’ are used to identify whether a read bus cycle or a write
bus cycle is performing. When WR’ = 0 ,then it indicates that valid output data on the data
bus.
 RD’ indicates that the 8086 is performing a read data or instruction fetch process is
occurring.
 Control signals for all operations are generated by decoding M/IO’, RD’, WR’. They are
decoded by 74138 3:8 decoder.
 Minimum Mode Configuration
INTR and INTA :
When INTR = 1,then there is an interrupt to 8086 by other devices for their
service. When INTA’= 0,then it indicates that the processor is ready to
service them.
 The bus request is made by other devices using the HOLD signal and the
processor acknowledges them using the HLDA output signal.

Timing diagram :
The working of min mode can be easily understood by timing diagrams.
 All processors bus cycle is of at least 4 T-states(T1,T2,T3,T4) .The address is
given by processor in the T1 state. It is available on the bus for one T-state.
 In T2, the bus is tristated for changing the direction of the bus( in the case of a
data read cycle.)
 The data transfer takes place between T3 and T4.
 If the addressed device is slower, then the wait state is inserted between
T3 and T4.
Timing Diagram – Memory Read

 At T1 state, ALE =1 ,this indicates that a

valid address is latched on the address
bus and also M / IO’= 1, which indicates
the memory operation is in progress.
 In T2, the address is removed from the
local bus and is sent to the addressed
device. Then the bus is tristated.
 When RD’ = 0 , the valid data is
present on the data bus.
 During T2 , DEN’ =0, which enables
transceivers and DT/R’ = 0 ,which
indicates that the data is received.
 During T3, data is put on the data bus
and the processor reads it.
 The output device makes the READY
line high. This means the output device
has performed the data transfer
process. When the processor makes
the read signal to 1, then the output
device will again tristate its bus drivers.
Timing Diagram – Memory Write

 At T1 state, ALE =1, this indicates that a

valid address is latched on the address
bus and also M/IO’= 1, which indicates
the memory operation is in progress.
 In T2, the processor sends the data to
be written to the addressed location.
 The data is buffered on the bus until
the middle of T4 state.
 The WR’=0 becomes at the beginning
of T2.
 The BHE’ and A0 signals are used to
select the byte or bytes of memory or
I/O word.
 During T2 DEN’ =0, which enables,
transceivers and DT/R’ = 1 ,which
indicates that the data is transferred by
the processor to the addressed device.
 8086 - Maximum Mode Configurations
Maximum Mode
 Maximum mode is used when the 8086 microprocessor is operating with
one or more external coprocessors or support chips.
 In this mode, the 8086 uses a multiplexed bus for data and instructions,
and a 20-bit address bus.
 The maximum mode requires additional support chips, such as a bus
controller, a clock generator, and a data buffer.

Advantages of max mode of 8086:

 It helps to interface more devices like 8087.This interface is also called
a closely coupled co-Processor configuration. In this 8086 is called as the
host and 8087 as Co-processor.
 It supports multiprocessing, Therefore it helps to increase the efficiency.
 The 8087 was the first floating-point coprocessor for the 8086 series of
microprocessors.
 The purpose of the 8087 was to increase calculations for floating point
operations, such as add, sub, multiply, divide, and square root.
 Maximum Mode Configurations
 In this we can connect more processors to 8086 (8087/8089).
 8086 max mode is basically for implementation of allocation of global resources and passing
bus control to other coprocessor(i.e. second processor in the system), because two
processors can not access system bus at same instant.
 All processors execute their own program.
 Maximum Mode Configurations
 When MN/ MX’ = 0 , 8086 works in max mode.

 Clock is provided by 8284 clock generator.

 8288 bus controller - Address from the address bus is latched into 8282 8-bit latch. Three such
latches are required because address bus is 20 bit. The ALE(Address latch enable) is connected to
STB(Strobe) of the latch. The ALE for latch is given by 8288 bus controller.

 The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
because data bus is 16-bit. The transceivers are enabled, the DEN signal, while the direction of data is
controlled by the DT/R signal. DEN is connected to OE’ and DT/R’ is connected to T. Both DEN
and DT/ R’ are given by 8288 bus controller.
 Minimum and Maximum Mode Configurations
Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288
bus controller.
Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0/GT0 has more priority than
RQ1/GT1.
INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
In max mode, the advanced write signals get enabled one T-state in advance as compared to normal
write signals. This gives slower devices more time to get ready to accept the data, therefore it
reduces the number of cycles.
Difference between Minimum and Maximum Mode
Thank You!!!