CD74HC4067, CD74HCT4067

SCHS209D – NOVEMBER 1998 – REVISED DECEMBER 2024

CD74HCx4067 High-Speed CMOS Logic 16-Channel Analog Multiplexer and

Demultiplexer
1 Features • Signal gating
• Modulators
• Wide analog input voltage range • Squelch controls
• Low ON resistance • demodulators
– VCC = 4.5V, 70Ω (typ) • choppers
– VCC = 6V, 60Ω (typ) • commutating switches
• Fast switching and propagation speeds • Analog-to-digital and digital-to-analog conversions
• Break-before-make switching • Digital control of frequency, impedance, phase,
– 6ns (typ) at 4.5V and analog-signal gain
• Available in both narrow- and wide-body plastic
3 Description
packages
• Fanout (over-temperature range) The CD74HC4067 and CD74HCT4067 devices are
– Standard outputs: 10 LSTTL loads digitally controlled analog switches that use silicon-
– Bus driver outputs: 15 LSTTL loads gate CMOS technology to achieve operating speeds
• Wide operating temperature range: –55°C to similar to LSTTL, with the low power consumption of
+125°C standard CMOS integrated circuits.
• Balanced propagation delay and transition times These analog multiplexers and demultiplexers control
• Significant power reduction compared to LSTTL analog voltages that may vary across the voltage
logic ICs supply range. They are bidirectional switches, thus
• HC types allowing any analog input to be used as an output and
– 2V to 6V operation vice-versa. The switches have low on resistance and
– High noise immunity: NIL = 30%, NIH = 30% of low off leakages. In addition, these devices have an
VCC at VCC = 5V enable control that, when high, disables all switches
• HCT types to their off state.
– 4.5V to 5.5V operation
– Direct LSTTL input logic compatibility, VIL= 0.8V Package Information
(max), VIH = 2V (min) PART NUMBER PACKAGE (1) BODY SIZE (NOM)
– CMOS input compatibility, Il ≤ 1µA at VOL, VOH CD74HC4067M SOIC(24) 15.4mm × 10.3mm
CD74HC4067M96 SOIC(24) 15.4mm × 10.3mm
2 Applications
CD74HC4067SM96 SSOP(24) 8.20mm × 7.40mm
• Energy infrastructure CD74HCT4067M SOIC(24) 15.4mm × 10.3mm
• Building automation CD74HC4067PW TSSOP(24) 7.8mm × 6.4mm
• Wireless infrastructure
CD74HCT4067PW TSSOP(24) 7.8mm × 6.4mm
• Appliances
• Data center & enterprise computing (1) For all available packages, see the orderable addendum at
• Retail automation & payment the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD74HC4067, CD74HCT4067
SCHS209D – NOVEMBER 1998 – REVISED DECEMBER 2024 www.ti.com

I0
9
10
S0
11
S1 P N
14
S2
13
S3

BINARY 14 - OUTPUT CIRCUITS

1 OF 16 1 COMMON
SAME AS ABOVE
DECODER INPUT/
(WITH ANALOG INPUTS)
SN = 5 STAGES OUTPUT
I1 TO I14
E = 4 STAGES

P N

16
15
E I15

Functional Block Diagram

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Table of Contents
1 Features............................................................................1 13 Analog Channel Specifications.................................. 11
2 Applications..................................................................... 1 14 Typical Characteristics............................................... 12
3 Description.......................................................................1 15 Analog Test Circuits....................................................13
4 Pin Configuration and Functions...................................4 16 Device and Documentation Support..........................14
4.1 Device Functional Modes............................................5 16.1 Related Documentation.......................................... 14
5 Absolute Maximum Ratings........................................... 5 16.2 Receiving Notification of Documentation Updates..14
6 Thermal Information........................................................6 16.3 Support Resources................................................. 14
7 Recommended Operating Conditions........................... 6 16.4 Trademarks............................................................. 14
8 Electrical Characteristics: HC Devices..........................7 16.5 Electrostatic Discharge Caution..............................14
9 Electrical Characteristics: HCT Devices....................... 8 16.6 Glossary..................................................................14
10 HTC Input Loading........................................................ 8 17 Revision History.......................................................... 14
11 Switching Characteristics HC.......................................9 18 Mechanical, Packaging, and Orderable
12 Switching Characteristics HCT.................................. 10 Information.................................................................... 14

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4 Pin Configuration and Functions

COMMON
INPUT/OUTPUT 1 24 VCC
I7 2 23 I8
I6 3 22 I9
I5 4 21 I10
I4 5 20 I11
I3 6 19 I12
I2 7 18 I13
I1 8 17 I14
I0 9 16 I15
S0 10 15 E
S1 11 14 S2
GND 12 13 S3

Figure 4-1. N, DW, or DB Packages 24-Pin PDIP, SOIC, or SSOP (Top View)

PIN
TYPE(1) DESCRIPTION
NAME NO.
COMMON
INPUT/ 1 IO Common input or output.
OUTPUT
I7 2 IO Switch input/output
I6 3 IO Switch input/output
I5 4 IO Switch input/output
I4 5 IO Switch input/output
I3 6 IO Switch input/output
I2 7 IO Switch input/output
I1 8 IO Switch input/output
I0 9 IO Switch input/output
S0 10 I Select/Address pin
S1 11 I Select/Address pin
GND 12 P Ground pin
S3 13 I Select/Address pin
S2 14 I Select/Address pin
E 15 I Enable for all switches ON/OFF
I15 16 IO Switch input/output
I14 17 IO Switch input/output
I13 18 IO Switch input/output
I12 19 IO Switch input/output
I11 20 IO Switch input/output
I10 21 IO Switch input/output
I9 22 IO Switch input/output
I8 23 IO Switch input/output
VCC 24 P Power pin

(1) I = input, O = output, P = Power

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4.1 Device Functional Modes

Table 4-1. Truth Table
SELECTED
S0 S1 S2 S3 E
CHANNEL
X X X X 1 None
0 0 0 0 0 0
1 0 0 0 0 1
0 1 0 0 0 2
1 1 0 0 0 3
0 0 1 0 0 4
1 0 1 0 0 5
0 1 1 0 0 6
1 1 1 0 0 7
0 0 0 1 0 8
1 0 0 1 0 9
0 1 0 1 0 10
1 1 0 1 0 11
0 0 1 1 0 12
1 0 1 1 0 13
0 1 1 1 0 14
1 1 1 1 0 15

5 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
VCC HC -0.5 7 V
DC Supply voltage
VCC HCT –0.5 7 V
IIK DC input diode current For VI < -0.5V or VI > VCC + 0.5V –20 20 mA
For VO < -0.5V or VO > VCC +
IOK DC output diode current –20 20 mA
-0.5V
ICC DC VCC or ground current –50 50 mA
DC Output
Source or Sink
For VO > -0.5V or VO < VCC + -0.5V –25 25 mA
Current per
Output Pin, IO
TJMAX Maximum junction temperature (Plastic Package) 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to ground, unless otherwise specified.

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6 Thermal Information
CD74HCx4067
THERMAL METRIC (1) E (PDIP) M (SOIC) SM (SSOP) PW (TSSOP) UNIT
24 PINS 24 PINS 24 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 67 84.8 96.2 97.4 °C/W
Junction-to-case (top) thermal
RθJC(top) N/A 57.0 60.0 45.0 °C/W
resistance
RθJB Junction-to-board thermal resistance N/A 59.5 65.1 62.7 °C/W
Junction-to-top characterization
ΨJT N/A 29.0 21.1 5.20 °C/W
parameter
Junction-to-board characterization
ΨJB N/A 59.0 64.4 62.1 °C/W
parameter

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7 Recommended Operating Conditions

MIN NOM MAX UNIT
CD54 and 74HC
2 6 V
Supply voltage range (TA = full package temperature types
VCC
range)(2) CD54 and 74HCT
4.5 5.5
types
VIS Analog switch I/O voltage 0 VCC V
TA Ambient temperature –55 125 °C
2V 0 1000
tr , tf Input rise and fall times 4.5 V 0 500 ns
6V 0 400

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8 Electrical Characteristics: HC Devices

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Switch
VIS (V) VI (V) VCC (V) TA
25°C 1.5
2 –40°C to +85°C 1.5
–55°C to +125°C 1.5
25°C 3.15
High Level Input Voltage VIH 4.5 –40°C to +85°C 3.15 V
–55°C to +125°C 3.15
25°C 4.2
6 –40°C to +85°C 4.2
–55°C to +125°C 4.2
25°C 0.5
2 –40°C to +85°C 0.5
–55°C to +125°C 0.5
25°C 1.35
Low Level Input Voltage VIL 4.5 –40°C to +85°C 1.35 V
–55°C to +125°C 1.35
25°C 1.8
6 –40°C to +85°C 1.8
–55°C to +125°C 1.8
25°C 70 160
4.5 –40°C to +85°C 200
–55°C to +125°C 240
VCC or GND VCC or GND Ω
25°C 60 140
6 –40°C to +85°C 175
–55°C to +125°C 210
"ON" Resistance IO = 1mA RON
25°C 90 180
4.5 –40°C to +85°C 225
–55°C to +125°C 270
VCC to GND VCC to GND Ω
25°C 80 160
6 –40°C to +85°C 200
–55°C to +125°C 240

"ON" Resistance Between Any Two 4.5 10

ΔRON 25°C Ω
Switches 6 8.5
25°C ±0.8
Off-Switch Leakage Current IZ E = VCC VCC or GND 6 –55°C to 85°C ±8 µA
–55°C to 125°C ±8
25°C ±0.1
VCC or
Input Leakage Current (Any Control) IIL 6 –55°C to 85°C ±1 µA
GND(1)
–55°C to 125°C ±1

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Over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
25°C 8
Quiescent Device Current
ICC VCC or GND 6 –55°C to 85°C 80 µA
–55°C to 125°C 160

(1) Any voltage between VCC and GND.

9 Electrical Characteristics: HCT Devices

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Switch
VIS (V) VI (V) VCC (V) TA
25°C 2
High Level Input Voltage VIH –40°C to +85°C 2 V
–55°C to +125°C 2
4.5
25°C 0.8
Low Level Input Voltage VIL –40°C to +85°C 0.8 V
–55°C to +125°C 0.8
25°C 70 160
VCC or GND VCC or GND –40°C to +85°C 200 Ω
–55°C to +125°C 240
"ON" Resistance IO = 1mA RON 4.5
25°C 90 180
VCC to GND VCC to GND –40°C to +85°C 225 Ω
–55°C to +125°C 270
"ON" Resistance Between Any Two
ΔRON 4.5 25°C 10 Ω
Switches
25°C ±0.8
Off-Switch Leakage Current IZ E = VCC VCC or GND 5.5 –55°C to 85°C ±8 µA
–55°C to 125°C ±8
25°C ±0.1
Input Leakage Current (Any Control) IIL VCC or GND 5.5 –55°C to 85°C ±1 µA
–55°C to 125°C ±1
25°C 8
Quiescent Device Current
ICC VCC or GND 5.5 –55°C to 85°C 80
–55°C to 125°C 160
µA
25°C 100 360
Additional Quiescent Device Current
▲ICC
Per Input Pin: 1 Unit Load (1) VCC - 2.1 4.5 to 5.5 –55°C to 85°C 450
–55°C to 125°C 490

(1) For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA

10 HTC Input Loading

over operating free-air temperature range (unless otherwise noted)
INPUT UNIT LOAD(1)
S0 – S3 0.5
E 0.3

(1) Unit Load is the ΔICC limit specified in Section 9 (for example, 360-µA max at 25°C.

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11 Switching Characteristics HC
over operating free-air temperature range (unless otherwise noted)
Parameter Test Conditions CL (pF) MIN NOM MAX UNIT
VCC (V) TA
25°C 75
2
-40°C to 85°C 95
-55°C to 125°C 110
Propagati 25°C 15
on Delay 4.5 -40°C to 85°C 50 19
Time tPHL, tPLH ns
Switch In -55°C to 125°C 22
to Out 25°C 13
6 -40°C to 85°C 16
-55°C to 125°C 19
5 25°C 15 6
25°C 275
2 -40°C to 85°C 345
-55°C to 125°C 415
25°C 55
Switch 4.5 -40°C to 85°C 50 69
Turn On E tPZH, tPZL ns
to Out -55°C to 125°C 83
25°C 47
6 -40°C to 85°C 59
-55°C to 125°C 71
5 25°C 15 23
25°C 300
2 -40°C to 85°C 375
-55°C to 125°C 450
25°C 60
Switch 4.5 -40°C to 85°C 50 75
Turn On tPZH, tPZL ns
Sn to Out -55°C to 125°C 90
25°C 51
6 -40°C to 85°C 64
-55°C to 125°C 76
5 25°C 15 25
25°C 275
2 -40°C to 85°C 345
-55°C to 125°C 415
25°C 55
Switch 4.5 -40°C to 85°C 50 69
Turn Off ! tPHZ, tPLZ ns
E to Out -55°C to 125°C 83
25°C 47
6 -40°C to 85°C 59
-55°C to 125°C 71
5 25°C 15 23

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over operating free-air temperature range (unless otherwise noted)

Parameter Test Conditions CL (pF) MIN NOM MAX UNIT
25°C 290
2 -40°C to 85°C 365
-55°C to 125°C 435
25°C 58
Switch 4.5 -40°C to 85°C 50 73
Turn Off tPHZ, tPLZ ns
Sn to Out -55°C to 125°C 87
25°C 49
6 -40°C to 85°C 62
-55°C to 125°C 74
5 25°C 15 21
Input 25°C 10
(Control)
C -40°C to 85°C 10
Capacitan I
ce -55°C to 125°C 10
CPD pF
Power
dissipatio
CPD 5 25°C 93
n
capacitan
ce(1)

12 Switching Characteristics HCT

over operating free-air temperature range (unless otherwise noted)
Parameter Test Conditions CL (pF) MIN NOM MAX UNIT
VCC (V) TA
Propagati 25°C 15
on Delay 4.5 -40°C to 85°C 50 19
Time tPHL, tPLH ns
Switch In -55°C to 125°C 22
to Out 5 25°C 15 6
25°C 60
Switch 4.5 -40°C to 85°C 50 75
Turn On E tPZH, tPZL ns
to Out -55°C to 125°C 90
5 25°C 15 25
25°C 60
Switch 4.5 -40°C to 85°C 50 75
Turn On tPZH, tPZL ns
Sn to Out -55°C to 125°C 90
5 25°C 15 25
25°C 55
Switch 4.5 -40°C to 85°C 50 69
Turn Off ! tPHZ, tPLZ ns
E to Out -55°C to 125°C 83
5 25°C 15 23
25°C 58
Switch 4.5 -40°C to 85°C 50 73
Turn Off tPHZ, tPLZ ns
Sn to Out -55°C to 125°C 87
5 25°C 15 21

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over operating free-air temperature range (unless otherwise noted)

Parameter Test Conditions CL (pF) MIN NOM MAX UNIT
Input 25°C 10
(Control)
C -40°C to 85°C 10
Capacitan I
ce -55°C to 125°C 10
CPD pF
Power
dissipatio
CPD 5 25°C 96
n
capacitan
ce(1)

13 Analog Channel Specifications

over operating free-air temperature range (unless otherwise noted)
Parameter Test Conditions VCC (V) HC HCT UNIT
Switch Frequency Response Bandwidth at -3dB 4.5 89 89 MHz
1kHz, VIS=
Total Harmonic Distortion 4.5 0.051 0.051 %
4VPP
Switch "OFF" signal feedthrough 4.5 -75 -75 dB
CI
5 5 pF
Switch input capacitance
CCOM
50 50 pF
Common Capacitance

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14 Typical Characteristics
140 0

-1
120
-2
“ON” RESISTANCE, R ON (Ω)

100
-3

UNITS (dB)
80 -4

-5
60
-6

40 VCC = 4.5V -7

-8
20
-9
0 -10
0 1 2 3 4 5 6 7 8 9 10 104 105 106 107 108
INPUT SIGNAL VOLTAGE, VIS (V) FREQUENCY, f (Hz)
TA = 25°C GND = 0 V VCC = 4.5 V RL = 50 Ω TA = 25°C
Figure 14-1. Typical ON Resistance vs Input Signal Voltage Figure 14-2. Typical Switch Frequency Response
0
SWITCH-OFF SIGNAL FEEDTHROUGH (dB)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100
104 105 106 107 108
FREQUENCY, f (Hz)
VCC = 4.5 V RL = 50 Ω TA = 25°C
Figure 14-3. Typical Switch-Off Signal Feedthrough vs Frequency

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15 Analog Test Circuits

Figure 15-2. Sine Wave Distortion Test Circuit

Figure 15-1. Frequency Response Test Circuit

Figure 15-3. Control-to-Switch Feedthrough Noise Figure 15-4. Switch Off Signal Feedthrough Test
Test Circuit Circuit
tr = 6ns tf = 6ns tr = 6ns tf = 6ns
VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

t THL t TLH t THL t TLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
t PHL t PLH t PHL t PLH

Figure 15-5. HC Transition Times and Propagation Figure 15-6. HCT Transition Times and Propagation
Delay Times, Combination Logic Delay Times, Combination Logic

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16 Device and Documentation Support

16.1 Related Documentation
• Texas Instruments, High-Speed CMOS Logic 16-Channel Analog Multiplexer/Demultiplexer
16.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
16.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
16.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
16.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

16.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

17 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2003) to Revision D (December 2024) Page
• Updated Applications, Pin Configuration and Functions section, ESD Ratings table, Thermal Information
table, Detailed Description section, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and
Orderable Information section............................................................................................................................ 1

18 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD74HC4067M96 ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC4067M Samples

CD74HC4067SM96 ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HP4067 Samples

CD74HC4067SM96E4 ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HP4067 Samples

CD74HC4067SM96G4 ACTIVE SSOP DB 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HP4067 Samples

CD74HCT4067M ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4067M Samples

CD74HCT4067ME4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4067M Samples

CD74HCT4067MG4 ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT4067M Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD74HCT4067 :

• Automotive : CD74HCT4067-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC4067M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1
CD74HC4067SM96 SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC4067M96 SOIC DW 24 2000 350.0 350.0 43.0
CD74HC4067SM96 SSOP DB 24 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HCT4067M DW SOIC 24 25 506.98 12.7 4826 6.6
CD74HCT4067ME4 DW SOIC 24 25 506.98 12.7 4826 6.6
CD74HCT4067MG4 DW SOIC 24 25 506.98 12.7 4826 6.6

Pack Materials-Page 3
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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