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Design of Five-Level Cascaded H-Bridge Multilevel Inverter

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DOI: 10.1007/978-981-15-2256-7_7

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Design of Five-Level Cascaded H-Bridge
Multilevel Inverter

S. Swathy, N. Niveditha and K. S. Chandragupta Mauryan

Abstract The abstract of this paper is to design a five-level cascaded H-bridge

multilevel inverter using phase disposition pulse width modulation (PD-PWM)
technique, to obtain optimal switching angles for harmonic reduction and to
compare the THD content of the output waveform of the five-level cascaded
H-bridge multilevel inverter for different modulation index by using mathematical
approach and MATLAB/SIMULINK.

Keywords Multilevel inverter Modulation techniques
Selective harmonic


elimination Total harmonic distortion FPGA

1 Introduction

Demand for energy is getting increased day by day. The key source of energy
available now is from non-renewable sources like fossil fuels. The over utilization
of these sources to meet our daily requirements have put it in a degradation state [1,
2]. Hence, there is a rapid development in the research to produce energy from
alternate sources, such as wind, solar, tidal, etc. Among them, energy taken from
photovoltaic systems plays an important role. The energy which is taken from a
photovoltaic system (PV system) is DC in nature. Most of the equipments are used
for domestic and industrial purposes which work on an AC source, the DC output
from a PV system is converted into an AC and for this purpose, power inverters
play a major role.

S. Swathy (&)
N. Niveditha

Department of Electrical and Electronics Engineering, Karpagam College of Engineering,
Coimbatore, Tamil Nadu, India
K. S. Chandragupta Mauryan
Department of Electrical and Electronics Engineering, Guru Nanak Institution Technical
Campus, Hyderabad, Telangana, India

© Springer Nature Singapore Pte Ltd. 2020 65

H. S. Saini et al. (eds.), Innovations in Electrical and Electronics Engineering,
Lecture Notes in Electrical Engineering 626,
https://doi.org/10.1007/978-981-15-2256-7_7
66 S. Swathy et al.

2 Multilevel Inverter Concepts

Multilevel inverters concept attracts academia as well as industry over wide range.
They combine switched waveforms with lower levels of harmonic distortion than
an equivalently rated two-level converter [1–3]. It found that with the increase in
level, the steps increases and the output waveform approaches to a near sinusoidal
waveform. Thus, it reduces the THD with a disadvantage of complex control and
voltage imbalance problem. They are employed mainly for high-power,
high-voltage/medium-power applications. They create more switching states,
thereby stepping up output inverter voltages in small increments. These smaller
voltage steps help in creating high-quality waveforms, lower dv/dt and reduced
electromagnetic compatibility. But in order to increase the number of levels, more
number of components are required and same will make the circuit complex [2].
High switching frequency employed in multilevel inverters helps in minimizing the
output harmonics and reducing the passive component size in the power circuit.
Figure 1 shows different number of voltage-level output waveform of MLI.
There are also different topologies of multilevel inverters that generate a stepped
output voltage waveform and that are suitable for different applications. By
designing multilevel circuits in different ways, many topologies with properties
have been developed. The basic multilevel inverter topologies include:
Diode-clamped multilevel inverter, capacitor-clamped multilevel inverter, cascaded
H-bridge (CHB) multilevel inverter.

2.1 Cascaded H-Bridge Multilevel Inverter (CHB-MLI)

The concept of multilevel inverter is based on connecting H-bridge inverters in

series to get a sinusoidal voltage output. Figure 2 shows a full-bridge inverter. One
full-bridge is itself a three-level cascaded H-bridge multilevel inverter and every
module added in cascade which extends the inverter with two voltage levels. Each
full-bridge inverter can create three voltages VDC, 0 and −VDC. To change one level
of voltage cascaded H-bridge multilevel inverter turns one switch ON and other
switch OFF in one full-bridge inverter. For example, to achieve voltage +Vdc,

Fig. 1 3, 5, 7 level output waveform of multilevel inverter at fundamental frequency

Design of Five-Level Cascaded H-Bridge Multilevel Inverter 67

switches S1 and S2 are turned ON, for −Vdc, the switches S3 and S4 are turned OFF.
When there is no current following through the full-bridge, then 0 voltage level is
achieved [3, 4].
The output voltage in each bridge is the summation of the voltage that is gen-
erated by each cell. The number of output voltage levels are 2n + 1, where n is the
number of cells. The cascaded H-bridge multilevel inverter is capable of producing
the total voltage source magnitude in both positive and negative half cycles, while
many other topologies can only produce half the total DC-bus voltage source
magnitude. Full-bridge inverter that is connected in series can contribute with the
same voltage, thus meets topology. There is possibility to charge every module in a
cascaded H-bridge multilevel inverter with different voltages.
In Fig. 3, there are two full-bridge inverters connected in series for obtaining five
different output voltage levels, −2VDC, VDC, 0 −VDC and +2Vdc. The advantages of
this type of multilevel inverter are that it needs less number of components com-
parative to the diode clamped or the flying capacitor. However, the number of
sources is higher, for the phase-leg to be able to create a number if m voltage level
and switches 2 * (m − 1) [1, 2, 4].

3 Modulation Techniques for Multilevel Inverter

Multilevel inverters have different modulation techniques for obtaining a better

output voltage response with minimum harmonic distortions. There are basically
two groups of methods: modulation with fundamental switching frequency or high
switching frequency pulse width modulation (PWM) [5–11].

3.1 Pulse Width Modulation Techniques

A multilevel pulse width modulation method uses high switching frequency carrier
waves in comparison to the reference waves to generate a sinusoidal output wave as

Fig. 2 Single-phase
full-bridge inverter
68 S. Swathy et al.

Fig. 3 Single-phase
five-level multilevel inverter

such in the two-level PWM case. To reduce harmonic distortions in the output
voltage waveform, phase-shifting techniques are used [12–20].
The carrier-based pulse width modulation techniques can be broadly classified
into:
• Phase-shifted modulation
• Level-shifted modulation.
In both modulation techniques, for an m-level inverter, (m-1) triangular carrier
waves are required and all the carrier waves should have the same frequency and
same peak-to-peak magnitude.
Phase Disposition Pulse Width Modulation: In phase disposition modulation
technique, all the triangular carriers are in phase and are arranged one over the other
as shown in Fig. 4. These arranged triangular carriers are compared with reference
wave to obtain the pulses for the multilevel inverter switches. This technique is
generally accepted as the method that creates the lowest harmonic distortion in
line-to-line voltage.
Design of Five-Level Cascaded H-Bridge Multilevel Inverter 69

Fig. 4 Reference and carrier wave for a five-level cascaded H-bridge multilevel inverter with
PD-PWM

4 Operating Modes of Five-Level Cascaded H-Bridge

Multilevel Inverter

Mode1: +2Vdc: Figure 5 shows the operating mode for getting output voltage of
+2Vdc. In this mode, switches SW1, SW2, SW5 and SW6 are ON and all the other
switches SW3, SW4, SW7 and SW8 are OFF.
Mode2: +Vdc: Figure 6 shows the operating mode for getting output voltage of
+Vdc. In this mode, switches SW1, SW2, SW8 and SW6 are ON and all the other
switches SW3, SW4, SW7 and SW5 are OFF.
Mode3: 0: Figure 7 shows the operating mode for getting output voltage of zero.
The lower-leg switches are triggered; hence, there will no flow of current in the
power circuit.

Fig. 5 Operating mode for

getting output voltage of
+2Vdc
70 S. Swathy et al.

Fig. 6 Operating mode for

getting output voltage of +Vdc

Fig. 7 Operating mode for

getting output voltage of zero

Mode4: −Vdc: Figure 8 shows the operating mode for getting output voltage of
−Vdc. In this mode, switches SW3, SW4, SW8 and SW6 are ON and all the other
switches SW1, SW2, SW7 and SW5 are OFF. The flow of current is opposite to the
load current.
Design of Five-Level Cascaded H-Bridge Multilevel Inverter 71

Fig. 8 Operating mode for

getting output voltage of −Vdc

Mode5: -2Vdc: Figure 9 shows the operating mode for getting output voltage of
−2Vdc. In this mode, switches SW3, SW4, SW8 and SW7 are ON and all the other
switches SW1, SW2, SW6 and SW5 are OFF. The flow of current is opposite to the
load current.

Fig. 9 Operating mode for

getting output voltage of
−2Vdc
72 S. Swathy et al.

5 Fourier Analysis of PD-PWM Technique

The concept of a two-level pulse width modulated converter system is that a

low-frequency reference waveform is compared against a high-frequency carrier
waveform and the compared output is used to control the switches. The conse-
quence of switching process has fundamental component, the reference waveform
and also incorporates a series unwanted harmonics. Determination of harmonic
frequency components is complex and it is often done by fast Fourier transform
analysis of a simulated time-varying waveform. This approach also reduces
mathematical effort but uncertainly, it leaves error. In contrast, an analytical solu-
tion which exactly identifies the harmonic component of a PWM waveform ensures
that precisely the harmonics are being considered when various PWM strategies are
compared against each other [21–27]. Table 1 gives the switching function con-
dition of a five-level multilevel inverter.

Aoo X 1
f ðt Þ ¼ þ ½Aon cosð½nxo tÞ þ Bon sinð½nxo tÞ
2 n¼1
X
1
þ ½Amo cosð½nxc tÞ þ Bmo sinð½mxc tÞ
m¼1
1 X
X 1
þ ½Amn cosð½mxc t þ nxo tÞ
m¼1 n¼1
n6¼0

þ Bmn sinð½nxc t þ nxo tÞ

m carrier index variable

n base-band index variable.
The final expression for harmonic components can be obtained by on substi-
tuting the equation

Table 1 Switching function condition of a five-level multilevel inverter

F(x, y) When p  x  0 When 0\x  p
p p
+2VDC M cos y [ 12  2p M cos y [ 1
2 2pþ
p p p p
+VDC  2p \M cos y\ 12  2p 2p \M cos y\ 2 þ 2p
1

p p p p
0  12  2p \M cos y\  2p  2 þ 2p \M cos y\ 2p
1

−VDC p
1  2p p
\M cos y\  12  2p p
1 þ 2p \M cos y\  12 þ p
2p
p p
−2VDC M cos y\  1  2p M cos y\  1 þ 2p
Design of Five-Level Cascaded H-Bridge Multilevel Inverter 73

8Vdc X
1
1 X 1
1
Vaz ðtÞ ¼ 2MVdc cos x0 t þ J2k1 ð½2m  12pM Þ
p m¼1 2m  1 k¼1 2k  1
2

 f1 þ 2 sinð½2k  1u cos kpg  cosð½2m  1xc tÞ

2Vdc X
1
1 X 1
þ J2n þ 1 ð4mpM Þ cos np cosð2mxc t þ ½2n þ 1x0 tÞ
p m¼1 2m n¼1
4Vdc X
1
1 X1 X 1
þ ½J2k1 ð½2m  12pM Þ cos kp
p2 m¼1 2m  1 n¼1 k¼1
n6¼0
 
cosð½n  k pÞ þ 2 sinð½2k  1  2nuÞ cosð½n  k pÞ þ 2 sinð½2k  1 þ 2nuÞ
 þ
½2k  1  2n ½2k  1 þ 2n
 cosð½2m  1xc t þ 2nx0 tÞ

6 Simulation Results of Cascaded H-Bridge Multilevel

Inverter Using PD-PWM Technique

The simulation is carried out using MATLAB/SIMULINK software. The simula-

tion diagram is shown in Fig. 10.
Table 2 gives the design parameters for cascaded H-bridge multilevel inverter.
Figure 11 shows the output voltage and output current of five-level cascaded
H-bridge multilevel inverter for switching frequency of 2 kHz M = 1 and Fig. 12

Fig. 10 Simulation diagram of cascaded H-bridge multilevel inverter using PD-PWM technique
74 S. Swathy et al.

Table 2 Design parameters for cascaded H-bridge multilevel inverter

S. No. Parameter Five-level cascaded H-bridge inverter
1 Input voltage 130 V
2 Load R = 50 Ω
3 Switching frequency 1 and 2 kHz
4 Modulation index 0.8 and 1

Fig. 11 a Output voltage and b Output current of five-level cascaded H-bridge multilevel inverter
for switching frequency of 2 kHz M = 1

shows the harmonic spectrum of output current of five-level cascaded H-bridge

multilevel inverter for the switching frequency of 2kH and modulation index,
M = 0.8 and M = 1.
Comparison of THD values for modulation index 0.8 and 1 and switching
frequencies of 1 kHz and 2 kHz are given in Table 3. Also the Comparison of THD
for PDPWM and SHE technique is for 0.8 and 1 modulation index and 1 and 2 kHz
switching frequencies is given in Table 4.
Design of Five-Level Cascaded H-Bridge Multilevel Inverter 75

Fig. 12 Harmonic spectrum of output current of five-level cascaded H-bridge multilevel inverter
(2 kHz) a M = 0.8 b M = 1

Table 3 Comparison of THD for various modulation index and switching frequencies
Parameter Switching frequency Switching frequency
(1 kHz) (2 kHz)
Modulation index Modulation Index
0.8 1 0.8 1
Voltage (%THD) 38.07 26.64 36.74 23.02
Current (%THD) 38.07 26.64 36.74 23.02

Table 4 Comparison of THD for PD-PWM and SHE techniques

Total harmonic PD-PWM SHE
elimination Third harmonic Fifth harmonic Seventh harmonic
elimination elimination elimination
%THD for 26.64 18.54 23.38 22.59
voltage
%THD for 26.64 18.54 23.38 22.59
current
76 S. Swathy et al.

7 Hardware Implementation

FPGA Kit
The control signal for the power switches of a five-level cascaded H-bridge mul-
tilevel inverter is developed with the help of SPARTAN 6-XC6SLX25 trainer kit.
Figure 13 shows the schematic of SPARTAN 6 FPGA kit.
Design specification for hardware implementation of a five-level cascaded H-bridge
multilevel inverter is given in Table 5. Output voltage and output current for
switching frequency of 1 kHz and modulation index of 0.8 are shown in Fig. 14a
and b. Also the FFT of output voltage and current for switching frequency of 1 kHz
and modulation index of 0.8 is shown in Fig. 15a, b.
The harmonic spectrum with R-Load for switching frequency of 1 kHz and
modulation index of 0.8 is shown in Fig. 16 for output voltage, current and power.
The comparison of different modulation indices and switching frequency is given in
Table 6.

Fig. 13 SPARTAN 6-FPGA

kit

Table 5 Design specification for hardware implementation of a five-level cascaded H-bridge

multilevel inverter
S. No. Parameters Specification
1 Input voltage 130 V
2 Load 50 Ω
3 Switching frequency (fs) 1 and 2 kHz
4 Voltage and current measurement Digital storage oscilloscope
5 Harmonic measurement Fluke 43B
Design of Five-Level Cascaded H-Bridge Multilevel Inverter 77

Fig. 14 a Output voltage and b Output current of five-level cascaded H-bridge multilevel inverter

8 Conclusion

In this work, a single-phase five-level cascaded H-bridge multilevel inverter is

studied and analyzed in terms of output voltage, output current and harmonic
spectrum. Phase disposition PWM modulation technique is used to generate
78 S. Swathy et al.

Fig. 15 FFT of a Output voltage and b Output current

switching pulses for the inverter. Further, optimal switching angles for the inverter
are calculated for harmonic reduction (third harmonic, fifth harmonic and seventh
harmonic). Results are verified using simulation done in MATLAB/SIMULINK.
The five-level cascaded H-bridge multilevel inverter is implemented as a hardware
prototype. The pulses for cascaded H-bridge multilevel inverter are generated using
Spartan-6 XC6SLX25 FPGA kit. A comparison of the output THD with
Design of Five-Level Cascaded H-Bridge Multilevel Inverter 79

Fig. 16 Harmonic spectrum of a Output voltage, b Output current and c Power

Table 6 Comparison of different modulation indices and switching frequency

Parameters Switching frequency Switching frequency
(1 kHz) (2 kHz)
Modulation index Modulation index
0.8 1 0.8 1
Voltage (%THD) 36.5 26.5 33.2 21.1
Current (%THD) 36.5 26.5 32.9 21.2
Power (W) 89 144 93 134

modulation index of 0.8 and 1, and switching frequencies 1 and 2 kHz is carried
out. As a future scope, multilevel inverter can be analyzed for different output levels
by changing modulation index and switching frequency. By designing suitable
filters, the total harmonic distortion can further be reduced on the output, to meet
IEEE harmonic standards.

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