CD74HC138, CD74HCT138,

Data sheet acquired from Harris Semiconductor

CD74HC238, CD74HCT238
SCHS147A
High Speed CMOS Logic 3-to-8 Line Decoder/
October 1997 - Revised February 1999 Demultiplexer Inverting and Non-Inverting

Features
• Select One Of Eight Data Outputs
Active Low for 138, Active High for 238
[ /Title • l/O Port or Memory Selector
(CD74
• Three Enable Inputs to Simplify Cascading
HC138
, • Typical Propagation Delay of 13ns at VCC = 5V,
CL = 15pF, TA = 25oC
CD74
HCT13 • Fanout (Over Temperature Range)
8, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

HC238 • Wide Operating Temperature Range . . . -55oC to 125oC

, • Balanced Propagation Delay and Transition Times
CD74 • Significant Power Reduction Compared to LSTTL
HCT23 Logic ICs
8) • HC Types
/Sub- - 2V to 6V Operation
ject - High Noise Immunity: NIL = 30%, NIH = 30% of VCC
(High at VCC = 5V
Speed • HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

Pinout
CD74HC138, CD74HCT138, CD74HC238, CD74HCT238
(PDIP, SOIC)
TOP VIEW

A0 1 16 VCC

A1 2 15 Y0 (Y0)

A2 3 14 Y1 (Y1)

E1 4 13 Y2 (Y2)

E2 5 12 Y3 (Y3)
E3 6 11 Y4 (Y4)

(Y7) Y7 7 10 Y5 (Y5)

GND 8 9 Y6 (Y6)

Signal names in parentheses are for ’HC238 and ’HCT238.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 1999, Texas Instruments Incorporated
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 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

Description Ordering Information

The Harris CD74HC138, CD74HC238 and CD74HCT138, PKG.
CD74HCT238 are high speed silicon gate CMOS decoders PART NUMBER TEMP. RANGE (oC) PACKAGE NO.
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption CD74HCT138E -55 to 125 16 Ld PDIP E16.3
usually associated with CMOS circuitry, yet have speeds
CD74HC238E -55 to 125 16 Ld PDIP E16.3
comparable to low power Schottky TTL logic. Both circuits
have three binary select inputs (A0, A1 and A2). If the device CD74HCT238E -55 to 125 16 Ld PDIP E16.3
is enabled, these inputs determine which one of the eight
normally high outputs of the HC/HCT138 series will go low CD74HC138M -55 to 125 16 Ld SOIC M16.15
or which of the normally low outputs of the HC/HCT238 CD74HCT138M -55 to 125 16 Ld SOIC M16.15
series will go high.
CD74HC238M -55 to 125 16 Ld SOIC M16.15
Two active low and one active high enables (E1, E2, and E3)
are provided to ease the cascading of decoders. The CD74HCT238M -55 to 125 16 Ld SOIC M16.15
decoder’s 8 outputs can drive 10 low power Schottky TTL
equivalent loads. CD74HC138SM -55 to 125 16 Ld SSOP M16.209

NOTES:
Ordering Information 1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
PKG.
PART NUMBER TEMP. RANGE (oC) PACKAGE NO. 2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
CD74HC138E -55 to 125 16 Ld PDIP E16.3 Harris customer service for ordering information.

Functional Diagram
HC/HCT HC/HCT
238 138
1 15
A0 Y0 Y0
2 14
A1 Y1 Y1
3 13
A2 Y2 Y2
12
Y3 Y3
4 11
E1 Y4 Y4
5 10
E2 Y5 Y5
6 9
E3 Y6 Y6
7
Y7 Y7

TRUTH TABLE CD74HC138, CD74HCT138

INPUTS
ENABLE ADDRESS OUTPUTS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H X X X H H H H H H H H
L X X X X X H H H H H H H H
X H X X X X H H H H H H H H
H L L L L L L H H H H H H H
H L L L L H H L H H H H H H
H L L L H L H H L H H H H H
H L L L H H H H H L H H H H

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 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

TRUTH TABLE CD74HC138, CD74HCT138

INPUTS
ENABLE ADDRESS OUTPUTS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H L L H L L H H H H L H H H
H L L H L H H H H H H L H H
H L L H H L H H H H H H L H
H L L H H H H H H H H H H L
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

TRUTH TABLE CD74HC238, CD74HCT238

INPUTS
ENABLE ADDRESS OUTPUTS
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H X X X L L L L L L L L
L X X X X X L L L L L L L L
X H X X X X L L L L L L L L
H L L L L L H L L L L L L L
H L L L L H L H L L L L L L
H L L L H L L L H L L L L L
H L L L H H L L L H L L L L
H L L H L L L L L L H L L L
H L L H L H L L L L L H L L
H L L H H L L L L L L L H L
H L L H H H L L L L L L L H
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

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 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3) θJA (oC/W)
DC Input Diode Current, IIK PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DC Output Diode Current, IOK SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
DC Output Source or Sink Current per Output Pin, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND

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 CD74HC138, CD74HCT138, CD74HC238, CD74HCT238

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and 0 5.5 - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per -2.1 5.5
Input Pin: 1 Unit Load
(Note 4)
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

A0-A2 1.5

E1, E2 1.25

E3 1

NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,

360µA max at 25oC.

Switching Specifications Input tr, tf = 6ns

-40oC TO
25oC 85oC -55oC TO 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF 2 - - 150 - 190 - 225 ns

Address to Output 4.5 - - 30 - 38 - 45 ns

CL = 15pF 5 - 13 - - - - - ns

CL = 50pF 6 - - 26 - 33 - 38 ns

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Switching Specifications Input tr, tf = 6ns (Continued)

-40oC TO
25oC 85oC -55oC TO 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

Enable to Output tPLH, tPHL CL = 50pF 2 - - 150 - 190 - 265 ns

HC/HCT138
4.5 - - 30 - 38 - 53 ns

6 - - 26 - 33 - 45 ns

Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns

(Figure 1)
4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Power Dissipation CPD CL = 15pF 5 - 67 - - - - - pF

Capacitance, (Notes 5, 6)

Input Capacitance CIN - - - - 10 - 10 - 10 pF

HCT TYPES
Propagation Delay
Address to Output tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns

CL = 15pF 5 - 14 - - - - - ns

Enable to Output tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns

HC/HCT138

Enable to Output tPLH, tPHL CL = 15pF 4.5 - - 40 - 50 - 60 ns

HC/HCT238

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns

(Figure 2)

Power Dissipation CPD CL = 15pF 5 - 67 - - - - - pF

Capacitance, (Notes 5, 6)

Input Capacitance CIN - - - - 10 - 10 - 10 pF

NOTES:
5. CPD is used to determine the dynamic power consumption, per gate.
6. PD = VCC2 fi (CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns
VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50%
INVERTING 10% INVERTING 1.3V
OUTPUT 10%
OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

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Copyright  1999, Texas Instruments Incorporated