8051 Architecture
8051 Architecture
23EC4103
Microcontrollers
2
Analyse
and CO1: Analyse and elucidate the internal
elucidat architecture of the8051 Microcontroller.
e
Course
Objectives Develop
CO3: Develop programs to configure and utilize
on-chip peripherals of 8051 microcontroller.
A microprocessor is a
programmable device that
performs arithmetic, logic,
control, and input/output
operations.
4
Evolution of Microprocessor
Fairchild Semiconductors,
founded in 1957, invented the first
IC in 1959.
In 1968, Robert Noyce, Gordan
Moore, Andrew Grove resigned
from Fairchild Semiconductors.
They founded their own company
Intel ( Integrated Electronics.
Intel grown from 3-man start-up in
1968
Evolution of Microprocessor 5
1971 1972 1974 1976
80486 – 32bit 80386 – 32 bit 80286 – 16 bit 80186 – 16bit 8086 – 16bit
32-bit processor
Pentium III – 1999
1993 1995 1997 Pentium IV – 2000
64-bit Processor
Intel Core 2 – 2006
Intel i3 – 2010
Intel i5 – 2009
Pentium – 32bit Pentium Pro Pentium II
Intel i7 - 2008
Microprocessor Based System 6
CPU
External RAM, ROM, I/O
(No internal RAM, ROM, I/O ports in the CPU)
7
Advantages:
Microprocessor Microcontroller
CPU is stand-alone, RAM, CPU, RAM, ROM, I/O and
ROM, I/O, timer are timer are all on a single
separate chip
Versatility Single-purpose
Systems
On Chip Full
Four 8 BIT I/O PORTS Two 16 Bit Duplex UART for
(32 I/O LINES) Timers/Counters Serial
Communication
16-bit program
16-bit Data Pointer 32 General
counter to access
to access external Purpose Registers
external Code
Data Memory each of 8 bits
Memory and
8051 Family 16
Pin
Diagram
Block Diagram of 8051 18
XTAL1 and XTAL2 19
22
PSEN’ and ALE 23
P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.
Pin Description Summary 25
PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
ALE O Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory.
PSEN* O Program Store Enable: The read strobe to external program
memory. When executing code from the external program
memory, PSEN* is activated twice each machine cycle,
except that two PSEN* activations are skipped during
each access to external data memory.
EA*/VPP I External Access Enable/Programming Supply Voltage: EA*
must be externally held low to enable the device to fetch
code from external program memory locations. If EA* Is
held high, the device executes from internal program
memory. This pin also receives the programming supply
voltage Vpp during Flash programming. (applies for 89c5x
MCU's)
General Block Diagram of 8051
26
CPU
Bus Serial
OSC 4 I/O Ports
Control Port
TXD RXD
P0 P1 P2 P3
27
Detailed Block Diagram 28
[PSW]
C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1