LV56851UV

Linear Voltage Regulator, Multiple-Output,

System Power Supply IC,
for Automotive Infotainment System

Overview www.onsemi.com
The LV56851UV is a multiple output linear voltage regulator IC, which allows
reduction of quiescent current. The LV56851UV is specifically designed to
address automotive infotainment systems power supply requirements.
The LV56851UV integrates 5 linear regulator outputs, 1 high side power switch,
I2C-bus communication, ACC detection, battery voltage detection, over-current
limiter, overvoltage protection and thermal shut down.

Features HZIP15
• Low consumption current: 60A (typ, VDD output is in operation)
• 5 regulator outputs
VDD for microcontroller: 3.3 V,Iomax: 300 mA
For system: 3.3/5 V, Iomax: 300 mA
For audio: 5/8.5/9/12 V, Iomax: 400 mA
For illumination: 8/9/10.5/12 V, Iomax: 300 mA
For CD: 5/6/7/8 V, Iomax: 1500 mA
• 1 high side switch
AMP: Imax: 500 mA, voltage difference between input and output: 0.75 V
• ACC detection circuit
Detection Voltage 2.7/3.2/3.6/4.2 V
• Battery voltage detection (BDET) : VCC2
Low voltage detection(UVDET): 6.5/7.5(hys=0.5 V or 1.5 V)/8 V
Over voltage detection(OVDET): detection voltage 18 V
• I2C-bus communication interface
Each output except VDD is independently enabled/disabled.
SYS/ILM/CD/AUDIO/ACC/UV voltage setting.
Read back supported: Output voltage setting, Output over-current,
Detections(ACC/UV/OVDET/OVP/TWARN)
• RESET ORDERING INFORMATION
Detection Voltage 2.8 V(typ, 0.85*VDD), N-MOS Open-Drain output
• Supply input Ordering Code:
LV56851UV-XH
VCC1: For internal reference voltage, control circuitry, VDD output.
VCC2: For AUDIO/ILM/CD/AMP/SYS Package
• Over-current protection HZIP15
• Overvoltage protection(OVP): VCC1,VCC2 Typ 21 V (Pb-Free / Halogen Free)
(All outputs except VDD are turned off) Shipping (Qty / packing)
• Thermal shutdown: Typ 175°C , Thermal Warning: Typ 140°C 720 / Tube
• Package : HZIP15
• AEC-Q100 (Grade 3) Qualified and PPAP capable

Typical Applications
• Automotive infotainment

* I2C Bus is a trademark of Philips Corporation.

© Semiconductor Components Industries, LLC, 2016 1 Publication Order Number:

April 2016- Rev. 0 LV56851UV/D
 LV56851UV

BLOCK DIAGRAM

VCC1
VDD
8 11
3.3 V, 0.3 A
OVP
VREF -
+

VREG 5.1 V
SYS
9
VREF 3.3 V/5 V, 0.3 A
VREF 1.25 V SYS_EN
-
+
TSD/
TWARN
VCC2 ILM
7 3
VREF 8/9/10.5/12 V, 0.3 A
OVP ILM_EN
-
+

2 GND

VDD 4
AUDIO
VDD
VREF 5/8.5/9/12 V, 0.4 A
RSTB RESET AUDIO_EN
-
+
13
FILT

VDD VDD

5
CD
SCL
VREF 5/6/7/8 V, 1.5 A
10
CD_EN
-
+
SDA I2C-bus
12
CTL
OVP AMP
TSD 1
UV VCC2-0.75 V, 0.5 A
OV
AMP_EN CTRL
OVP→All Output OFF
except VDD
ACC TSD→All Output OFF
UVDET VDD

ACCIN OVDET BDET

6 14
OVP
BDET
VDD
ACCDET
VREF 15

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 LV56851UV

PIN EQUIVALENT CIRCUITS

Pin # Pin name Function Equivalent circuit

7 VCC2

AMP output
1 AMP
VCC2-0.75 V 1

2
GND

2 GND GND

7
VCC2

3
ILM output

20.9~33.4kΩ 180kΩ
3 ILM
8 V~12 V

1kΩ

2 GND

7
VCC2

4
AUDIO output
180kΩ

4 AUDIO
5 V~12 V
20.9~60kΩ

1kΩ

2 GND

7
VCC2

5
CD output
180kΩ

5 CD
5 V~8 V
33.3~60kΩ

1kΩ

2 GND

Continued on next page

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 LV56851UV

Continued from preceding page

Pin # Pin name Function Equivalent circuit

90kΩ
6 ACCIN ACC detection input

36~78kΩ
GND
2

VCC2 VCC1
7 VCC2 Supply terminal 7 8

8 VCC1 Supply terminal

2 GND

7
VCC2

9
SYS output
9 SYS 230/420kΩ
3.3 V/5 V

1kΩ
140kΩ

2 GND

8 VCC1

11 VDD

10 SCL I2C-bus clock input 1kΩ

10

GND
2

Continued on next page

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 LV56851UV

Continued from preceding page

Pin # Pin name Function Equivalent circuit

8 VCC1

VDD output 11
11 VDD

230kΩ
3.3 V

140kΩ
2 GND

VDD
11

2 100Ω 1kΩ
12 SDA I C-bus data input
12

GND
2

VDD
11
RESET
13 RSTB 100Ω 1kΩ
13
Open-drain output

GND
2

11
VDD
14 BDET BDET output

100Ω
14
15

15 ACCDET ACCDET output

2 GND

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 LV56851UV

MAXIMUM RATINGS / Ta = 25C (Note 1)

Parameter Symbol Conditions Ratings Unit

Supply voltage Vcc max VCC1,VCC2 36 V

SDA,SCL,ACCDET,BDET,RSTB,SYS,VDD 7
Input voltage Vio max ILM,AUDIO,CD 14 V
ACCIN, AMP 36
-Independent IC 1.3
Allowable power Pd max
-Al heatsink (50 * 50 * 1.5 mm3) is used 5.3 W
dissipation Ta ≤ 25°C
-Size of heatsink: infinite 26
VCC1/VCC2/ACCIN
Peak supply voltage Vcc peak 50 V
• See the test waveform below
Operating ambient
Topr -40 to +85 °C
temperature
Storage temperature Tstg -55 to +150 °C
Junction temperature Tjmax +150 °C
1. Stresses exceeding those listed in the Absolute Maximum Rating table may damage the device. If any of these limits are exceeded,
device functionality should not be assumed, damage may occur and reliability may be affected.

• Waveform of surge test (VCC1,VCC2,ACCIN)

50V
90%

10%
16V
5msec 100ms

• Allowable power dissipation derating curve

HZIP15
(a) Independent IC
(b)Aluminum heat-sink (50×50×1.5 mm3)
Heat-sink tightening condition
tightening torque: 39 N•cm ,
with silicone grease

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 LV56851UV

RECOMMENDED OPERATING RANGES at Ta = 25C (Note 2)

■VCC1
Parameter Symbol Conditions Ratings Unit
Operating supply voltage1 VCCop1 VDD output 7 to 16 V
■VCC2
Parameter Symbol Conditions Ratings Unit
ILM(10.5 V) output 12.5 to 16
Operating supply voltage2 VCCop2 V
ILM(8 V) output 10 to 16
Operating supply voltage3 VCCop3 AUDIO(8.5 V) output 9.5 to 16 V
CD(8V) output(Io=1.5 A) 10.5 to 16
Operating supply voltage4 VCCop4 V
CD(8V) output(Io≤ 1 A) 10 to 16
Operating supply voltage5 VCCop5 AMP output 7.5 to 16 V

Operating supply voltage6 VCCop6 SYS output 7.5 to 16 V

2. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses
beyond the Recommended Operating Ranges limits may affect device reliability.

• “Maximum Rating” and “Recommended operating range”

VCC1 VCC2

Out-of-Rating
36 V
disabled(OVP)
21 V
20.5 V
operating1
16 V
14V
13V
12.5V
11V recommended
10V 10V 10V
9.5V operation
9V
8V range
7V 7.5V 7.5V 7.5V 7.5V
operating2(*)

drop out
region
Vo=12 V

Vo=12 V

Vo=8 V
Vo=9 V

Vo=8 V

Vo=8.5 V

Vo=5 V

Vo=7 V

Vo=6 V

Vo=5 V
Vo=10.5 V

Vo=9 V
Vo=3.3 V

Vo=5 V

VDD

SYS ILM AUDIO CD(Io≤1 A) AMP

(*) Each lower limit value is determined by “Output voltage”-“Dropout voltage”.

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 LV56851UV

ELECTRICAL CHARACTERISTICS at Ta  25C(Note 4), VCC1=VCC2=14.4 V unless otherwise noted. (Note 3)

Parameter Symbol Conditions Min Typ Max Unit
VDD w/out load, ACCIN=0V
Quiescent current Icc 2 60 100 μA
I C register Gr0/Gr1/Gr2=00h
VDD output (3.3 V)
Output voltage Vo1 Io1=200 mA 3.13 3.3 3.47 V
Output current Io1 Vo1≥ 3.1 V 300 mA
Line regulation ∆VoLN1 7.5 V<VCC1<16 V, Io1=200 mA 30 90 mV
Load regulation ∆VoLD1 1 mA<Io1<200 mA 70 150 mV
Dropout voltage VDROP1 Io1=200 mA 0.5 1.0 V
f=120 Hz, VCC1=0.5 Vpp
Ripple rejection (Note 5) RREJ1 40 50 dB
Io1=200 mA
RESET
Vrst0 VDD falling 2.7 2.8 2.94 V
Reset voltage
Vrst As a ratio of Vo1, VDD falling 85 %
Hysteresis voltage Vrshs As a ratio of Vo1 1.6 %
Detection Delay1 Td1 H to L, VDD=Vrst+0.4 V to Vrst-0.4 V 25 μsec
Detection Delay2 Td2 L to H, VDD=Vrst-0.4 V to Vrst+0.4 V 100 μsec
SYS output (3.3 V/5 V) ; SYS_EN=1
Output voltage 1 Vo21 Io2=200 mA, SYS_V=0 3.13 3.3 3.47 V
Output voltage 2 Vo22 Io2=200 mA, SYS_V=1 4.75 5.0 5.25 V
Output current Io2 Vo21≥3.1 V, Vo22≥4.7 V 300 mA
Line regulation ∆VoLN2 7.5 V<VCC2<16 V, Io2=200 mA 30 90 mV
Load regulation ∆VoLD2 1 mA<Io2<200 mA 70 150 mV
Dropout voltage VDROP2 Io2=200 mA 0.4 0.8 V
f=120 Hz, VCC2=0.5 Vpp
Ripple rejection (Note 5) RREJ2 40 50 dB
Io2=200 mA
ILM output (8-12 V); ILM_EN=1
Output voltage 1 Vo31 Io3=200 mA, ILM_V[1:0]=00 7.6 8.0 8.4 V
Output voltage 2 Vo32 Io3=200 mA, ILM_V[1:0]=01 8.55 9.0 9.45 V
Output voltage 3 Vo33 Io3=200 mA, ILM_V[1:0]=10 9.97 10.5 11.03 V
Output voltage 4 Vo34 Io3=200 mA, ILM_V[1:0]=11 11.4 12 12.6 V
Output current Io3 300 mA
Line regulation ∆VoLN3 Vo+2 V<VCC2<16 V, Io3=200 mA 30 90 mV
Load regulation ∆VoLD3 1 mA<Io3<200 mA 70 150 mV
Dropout voltage VDROP3 Io3=200 mA 0.6 1.05 V
Ripple rejection (Note 5) RREJ3 f=120 Hz ,Io3=200 mA 40 50 dB
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 LV56851UV

Continued from preceding page

Parameter Symbol Conditions Min Typ Max Unit

CD output (5-8 V); CD_EN=1
Output voltage 1 Vo41 Io4=1000 mA, CD_V[1:0]=00 4.75 5.0 5.25 V
Output voltage 2 Vo42 Io4=1000 mA, CD_V[1:0]=01 5.7 6.0 6.3 V
Output voltage 3 Vo43 Io4=1000 mA, CD_V[1:0]=10 6.65 7.0 7.35 V
Output voltage 4 Vo44 Io4=1000 mA, CD_V[1:0]=11 7.6 8.0 8.4 V
Output current Io4 Vo41≥4.7 V, V44≥7.6 V 1500 mA
Line regulation ∆VoLN4 Vo+2 V<Vcc2<16 V,Io4=1000 mA 50 100 mV
Load regulation ∆VoLD4 10 mA<Io4<1000 mA 100 200 mV
Dropout voltage 1 VDROP4 Io4=1000 mA 0.9 1.5 V
Dropout voltage 2 VDROP4’ Io4=500 mA 0.45 0.75 V
Ripple rejection
RREJ4 f=120 Hz ,Io4=1000 mA 40 50 dB
(Note 5)

AUDIO output (5-12 V); AUDIO_EN=1

Output voltage 1 Vo51 Io5=200 mA, AUD_V[1:0]=00 4.75 5.0 5.25 V
Output voltage 2 Vo52 Io5=200 mA, AUD_V[1:0]=01 8.13 8.5 8.87 V
Output voltage 3 Vo53 Io5=200 mA, AUD_V[1:0]=10 8.55 9.0 9.45 V
Output voltage 4 Vo54 Io5=200 mA, AUD_V[1:0]=11 11.4 12 12.6 V
Output current Io5 400 mA
Line regulation ∆VoLN5 Vo+1 V<VCC2<16 V,Io5=200 mA 30 90 mV
Load regulation ∆VoLD5 1 mA<Io5<200 mA 70 150 mV
Dropout voltage VDROP5 Io5=200 mA 0.3 0.6 V
Ripple rejection
RREJ5 f=120 Hz, Io5=200 mA 40 50 dB
(Note 5)

AMP HS-SW; AMP_EN=1

Output voltage Vo6 Io6=500 mA Vcc2-1.5 Vcc2-0.75 V
Output current Io6 Vo6≥VCC2-1.5 V 500 mA
ACC detection
Detection voltage 1 Vacc1 ACC_V[1:0]=00, ACCIN falling 2.62 2.7 2.78 V
Detection voltage 2 Vacc2 ACC_V[1:0]=01, ACCIN falling 3.1 3.2 3.3 V
Detection voltage 3 Vacc3 ACC_V[1:0]=10, ACCIN falling 3.49 3.6 3.71 V
Detection voltage 4 Vacc4 ACC_V[1:0]=11, ACCIN falling 4.07 4.2 4.33 V
Release voltage 1 Vaccr1 ACC_V[1:0]=00, ACCIN rising 2.81 2.9 2.99 V
Release voltage 2 Vaccr2 ACC_V[1:0]=01, ACCIN rising 3.3 3.4 3.5 V
Release voltage 3 Vaccr3 ACC_V[1:0]=10, ACCIN rising 3.68 3.8 3.92 V
Release voltage 4 Vaccr4 ACC_V[1:0]=11, ACCIN rising 4.26 4.4 4.54 V
Threshold hysteresis Vachs 0.2 V
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 LV56851UV

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Parameter Symbol Conditions Min Typ Max Unit
Under-Voltage detection(UVDET)
detection voltage 1 Vuv1 VCC2 falling, UVD_V[1:0]=00 6.3 6.5 6.7 V
detection voltage 2 Vuv2 VCC2 falling, UVD_V[1:0]=01 7.27 7.5 7.73 V
detection voltage 3 Vuv3 VCC2 falling, UVD_V[1:0]=10 7.27 7.5 7.73 V
detection voltage 4 Vuv4 VCC2 falling, UVD_V[1:0]=11 7.76 8.0 8.24 V
release voltage 1 Vuvr1 VCC2 rising, UVD_V[1:0]=00 6.79 7.0 7.21 V
release voltage 2 Vuvr2 VCC2 rising, UVD_V[1:0]=01 7.76 8.0 8.24 V
release voltage 3 Vuvr3 VCC2 rising, UVD_V[1:0]=10 8.73 9.0 9.27 V
release voltage 4 Vuvr4 VCC2 rising, UVD_V[1:0]=11 8.24 8.5 8.76 V
detection hysteresis 1 Vuvhs1 UVD_V[1:0]=00 0.5 V
detection hysteresis 2 Vuvhs2 UVD_V[1:0]=01 0.5 V
detection hysteresis 3 Vuvhs3 UVD_V[1:0]=10 1.5 V
detection hysteresis 4 Vuvhs4 UVD_V[1:0]=11 0.5 V
Over-Voltage detection(OVDET)
detection voltage Vovd VCC2 rising 17 18 19 V
detection hysteresis Vodhys 0.5 V
Over-Voltage protection(OVP)
detection voltage Vovp VCC1/VCC2 rising, output disabled 21 V
detection hysteresis Vovhys 0.5 V
CMOS Output(ACCDET, BDET)
“H” voltage VflgH Isource=1 mA VDD-0.3 VDD V
“L” voltage VflgL Isink=1 mA 0.3 0.4 V
RSTB :
Input “L” voltage Vilrs Internal circuit reset 0 0.4 V
Input “H” voltage Vihrs Internal circuit reset released 2.8 VDD VDD+0.3 V
“L” voltage VrsbL Isink=1 mA 0.3 0.4 V
2
I C-bus I/F; SCL,SDA
Input “L” voltage Vils 0 0.4 V
Input “H” voltage Vihs 2.8 VDD VDD+0.3 V
SDA “L” voltage Vols Isink=1 mA, ACK or data read 0.3 0.4 V
3. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. All the specification is defined based on the tests performed under the conditions where Tj and Ta(=25°C) are almost equal. These tests
were performed with pulse load to minimize the increase of junction temperature (Tj).
5. Guaranteed by design

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 LV56851UV

TYPICAL CHARACTERISTICS
Standby Current (Icc) Standby Current (Icc)
80 800

75 700
70
600
65
500
60
Icc (uA)

Icc (uA)
55 400

50 VCC=7V
300
VCC=14.4V -45°C
45 25°C
VCC=16V 200
40 85°C
100 110°C
35

30 0
-50 0 50 100 0 5 10 15 20 25 30 35 40
temp(deg.) VCC1,VCC2 (V)

RESET Voltage RESET detection hysteresis

87 3

86.5
2.5
86

85.5
2
Vrshs (%)

85
Vrst (%)

84.5 1.5

84
1
83.5

83
0.5
82.5

82 0
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

RESET Detection Voltage RESET Detection Delay (Td1)

2.95 35

33
2.9
31
Td1 (us)

29
2.85
Vreset(V)

27

2.8
25

23
2.75
21

2.7 19
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

RESET Detection Delay (Td2)

140

130

120

110
Td2 (us)

100

90

80

70
-50 0 50 100
temp(deg.)

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 LV56851UV

ACC Under Voltage Detection2, detection voltage Under Voltage Detection2, detection voltage
3.6 8.2

8.1
3.5
8
Vacc2, Vaccr2 (V)

Vuv2, Vuvr2 (V)

3.4
Vacc2 7.9

Vaccr2 Vuv2
3.3 7.8
Vuvr2
7.7
3.2
7.6
3.1
7.5

3 7.4
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

Over Voltage Detection, detection voltage Over Voltage Protection, detection voltage
18.4 22

18.2
Vovd Vovp
21.5
Vovd_r Vovp_r
18
Vovd (V)

21
17.8
Vovp (V)

17.6
20.5

17.4
20
17.2

17 19.5
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

[VDD] Output voltage (Io=200mA) [VDD] Dropout voltage (Io=200mA)

3.4 0.8

3.38
VCC1=7V 0.7
3.36
VCC1=14.4V
3.34
0.6
VCC1=16V
3.32
Vo (V)

Vdrop (V)

3.3 0.5

3.28
0.4
3.26

3.24
0.3
3.22

3.2 0.2
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

[VDD] Output current vs Output voltage (VCC1=14.4V)

4 [VDD] Ripple Rejection vs frequency (Io=200mA, T=25°C)
100

3.5 90
VCC=7V
80
3 VCC=14.4V
70 VCC=16V
2.5
60
Vo (V)

(dB)

2 50
-45°C
1.5 40
25°C
85°C 30
1
110°C
20
0.5
10

0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 10 100 1000 10000 100000
Io (A) Frequency (Hz)

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 LV56851UV

[SYS(3.3V)] Output voltage (Io=200mA) [SYS(3.3V)] Dropout voltage (Io=200mA)

3.4 0.7

3.38
0.6
3.36

3.34
0.5
3.32

Vdrop (V)
Vo (V)

3.3 0.4

3.28
VCC2=7.5V 0.3
3.26
VCC2=14.4V
3.24
VCC2=16V 0.2
3.22

3.2 0.1
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

[SYS(3.3V)] Ripple Rejection vs frequency (Io=200mA, T=25°C)

[SYS(3.3V)] Output current vs Output voltage (VCC2=14.4V) 100
4
90
3.5 VCC=7.5V
80
VCC=14.4V
3
70
VCC=16V
2.5 60
(dB)
Vo (V)

2 50
-45°C
1.5 40
25°C
85°C 30
1
110°C 20
0.5
10
0
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
10 100 1000 10000 100000
Io (A) Frequency (Hz)

[ILM(8V)] Output voltage (Io=200mA) [ILM(8V)] Dropout voltage (Io=200mA)

8.2 0.9

8.15
0.8

8.1
0.7
8.05
0.6
Vo (V)

Vdrop (V)

8
0.5
7.95
VCC2=10V
0.4
7.9 VCC2=14.4V
VCC2=16V 0.3
7.85

7.8 0.2
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

[ILM(8V)] Output current vs Output voltage (VCC2=14.4V) [ILM(8V)] Ripple Rejection vs frequency (Io=200mA, T=25°C)
10 80

9 70
VCC=10V
8
60 VCC=14.4V
7 VCC=16V
50
6
(dB)
Vo (V)

5 40
-45°C
4 30
25°C
3
85°C 20
2
110°C
10
1

0 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 10 100 1000 10000 100000
Io (A) Frequency (Hz)

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 LV56851UV

[CD(8V)] Output voltage (Io=1A) [CD(8V)] Dropout voltage (Io=1A)

8.2 1.4

8.15 1.3

1.2
8.1
1.1
8.05
1
Vo (V)

Vdrop (V)
8 0.9

7.95 0.8
VCC2=10V
0.7
7.9 VCC2=14.4V
0.6
7.85 VCC2=16V
0.5

7.8 0.4
-50 0 50 100 -50 0 50 100
temp(deg.) temp(deg.)

[CD(8V)] Output current vs Output voltage (VCC2=14.4V) [CD(8V)] Ripple Rejection vs frequency (Io=1000mA, T=25°C)
9 90

8 80

7 70 VCC=10V
VCC=14.4V
6 60
VCC=16V
5 50
Vo (V)

(dB)

4 40
-45°C
3 30
25°C
2 85°C 20
110°C
1 10

0 0
0 0.5 1 1.5 2 2.5 10 100 1000 10000 100000
Io (A)
Frequency (Hz)

[AUDIO(8.5V)] Output voltage (Io=200mA)

8.7 AUDIO Dropout Voltage (Io=200mA)
0.45

8.65
0.4
VCC2=9.5V
8.6 VCC2=14.4V
0.35
8.55 VCC2=16V
0.3
Vo (V)

Vdrop (V)

8.5
0.25
8.45
0.2
8.4

0.15
8.35

8.3 0.1
-50 0 50 100 -50 0 50 100
temp(deg.)
temp(deg.)

[AUDIO(8.5V)] Output current vs Output voltage (VCC2=14.4V) [AUDIO] Ripple Rejection vs frequency (Io=200mA, T=25°C)
10 80

9 70 VCC=7.5V
8 VCC=14.4V
60
7 VCC=16V
50
6
(dB)
Vo (V)

5 40
-45°C
4 30
25°C
3 85°C
20
110°C
2
10
1

0 0
0 0.2 0.4 0.6 0.8 1 10 100 1000 10000 100000
Io (A) Frequency (Hz)

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 LV56851UV

[AMP] Output drop voltage (Io=500mA) [AMP] Output current vs Output voltage (VCC2=14.4V)
1 16

0.9 14

12
0.8
10
-45°C
Vo (V)

0.7

Vo (V)
25°C
8
85°C
0.6
6 110°C
VCC2=7.5V
0.5 4
VCC2=14.4V
VCC2=16V
0.4 2

0.3 0
-50 0 50 100 0 0.2 0.4 0.6 0.8 1 1.2

temp(deg.) Io (A)

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 LV56851UV

I2C-bus Interface timing

Parameter Symbol min typ max unit
SCL clock frequency fSCL 0 400 kHz
START condition hold time tHD;STA 0.6 us
SCL “L” pulse-width tLOW 1.3 us
SCL “H” pulse-width tHIGH 0.6 us
DATA hold time tHD;DAT 0 us
DATA setup time tSU;DAT 0.1 us
SDA/SCL rise time tr 0.3 us
SDA/SCL fall time tf 0.3 us
STOP condition setup time tSU;STO 0.6 us
Bus free time tBUF 1.3 us
between STOP and START condition
Bus line load capacitance Cb 400 pF

SDA
tf tr
tSU;DAT tBUF
tLOW tr tf

SCL

tHD;STA
ST tHD;DA tHIGH tSU;STO SP ST

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 LV56851UV

I2C-bus interface format (MSB first)

This part is I2C controlled power supply, using 2 wires This part doesn't accept sub-address auto increment
of SCL,SDA. format. (Single data byte write per a communication.)
The communication protocol comprises The protocol in Read-mode comprises start-condition,
start-condition, device-address, sub-address, data and device-address, data1, data2 and stop-condition.
stop-condition. (Note)The I2C-bus communication may be unstable
Every 8 bits are followed by ACK bit, and the receiver when VDD voltage is not stable or out of specification
device pulls down SDA line during ACK period. range, since I2C-BUS circuitry is supplied by VDD.

Write mode

SCL

SDA S6 S5 S4 S3 S2 S1 S0 W AK A7 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

Start Device Address + R/W + ACK Sub Address(A) + ACK Data(address A) + ACK Stop
Condition Condition

Read mode

SCL

SDA S6 S5 S4 S3 S2 S1 S0 R AK D15 D14 D13 D12 D11 D10 D9 D8 AK D7 D6 D5 D4 D3 D2 D1 D0 AK

Device Address + R/W + ACK Read data1 + ACK Read data2 + ACK
Start Stop
Condition Condition
• Device address
S6 S5 S4 S3 S2 S1 S0 R/W
0 0 0 1 0 0 0 1/0

• Register map
Write
D7 D6 D5 D4 D3 D2 D1 D0 init
PM ILM_EN CD_EN AUDIO_EN SYS_EN AMP_EN 0 0 0 00000000
VCTL ILM_V1 ILM_V0 CD_V1 CD_V0 AUD_V1 AUD_V0 SYS_V 0 00000000
DET ACC_V1 ACC_V0 UVD_V1 UVD_V0 BDETMD 0 (Reserved) 00000000

Read
D15 D14 D13 D12 D11 D10 D9 D8 init
VCTL ILM_V1 ILM_V0 CD_V1 CD_V0 AUD_V1 AUD_V0 SYS_V 0 00000000

D7 D6 D5 D4 D3 D2 D1 D0 init
FLG ACCUV UV OV OVP TWARN OC 0 0 00000000

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 LV56851UV

Write Register explanation

ADR bit Name init Description
00h 7 ILM_EN 0 ILM output enable 1: ON 0: OFF
6 CD_EN 0 CD output enable 1: ON 0: OFF
5 AUDIO_EN 0 AUDIO output enable 1: ON 0: OFF
4 SYS_EN 0 SYS output enable 1: ON 0: OFF
3 AMP_EN 0 AMP output enable 1: ON 0: OFF
2 0
1 0
0 0

ADR bit Name init Description

01h [7:6] ILM_V[1:0] 00 ILM output voltage(*) 11: 12 V 10: 10.5 V 01: 9 V 00: 8 V
[5:4] CD_V[1:0] 00 CD output voltage(*) 11: 8 V 10: 7 V 01: 6 V 00: 5 V
[3:2] AUD_V[1:0] 00 AUDIO output voltage(*) 11: 12 V 10: 9 V 01: 8.5 V 00: 5 V
1 SYS_V 0 SYS output voltage(*) 1: 5 V 0: 3.3 V
0 0
(*) “Output voltage setting” is only valid when corresponding output is set disabled(xxx_EN=0). It is ignored when the output is
set enabled(xxx_EN=1).

ADR bit Name init Description

02h [7:6] ACC_V[1:0] 00 ACC detection voltage 11: 4.2 V 10: 3.6 V 01: 3.2 V 00: 2.7 V
[5:4] UVD_V[1:0] 00 UVDET detection voltage
11: 8 V 10: 7.5 V(9 V) 01: 7.5 V(8 V) 00: 6.5 V
3 BDETMD 0 BDET output mode 1: BDET/TWARN 0: BDET only
2 0
[1:0] (Reserved) 00 (For TEST) Must be set to “00” for normal use.

Read Register explanation

ADR bit Name init Description
[15:14] ILM_V[1:0] 00 ILM output voltage 11: 12 V 10: 10.5 V 01: 9 V 00: 8 V
[13:12] CD_V[1:0] 00 CD output voltage 11: 8 V 10: 7 V 01: 6 V 00: 5 V
[11:10] AUD_V[1:0] 00 AUDIO output voltage 11: 12 V 10: 9 V 01: 8.5 V 00: 5 V
9 SYS_V 0 SYS output voltage 1: 5 V 0: 3.3 V
8 0
7 ACCUV 0 ACC detection 1: Under voltage 0: Nornmal
6 UV 0 Under voltage detection 1: Under voltage 0: Normal
5 OV 0 Over voltage detection 1: Over Voltage 0: Normal
4 OVP 0 Over voltage protection 1: Over Voltage Protection 0: Normal
3 TWARN 0 Thermal Warning 1: High temperature 0: Normal
2 OC 0 Output Over Current 1: Over current 0: Normal
1 0
0 0

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 LV56851UV

FUNCTIONAL DESCRIPTION The voltage of each output can be selected via I2C-bus.
These commands must be set prior to enabling
[Standby mode] corresponding output. If you intend to change the
When VCC1 is applied, internal control circuitry is voltage setting for these outputs, be sure to do it after
automatically reset and goes into Stand-by mode. the output is set disabled. In order to avoid unintended
In Stand-by mode, following functions are active. output voltage change, each “output voltage setting” is
VDD(3.3 V) output valid only when corresponding output is set
I2C-bus communication disabled(xxx_EN=0). The “output voltage setting” is
Over voltage ignored when the output is set enabled(xxx_EN=1).
protection(OVP)/UVDET/OVDET/ACC Output voltage setting can be referred by reading via
detection/BDET output I2C-bus(VCTL register). It is strongly recommended
Thermal shutdown(TSD) to read and check VCTL register value just before
setting enable the output in order to avoid unintended
[VCC1/VCC2] output voltage change even in case if communication
VCC1 input is necessary for any operation of this error were to happen and incorrect voltage setting
device since VCC1 supplies VDD and common were written to the device.
circuitry such as reference voltage, internal control Each regulator output limits output current if the
circuitry. output gets over-loaded condition. The limit current
VCC2 is the supply for AUDIO/ILM/CD/AMP/SYS decreases as the output voltage gets lower, in order to
outputs. reduce the stress applied to the device.
LV56851UV can tolerate up to 50 V peak surge
voltage on VCC1/2 or ACCIN, but for more safety All regulators in LV56851UV are low dropout outputs,
design, adding power clamp such as power zener because the output stage of all regulators is P-channel
diode on battery connected line is recommended in LDMOS.
order to absorb applied surge. When you select output capacitors for linear
LV56851UV has no protection against battery reverse regulators, you should consider three main
connection. If a negative voltage input is possible, characteristics: startup delay, transient response and
adding Schottky diode between VCC and GND is loop stability. The capacitor values and type should be
recommended to protect the device from the negative based on cost, availability, size and temperature
voltage. constraints. Tantalum, Aluminum electrolytic, Film,
or Ceramic capacitors are all acceptable solutions.
[Controls] However, attention must be paid to ESR constraints.
The functions of LV56851UV can be controlled via The aluminum electrolytic capacitor is the least
I2C-bus. See “I2C bus interface format” term for expensive solution, but if the circuit operates at low
details. temperatures (-25 to -40°C ), both the value and ESR
of the capacitor will vary considerably. The capacitor
[Linear Regulators] manufacturer's datasheet usually provides this
VDD output information.
When VCC1 is applied, VDD output is active
regardless of control states. [High-side switch]
AMP is a high-side power switch connected to VCC2.
SYS/CD/AUDIO/ILM output The output is enabled or disabled via I2C-bus.
These outputs are individually enabled or disabled via The high-side switch limits output current if the output
I2C-bus. gets over-loaded condition. The limit current becomes
lower value, if the output voltage gets lower than 2.5

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 LV56851UV

V(typ) in order to reduce the stress applied to the [Detections]

device.
RESET circuit
If the output is connected to inductive load or loads
When the VDD voltage drops below the reset
which have different ground potential, protection
threshold (typ:2.8 V, 85% of Vo1:3.3 V) for more than
diodes (D1,D2) are necessary to protect the device
Detection delay period(Td1), RSTB is pulled low.
from negative voltage.
During RSTB=Low, internal control circuitry is reset
and all the registers of I2C-bus are initialized.
[Current Limiting]
When the VDD voltage rises higher than the threshold
When the each output becomes in over loaded
(typ:2.86 V, 86.6% of Vo1:3.3 V), RSTB becomes
condition, the device limits the output current.
open state and reaches high level by external resistor
All outputs are also protected against short circuit to
Rrst, internal reset is released after the delay
GND by fold back current limiter.
period(Td2).
If one of each output except VDD is in over-current
Add an optional capacitor between RSTB to GND in
condition, OC bit of FLG register is set 1, which can
order to obtain longer reset time (>Td2). The
be read via I2C-bus.
approximate delay time can be calculated by the
expression below.

VDD
I2C RESET delay time (typ)
Rrst RSTB = 0.68*Rrst*Crst + Td2 (sec)
To Reset
CTRL
MCU
Crst

(Optional) Vrst
Filter
VDD
Vrst : RESET voltage(typ:2.8 V)

RESET circuit block diagram

Vrst+Vrsth
VDD Vrst
(<Td1)
(<Td2) GND
VDD
Td2
Td2
RSTB Td1 Td1
GND
Unstable Region Unstable Region

RSTB Timing Chart

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 LV56851UV

Under voltage detection (UVDET) Thermal Shutdown

If the VCC2 voltage gets lower than set value To protect the device from overheating, a thermal
(UVD_V[1:0]), Under-Voltage is detected and the UV shutdown circuitry is included. If the junction
bit of FLG register is set 1, which can be read via temperature exceeds approximately 175°C(typ), all
I2C-bus. BDET pin keeps “Low” during UVDET outputs are turned off regardless of control state. After
condition. Each output status keeps the same the junction temperature drops below 145°C(typ),
condition even if UV is detected. VDD output is automatically restored and I2C-bus
control becomes available.
Over voltage detection (OVDET) The thermal shutdown circuit does not guarantee the
If the VCC2 voltage exceeds 18V(typ), Over-Voltage protection of the final product because it operates out
is detected and the OV bit of FLG register is set 1, of maximum rating (exceeding Tjmax=150°C).
which can be read via I2C-bus. BDET pin keeps
“Low” during OVDET condition. Each output status Thermal Warning
keeps the same condition even if OV is detected. To inform over-temperature of the die, when the
junction temperature exceeds approximately
ACC Under voltage detection 140°C(typ), the TWARN bit of FLG register is set 1,
If the ACCIN voltage gets lower than set value which can be read via I2C-bus. After the junction
(ACC_V[1:0]), the ACCUV bit of FLG register is set temperature drops below 130°C(typ), TWARN is
1, which can be read via I2C-bus. ACCDET pin keeps released and TWARN bit is reset.
“Low” during ACCUV is detected. Each output status keeps the same condition even if
Each output status keeps the same condition even if TWARN is detected.
ACCUV is detected. If you set BDETMD bit=1 of DET register, BDET pin
becomes “Low” when TWARN is detected.
Over voltage protection (OVP)
If the voltage of VCC1 or VCC2 exceeds 21 V(typ), BDET output
OVP is detected and the OVP bit of FLG register is set BDET output depends on BDETMD bit setting of
1, which can be read via I2C-bus. And all the outputs DET register as shown on the table below.
except VDD are automatically turned off. When the When each of the listed condition is satisfied, BDET is
voltage of VCC1 and VCC2 get lower than 20.5 pulled “Low”.
V(typ), OVP detection is released. But output voltages
are not automatically restored, because once OVP is
detected, PM register of I2C-bus is reset.
BDET pin keeps “Low” during OVP condition.

Conditions for BDET=Low BDETMD

Conditions 0 (default) 1
UV VCC2 < UVDET Threshold  
OV VCC2 > OVDET Threshold  
TWARN Tj > 140oC(typ) ignored 

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 LV56851UV

Timing Chart
21 V 20.5 V
18 V 17.5 V

OVP detect
VCC2 7V
6.5 V

OVP release
VCC1
3.8 V

VDD output 2.86 V 2.8 V 2.8 V

VDD lost

RSTB VDD

Output enable

Output enable
AUDIO_EN=1

AUDIO_EN=0
AMP_EN=1

AMP_EN=0
SYS_EN=1

SYS_EN=0
ILM_EN=1

ILM_EN=0
CD_EN=0
CD_EN=1

Settings
Settings

Settings
Settings

Initial
Initial

2
I C inputs
(SCL/SDA)

ILM output

CD output

AUDIO output

SYS output

AMP output

ACCIN 2.9 V 2.7 V

ACCDET VDD

BDET VDD

OVDET UVDET
Note: The above values are obtained when typ. All the voltage setting are default values

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 LV56851UV

APPLICATION CIRCUIT EXAMPLE

LV56851UV

ACCIN
AUDIO

ACCDET
VCC1

BDET
GND

SDA
SCL

RSTB
VCC2
AMP

VDD
SYS
ILM

CD
2 4 6 8 10 12 14
1 3 5 7 9 11 13 15
C4
C2

C3

SCL SDA
C1

BDET

C10
C9
ACCDET
D2 C6 C5 C8 C7
R3
ILM AUDIO CD R2
D1 SYS VDD RSTB
R1

D3

ACC
AMP +B

Peripheral parts
Part name Description Recommended value Note
C1 Capacitor for AMP output stabilization greater than 2.2 μF
C2,C3,C4,C9,C10 output stabilization capacitor greater than10 μF(*)
C6,C8 Power supply bypass capacitor C6: greater than 100 μF Make sure to
C8: greater than 47 μF implement close to
C5,C7 Capacitor for oscillation protector greater than 0.22 μF VCC and GND.
D1,D2 Internal device protection diode ON Semiconductor
SB1003M3
D3 Reverse current protection diode ON Semiconductor
SB1003M3
R1,R2 ACC divider resistors R1>R2
R3 Pull-up resistor 100 kΩ
(*) Make sure that output capacitors are greater than 10 μF and meets the condition of ESR=0.001 to 10 Ω , in which
voltage/temperature dependence and their tolerances are taken into consideration. Moreover, in case of electrolytic
capacitor, high-frequency characteristics should be sufficiently good.

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 LV56851UV

HZIP15 Heat sink attachment

Heat sinks are used to lower the semiconductor device
Heat sink
junction temperature by leading the head generated by
the device to the outer environment and dissipating the
gap
heat.

a. Unless otherwise specified, for power ICs with tabs

and power ICs with attached heat sinks, solder must
not be applied to the heat sink or tabs.
via hole
b. Heat sink attachment

Binding-head Countersunk head

machine-screw ma chine screw c. Silicone grease
• Spread the silicone grease evenly when mounting
• Use flat-head screws to attach heat sinks. heat sinks.
• Use also washer to protect the package. • Sanyo recommends YG-6260 (Momentive
• Use tightening torques in the ranges 39-59 Ncm(4-6 Performance Materials Japan LLC)
kgcm) .
• If tapping screws are used, do not use screws with a d. Mount
diameter larger than the holes in the semiconductor • First mount the heat sink on the semiconductor
device itself. device, and then mount that assembly on the printed
• Do not make gap, dust, or other contaminants to get circuit board.
between the semiconductor device and the tab or • In case of attaching a heat sink after mounting a
heat sink. semiconductor device into the printed circuit board,
• Take care to the position of via hole. be sure not to apply mechanical stress to the
• Do not allow dirt, dust, or other contaminants to get semiconductor device and the external pins when
between the semiconductor device and the tab or tightening up a heat sink with the screw.
heat sink.
• Verify that there are no press burrs or screw-hole e. When mounting the semiconductor device to the heat
burrs on the heat sink. sink using jigs, etc.,
• Warping in heat sinks and printed circuit boards • Take care not to allow the device to ride onto the jig
must be no more than 0.05 mm between screw holes, or positioning dowel.
for either concave or convex warping. • Design the jig so that no unreasonable mechanical
• Twisting must be limited to under 0.05 mm. stress is applied to the semiconductor device.
• Heat sink and semiconductor device should be
mounted in parallel. f. Heat sink screw holes
Take care of electric or compressed air screw driver • Be sure that chamfering and shear drop of heat sinks
• The speed of these torque wrenches must not exceed must not be larger than the diameter of screw head
700 rpm, and should typically be about 400 rpm. used.

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 LV56851UV

• When using nuts, do not make the heat sink hole

diameters larger than the diameter of the head of the
screws used. A hole diameter about 15 % larger than
the diameter of the screw is recommended.
• When tap screws are used, be sure that the diameter
of the holes in the heat sink are not too small. A
diameter about 15 % smaller than the diameter of the
screw is recommended.

g. There is a method to mount the semiconductor device

to the heat sink by using a spring band. But this
method is not recommended because of possible
displacement due to fluctuation of the spring force
with time or vibration.

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 LV56851UV

Package Dimensions
unit : mm

HZIP15
CASE 945AB
ISSUE A

SOLDERING FOOTPRINT*
(Unit: mm) Through Hole Area
Package name 2.54
HZIP15 (1.91)
1.2 2.54

2.54

2.54

NOTE: The measurements are not to guarantee but for reference only.

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 LV56851UV

ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.

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Mouser Electronics

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