LPC 2148 peripherals

Course handled by

Dr.Saru Meena R.

Assistant Professor

Dept. of Electronics and Communication

Engineering,

Amrita School of Engineering

Amrita Vishwa Vidyapeetham

Coimbatore
 General purpose input and output (GPIO)

§ General-purpose input/output (GPIO) is a pin on an IC (Integrated Circuit)

§ It can be either input pin or output pin, whose behavior can be controlled at the run time

§ A group of these pins is called a port (Example, Port 0 of LPC2148 has 32 pins).

§ LPC2148 has two 32-bit General Purpose I/O ports : (a) PORT0 and (b) PORT1

Port 0 :

§ PORT0 is a 32-bit port

§ Out of these 32 pins, 28 pins can be configured as either general purpose input or output

§ 1 of these 32 pins (P0.31) can be configured as general-purpose output only

§ 3 of these 32 pins (P0.24, P0.26 and P0.27) are reserved. Hence, they are not available for use. Also, these pins
are not mentioned in pin diagram

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 General purpose input and output (GPIO)

§ PORT1 is also a 32-bit port. Only 16 of these 32 pins (P1.16 –

P1.31) are available for use as general-purpose input or output

§ Almost every pin of these two ports has some alternate function

available

§ For example, P0.0 can be configured as the TXD pin for UART0

or as PWM1 pin as well

§ The functionality of each pin can be selected using the Pin

Function Select Registers (PINSEL)

Pin diagram of LPC 2148

3
 General purpose input and output (GPIO)

Pin Function Select Registers (PINSEL)

§ PINSEL registers are 32-bit registers. These registers are used to select or configure specific pin functionality.

§ There are 3 PINSEL registers in LPC2148:

1. PINSEL0 : - PINSEL0 is used to configure PORT0 pins P0.0 to P0.15.

2. PINSEL1 : - PINSEL1 is used to configure PORT0 pins P0.16 to P0.31

3. PINSEL2 : - PINSEL2 is used to configure PORT1 pins P1.16 to P1.31.

§ Any pin on the LPC2148 can have a maximum of 4 functions

§ In order to select one of the four functions, two corresponding bits of the PINSEL register are needed

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General purpose input and output (GPIO)

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 General purpose input and output (GPIO)

§ There are two types of GPIO : (a) Slow GPIO and (b) fast GPIO

Slow GPIO :

§ In slow GPIO mode, the access to GPIO registers is done through the VPB (VLSI Peripheral Bus)

§ The VPB clock is typically derived from the CPU clock (CCLK) but can be divided by a factor (default is 4)

§ This division makes GPIO operations slower compared to the fast mode

§ Slow GPIO operations can take more clock cycles due to the VPB divider

Key characteristics of slow GPIO :

§ Accesses GPIO through VPB (divided clock).

§ Suitable for most standard GPIO applications.

§ Can be relatively slower due to the clock division

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 General purpose input and output (GPIO)

Fast GPIO registers:

§ The fast GPIO is an enhanced version of GPIO access, introduced to speed up the GPIO operations.

§ In fast GPIO mode, the GPIO registers are accessed directly through the AHB (Advanced High-performance

Bus), which runs at the CPU clock speed (CCLK) without any division.

§ Fast GPIO operations are much faster because the GPIO control is directly connected to the AHB bus.

Key characteristics of fast GPIO:

§ Accesses GPIO directly through the AHB (no clock division).

§ Provides faster response for GPIO pin operations.

§ Suitable for time-critical applications where fast response is needed (e.g., toggling pins at high frequency)

Thus, slow GPIO is slower due to clock division, while fast GPIO operates at the system clock speed and is used

when speed is critical

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 General purpose input and output (GPIO)

Slow GPIO registers:

§ IOxDIR (GPIO Port Direction control register) : This is a 32-bit wide register. This register individually controls
the direction of each port pin. Setting a bit to ‘1’ configures the corresponding pin as an output pin. Setting a bit

to ‘0’ configures the corresponding pin as an input pin.

§ IOxSET (GPIO Port Output Set register) : This is a 32-bit wide register. This register is used to make pins of Port

(PORT0/PORT1) HIGH. Writing one to specific bit makes that pin HIGH. Writing zero has no effect.

§ IOxCLR (GPIO Port Output Clear register) : This is a 32-bit wide register. This register is used to make pins of
Port LOW. Writing one to specific bit makes that pin LOW. Writing zeroes has no effect.

§ IOxPIN (GPIO Port Pin value register): This is a 32-bit wide register. This register is used to read/write the value
on Port (PORT0/PORT1). But care should be taken while writing. Masking should be used to ensure write to the

desired pin

§ x=0 or 1 ; 0 if port 0 is used and 1 if port 1 is used

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General purpose input and output (GPIO)

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

Configuring the pins as input or output :

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General purpose input and output (GPIO)

15
General purpose input and output (GPIO)

16
General purpose input and output (GPIO)

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Analog to digital converter (ADC)

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Analog to digital converter (ADC)

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 Analog to digital converter (ADC)

Registers associated with ADC :

1) ADxCR : ADC control register (size : 32 bit)

x=0 or 1 depending upon the ADC module chosen

x=0 if ADC0 is chosen ; x=1 if ADC1 is chosen

AD0CR :

Bits 7:0 – SEL

These bits select ADC0 channel as analog input. In software-controlled mode, only one of these bits should be
1.e.g. bit 7 (10000000) selects AD0.7 channel as analog input

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 Analog to digital converter (ADC)

Bits 15:8 – CLKDIV

§ The APB(ARM Peripheral Bus)clock is divided by this value plus one, to produce the clock for ADC

§ This clock should be less than or equal to 4.5MHz

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 Analog to digital converter (ADC)

Peripheral clock (PCLK) :

§ CCLK → CPU clock (60 MHz)

§ 𝑓!"# = 12 𝑀𝐻𝑧

§ 𝑓!"# → PLL block → CCLK = 60 MHz

$$%&
§ CCLK → VPB DIV block → PCLK = '

§ If PCLK has to be 60 MHz , y=1 (i.e.) the

dividing factor in the VPB DIV block should

be 1

§ If PCLK has to be 30 MHz , y=2 (i.e.) the

dividing factor in the VPB DIV block should

be 2

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 Analog to digital converter (ADC)

Bits 15:8 – CLKDIV

§ The APB(ARM Peripheral Bus)clock is divided by this value plus one, to produce the clock for ADC

§ This clock should be less than or equal to 4.5MHz

Calculation :

($%& (+,-.+/,-01 #1!#2)

§ 4
= 𝐴𝐷𝐶 𝑐𝑙𝑜𝑐𝑘 = 4.5 𝑀𝐻𝑧

($%& $(6 #1!#2

§ PCLK = 60 MHz ; ∴ 𝑥 = 135 ; but this x is made to 14 so that ≤ 4.5 𝑀𝐻𝑧
4

§ But to avoid the divide by zero error , LPC 2148 will add 1 to whatever value is being given in CLKDIV . ∴ 8 bit
binary representation of 135 is loaded in CLKDIV ; CLKDIV = 0000 1101

§ In short , value needed is 𝑥 = 145 ; value loaded is 𝑥 = 135 23

 Analog to digital converter (ADC)

Bit 16 – BURST

Burst mode in the LPC2148 ADC allows for continuous conversions without the need for constant manual

triggering

§ When burst =0 , the ADC waits for the user to tell it to start each time. It takes one reading, then stops.

§ Burst = 0 means the user must manually trigger the ADC to start each conversion, either by software (the user

tell it to start) or using an external signal (like pressing a button)

§ The ADC converts the signal once and then stops. The user must issue another command for the next
conversion.

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 Analog to digital converter (ADC)

Bit 16 – BURST

When BURST = 1, ADC works in burst mode

§ When burst mode is enabled, the ADC automatically samples and converts the selected analog input channels

repeatedly without requiring the user to start each conversion individually

§ In simple terms, it's like setting the ADC to autopilot mode—once activated, it keeps converting analog signals

into digital values continuously for the selected channels, instead of waiting for the user to say, "start a new

conversion”

§ When Burst = 1, the START bits must be 000, otherwise the conversions will not start

§ In Burst mode, ADC does repeated conversions at the rate selected by the CLKS field for the analog inputs
selected by SEL field

§ When Burst = 1, the START bits must be 000, otherwise the conversions will not start

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 Analog to digital converter (ADC)

Bits 19:17 – CLKS

Selects the number of clocks used for each conversion in burst mode and the number of bits of accuracy of Result

bits of AD0DR.

e.g. 000 uses 11 clocks for each conversion and provide 10 bits of result in corresponding ADDR register.

000 = 11 clocks / 10 bits

001 = 10 clocks / 9 bits § For 10 bit ADC , the smallest change in analog voltage (step size) =
010 = 9 clocks / 8 bits !.!
= 3.2 𝑚𝑣
#$%&
011 = 8 clocks / 7 bits § If the input voltage is 0v, the digital output is 0. If the input voltage
100 = 7 clocks / 6 bits becomes 3.3mv, the digital output is 1.
101 = 6 clocks / 5 bits § Only if there is a change in input voltage by 3.2 mv, there will be a

110 = 5 clocks / 4 bits transition to the next value in digital output

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 Analog to digital converter (ADC)

Bit 20 – RESERVED

Bit 21 – PDN ; used to decide whether ADC is in power down mode or involved in conversion

0 = ADC is in Power Down mode

1 = ADC is operational

Bit 23:22 – RESERVED

Bit 26:24 – START

When BURST bit is 0, these bits control whether and when A/D conversion is started

000 = No start (Should be used when clearing PDN to 0)

001 = Start conversion now

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 Analog to digital converter (ADC)

010 = Start conversion when edge selected by bit 27 of this register occurs on CAP0.2/MAT0.2 pin

011= Start conversion when edge selected by bit 27 of this register occurs on CAP0.0/MAT0.0 pin

100 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.1 pin

101 = Start conversion when edge selected by bit 27 of this register occurs on MAT0.3 pin

110 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.0 pin

111 = Start conversion when edge selected by bit 27 of this register occurs on MAT1.1 pin

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 Analog to digital converter (ADC)

Bit 27 – EDGE

This bit is significant only when the Start field contains 010-111. In these cases,

0 = Start conversion on a rising edge on the selected CAP/MAT signal

1 = Start conversion on a falling edge on the selected CAP/MAT signal

Bit 31:28 – RESERVED

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 Analog to digital converter (ADC)

ADxGDR (A/D Global Data Register) :

§ ADxGDR is a 32-bit register (x=0 or 1)

§ This register contains the ADC’s DONE bit and the result of the most recent A/D conversion

Bit 5:0 – RESERVED

Bits 15:6 – RESULT

§ When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0 (less than or

equal to VSSA) to 1023 (greater than or equal to VREF).

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 Analog to digital converter (ADC)
Bit 23:16 – RESERVED

Bits 26:24 – CHN

§ These bits contain the channel from which ADC value is read.

e.g. 000 identifies that the RESULT field contains ADC value of channel 0.

Bit 29:27 – RESERVED

Bit 30 – Overrun

§ This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten before the
conversion that produced the result in the RESULT bits

§ This bit is cleared by reading this register

Bit 31 – DONE

§ This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the
AD0CR is written

§ If AD0CR is written while a conversion is still in progress, this bit is set and new conversion is started
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 Analog to digital converter (ADC)
AD0DR0-AD0DR7 (ADC0 Data Registers)

§ These are 32-bit registers.

§ They hold the result when A/D conversion is completed.

§ They also include flags that indicate when a conversion has been completed and when a conversion overrun
has occurred

AD0 data registers structure

Bit 5:0 – RESERVED

Bits 15:6 – RESULT

§ When DONE bit is set to 1, this field contains 10-bit ADC result that has a value in the range of 0 (less than or
equal to VSSA) to 1023 (greater than or equal to VREF).

Bit 29:16 – RESERVED

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 Analog to digital converter (ADC)
Bit 30 – Overrun

§ This bit is set to 1 in burst mode if the result of one or more conversions is lost and overwritten before the
conversion that produced the result in the RESULT bits

§ This bit is cleared by reading this register

Bit 31 – DONE

§ This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read

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 Analog to digital converter (ADC)
Steps in analog to digital conversion :

§ Configure the port pin to function as ADC

§ Configure the ADxCR (ADC Control Register) according to the need of application.

§ Start ADC conversion by writing appropriate value to START bits in ADxCR. (Example, writing 001 to START bits

of the register 26:24, conversion is started immediately).

§ Monitor the DONE bit (bit number 31) of the corresponding ADxDRy (ADC Data Register) till it changes from 0

to 1. This signals completion of conversion

§ Read the ADC result from the corresponding ADC Data Register ADxDRy. E.g. AD0DR1 contains ADC result of

channel 1 of ADC0.

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 Analog to digital converter (ADC)
Steps in analog to digital conversion :

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 Analog to digital converter (ADC)
Step 1 :
PINSEL 1 register

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 Analog to digital converter (ADC)
Step 2 : Enable the power/clock to ADC0

PCONP : Power control for peripheral register (32 bit register)

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 Analog to digital converter (ADC)
Step 3 : Select channel 3 in AD0

ADOCR (Bits 7:0)

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 Analog to digital converter (ADC)
Step 4 : Set the CLKDIV to 13 ADOCR

AD0CR | = 13<<8

Step 5 : Disable the BURST mode by making

bit 16 as 0. This is done via. AND operation
between AD0CR and 0xFFFEFFFF Bit 21 = 1 ; this can be done via. OR operation between AD0CR

AD0CR & = 0xFFFEFFFF and 0x00200000

Step 5 : Configure CLKS as 000 since 10 bit AD0CR | = 0x00200000

resolution is needed Step 7: Start the ADC conversion now

19 : 17 = 000 ; this can be done via AND ADC conversion can be started immediately by making bits 26 :
operation between AD0CR and 0xFFF1FFF 24 as 001. Bit 24 is made 1 via. OR operation between AD0CR and

AD0CR & = 0xFFF1FFF 0x01000000. Bits 25 and 26 are made 0 via. AND operation
between AD0CR and 0x F9FFFFFF
Step 6 : Make PDN = 1 to activate the ADC
module AD0CR | = 0x01000000

AD0CR &=0xF9FFFFFF
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 Analog to digital converter (ADC)
Step 8 : Check whether analog to digital ADODR3
conversion is over or not by monitoring the
DONE bit (bit 31) in AD0GDR

AD0GDR & = 0x80000000 ; separate out bit

Except the RESULT bits , all the other bits in AD0DR3 are made 0
31 alone from AD0GDR
via. AND operation between (AD0DR3 >> 6) and 0x000003FF
If AD0GDR & = 0x80000000 is 1 , it
val = (AD0DR3>>6) & 0X000003FF
indicates that analog to digital conversion is
Step 9 : Deactivate the ADC module by making START bits (bits
complete ; else , it indicates that the analog
26 : 24) in AD0DGR as 000. This is done via. AND operation
to digital conversion process is not yet
between AD0CR and 0x F8FFFFFF
completed
AD0GDR & = 0xF8FFFFFF
§ When DONE=1 , the 10 bit A/D conversion
result is available in bits 15 : 6 of To visualize the result in terms of ON / OFF of 10 LEDs connected

AD0DR3. To visualize the result starting to port 1 (P1.16 to P1.25) , IO1PIN = val <<16 (since port 1 has pins

from bit 0 , the data in AD0DR3 has to be only from P1.16 to P1.31)

shifted right by 6. 40
 Analog to digital converter (ADC)
while(1) delay(200000);
Complete ADC code :
{ void adc_init(void)
# include <LPC214x.h>
AD0CR | = 0x00000008; {
void adc_init(void);
AD0CR | = 13<<8; PINSEL1& = 0xDFFFFFFF;
void delay(int j);
AD0CR & = 0xFFFEFFFF; PINSEL1|=0x10000000;
unsigned int val;
AD0CR & = 0xFFF1FFFF; PCONP|= (unsigned long) (0x00000001 << 12) ;
int main ()
AD0CR | = 0x00200000; }
{
AD0CR | = 0x01000000 ; void delay (int j)
PINSEL2 = 0x00000000;
AD0CR &=0xF9FFFFFF; {
IO1DIR = 0xFFFFFFFF;
while((AD0GDR & = 0x80000000)==0); for(i=0;i<=j;i++)
adc_init();
val = (AD0DR3>>6) & 0X000003FF; {

IO1PIN = val <<16

AD0GDR & = 0xF8FFFFFF; }

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}
 Timer in LPC 2148
§ LPC has two timer units : Timer 0 and timer 1

§ Each timer module can either work in timer mode or in counter mode

Timer mode :

§ Objective: In Timer Mode, the Timer captures time intervals. It is used to create delays, trigger events after a
specified time, or generate periodic signals

§ Clock source: The clock source for Timer Mode is the PCLK (Peripheral Clock) of the microcontroller.

Operation:

§ The Timer's internal counter is incremented by each pulse from the PCLK, based on the pre-scaler value.

§ It can be configured the timer to generate interrupts after a certain value (e.g., Timer match register).

§ The timer register increments up to a pre-defined value or overflows and resets, creating a periodic event if
set up with interrupts

§ Use Case: Timer Mode is used when you need a precise delay or to generate periodic actions like blinking
an LED or controlling a PWM signal.
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 Timer in LPC 2148

Counter mode :

§ Objective: In Counter Mode, the timer counts the number of external events or pulses. It acts like a digital

counter and is used to count occurrences of an external signal.

§ Clock Source: In this mode, an external input pin acts as the clock source instead of the internal PCLK.

Operation:

§ The counter register increments whenever a pulse is detected at the external clock input.

§ The input signal must be applied at one of the designated Timer/Counter pins (e.g., CAP or MAT pins).

§ This mode is ideal for applications where the need is to measure or count the frequency or occurrence of an

external signal

§ Use case: Counter mode is used in scenarios like measuring rotational speed, counting the number of
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sensor pulses, or detecting events such as button presses
 Timer in LPC 2148

§ The timer module in LPC 2148 supports two advanced functionalities: Capture mode and Match mode

§ There are upto four 32 bit capture channels per timer and four 32 bit match registers

Capture mode :

Objective: In Capture mode, the timer captures the current value of the timer counter when a specific external

event (like a signal pulse) occurs

Operation :

§ The Timer has dedicated Capture input pins (e.g., CAP0.0, CAP0.1).

§ When an edge (rising or falling) is detected on the Capture pin, the value of the Timer Counter (TC) is copied

to the corresponding Capture Register (CR)

§ Configure whether to capture on a rising edge, falling edge, or both

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 Timer in LPC 2148

Match mode :

Objective: In Match mode, the timer counter value is compared with a predefined value, and specific actions
are performed when they match

Operation:

§ Match Registers (MR0, MR1) are used to specify the value that should be compared against the Timer

Counter (TC)

§ When the Timer Counter matches a value in the match register, several actions can be configured:

Generate an Interrupt: When the counter matches, an interrupt can be generated to perform specific actions

like toggling a pin or updating a value.

Reset the Timer: The timer can be reset to start counting again.

Stop the Timer: The timer can stop on a match, which is useful for one-shot timing operations

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Timer in LPC 2148

TCLK – Timer clock

§ The timer can be made to count faster

or slower by changing the value in the
prescaler register

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Registers associated with timer

1. T0CTCR (Timer0 Counter Control Register)

§ It is a 32 bit register

§ Used to select between timer counter mode

§ When in counter mode, it is used to select the pin and edges for counting.

Bits 1:0 – Counter/Timer Mode

§ This field selects which rising edges of PCLK can increment Timer’s Prescale Counter (PC), or clear PC and
increment Timer Counter (TC).

§ 00 = Timer Mode: Every rising edge of PCLK

§ 01 = Counter Mode (Rising edge): TC is incremented on rising edge on the capture input selected by Bits 3:2.

§ 10 = Counter Mode (falling edge) : TC is incremented on falling edge on the capture input selected by Bits
3:2

§ 11 = Counter Mode (Both rising and falling edge): TC is incremented on both edges on the capture input
selected by Bits 3:2 47
Registers associated with timer

1. T0CTCR (Timer0 Counter Control Register)

Bits 3:2 – Count Input Select

§ These bits determine which capture input to use for the external event counter

§ 00 = CAP0.0

§ 01 = CAP0.1

§ 10 = CAP0.2

§ 11 = CAP0.3

Bits 31:4 – Reserved

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Registers associated with timer

2. T0PR (Timer0 Prescale Register)

§ It is a 32-bit register

§ It holds the maximum value of the Prescale Counter

3. T0PC (Timer0 Prescale Counter Register)

§ It is a 32-bit register

§ It controls the division of PCLK by some constant value before it is applied to the Timer Counter

§ It is incremented on every PCLK

§ When it reaches the value in Prescale Register, the Timer Counter(TC) is incremented by 1 and Prescale
Counter is reset on next PCLK

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Registers associated with timer

4. T0TC (Timer0 Timer Counter)

§ It is a 32-bit timer counter
§ When the timer is Reset and enabled , TC is set to 0 and incremented by 1 every ‘PR+1’ clock cycles
§ It is incremented when the Prescale Counter (PC) reaches its maximum value held by Prescaler Register
(PR)
§ In short , TC will increment for every PR+1 clock cycles in PCLK
5.T0TCR (Timer 0 timer control register)
Bit 0 : used to enable or disable the timer.
§ Bit 0 = 1 enables the timer
§ Bit 0 = 0 disables the timer
Bit 1 : used for resetting the Timer Counter and Prescale Counter
§ Bit 1 =1 will reset the TC (Timer Counter) and PC (Prescale Counter) to 0 on the next positive edge of the
PCLK
§ The remaining bits are reserved and should not be modified 50
 Calculations in delay generation using timer

Find the no.of clock counts needed to generate a delay of 1

sec given that the input clock frequency for the timer unit
is 1 kHz

Solution :

Given that TCLK = 1KHz

Time of one clock period (𝑇!" + 𝑇!## ) is calculated as :

$ $
Time of one clock period = %&'(
= $))) = 1𝑚𝑠 ⟹ the delay

required for TC to increment by 1 is 1msec

Required delay to be generated = 1 sec = 𝑛 ∗ time of one

clock period

1
∴n= = 1000
1×10*+

i.e. 1000 clock counts provide a time interval of 1 second 51

 Steps in timer programming

1) Power Up the Timer Peripheral: Ensure that the Timer module is powered by configuring the Power
Control for Peripherals Register (PCONP)

2) Configure the Prescale Register: The Prescale Register (PR) is used to set the timer resolution. By
default, the timer increments every peripheral clock cycle (PCLK), but the Prescale Register is used to
to slow down the counting

3) Configure Timer Control Register (TCR): The TCR (Timer Control Register) controls enabling, disabling,
and resetting the Timer Counter (TC). To enable the timer, set bit 0 of TCR to 1

4) Wait for desired delay: Use the Timer Counter (TC) value to measure the elapsed time ; loop until the
desired count is reached

5) Once the desired count is reached , stop the timer

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 Steps in timer programming

1) Power Up the Timer Peripheral: Ensure that the Timer module is powered by configuring the Power
Control for Peripherals Register (PCONP)

2) Configure the Prescale Register: The Prescale Register (PR) is used to set the timer resolution. By
default, the timer increments every peripheral clock cycle (PCLK), but the Prescale Register is used to
to slow down the counting

3) Configure Timer Control Register (TCR): The TCR (Timer Control Register) controls enabling, disabling,
and resetting the Timer Counter (TC). To enable the timer, set bit 0 of TCR to 1

4) Wait for desired delay: Use the Timer Counter (TC) value to measure the elapsed time ; loop until the
desired count is reached

5) Once the desired count is reached , stop the timer

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 Steps in timer programming

Write an embedded C code to turn ON / turn OFF of an LED connected to P0.10 for every 1 sec. Use timer
0 module and take TCLK = 1 KHz

#include <lpc214x.h>

void initPLL(void); // Setup PLL and Clock Frequency

void initTimer0(void); // Setup and Initialize Timer0

void delay_ms(unsigned int counts); // Generate delay

int main(void)

initPLL(); //Initialize CPU and Peripheral Clocks @ 60Mhz

initTimer0(); //Initialize Timer0

IO0DIR = (1<<10); //Configure Pin P0.10 as Output

PCONP|=1<<1 ; // Power on the timer 0 module

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 Steps in timer programming

while(1) void initTimer0(void)

{ {
IO0SET = (1<<10); //Turn ON LED T0CTCR = 0x0; //Set Timer 0 into Timer Mode
delay_ms(1000); T0PR = 59999; //Increment T0TC at every 60000
IO0CLR = (1<<10); //Turn LED OFF clock cycles

delay_ms(1000); T0TCR |=0x00000001 ; //enable the timer

} T0TCR |=0x00000002; // Reset Timer counter and

preset counter
//return 0;
while (T0TC < 1000); // Wait for 1 second (1000 ms)
}
TOTCR &=~(0x00000001) ; // disabling the timer
}

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 Steps in timer programming

void initPLL()
{
PLL0CON=0X01;

PLL0CFG=0X04;
PLL0FEED=0XAA;
PLL0FEED=0X55;
while((PLL0STAT&(0X01<<10))==0);
PLL0CON=0X03;

PLL0FEED=0XAA;
PLL0FEED=0X55;
VPBDIV=0X01;
}

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 Programming with timer

Practice tasks :
1) Write an embedded C code that turns ON and OFF LEDs connected to P1.16 to P1.19 for every 100ms.The
delay has to be generated using timer 1. Take TCLK = 1 MHz.
2) Write an embedded C code to turn ON and OFF of LEDs connected to P1.16,P.17 and P1.19 for every 500
ms. Take TCLK = 1KHz. The delay has to be generated using timer 1 module.

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Timer in LPC 2148

58
Timer in LPC 2148

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