LTM4668A

Quad DC/DC µModule Regulator

with Configurable 1.2A Output Array
FEATURES DESCRIPTION
n Quad Output Step-Down µModule Regulator with The LTM®4668A is a quad DC/DC step-down µModule
1.2A per Output Channel (micromodule) regulator with 1.2A DC current per out-
n Wide Input Voltage Range: 2.7V to 17V put. Outputs can be paralleled in an array for up to 4.8A
n 0.6V to 5.5V Output Voltage capability. Included in the package are the switching
n 1.2A DC, Parallelable, Output Current Each Channel controllers, power FETs, inductors and support compo-
n ±1.5% Total Output Voltage Regulation nents. Operating over an input voltage range of 2.7V to
n 100% Duty Cycle Operation 17V, the LTM4668A supports an output voltage range of
n Current Mode Control, Fast Transient Response 0.6V to 5.5V. Only bulk input and output capacitors are
n External Frequency Synchronization needed. The device supports frequency synchronization,
n Selectable Burst Mode® Operation PolyPhase operation, selectable Burst Mode operation,
n Power Good Indicator 100% duty cycle and low IQ operation. Its high switching
n Over Voltage, Current and Temperature Protection frequency and a current mode architecture enables a very
n 6.25mm x 6.25mm x 2.1mm BGA Package fast transient response to line and load changes without
n Pin Compatible with LTM4668 (0.6V to 1.8V sacrificing stability.
Output, 1MHz).
Fault protection features include overvoltage, overcurrent
and overtemperature protection. The power module is
APPLICATIONS offered in a space saving and thermally enhanced 6.25mm
n Telecom, Networking and Industrial Equipment × 6.25mm × 2.1mm BGA package. The LTM4668A is avail-
n Multi-Rail Point of Load Regulation able with SnPb (BGA) or RoHS compliant terminal finish.
n FPGAs, DSPs and ASICs Application Configurable Output Array
All registered trademarks and trademarks are the property of their respective owners. 1.2A
2.4A
1.2A 3.6A
4.8A
1.2A 1.2A
1.2A 1.2A 1.2A

TYPICAL APPLICATION
5V to 17V Input, Quad 1.5V, 1.8V, 2.5V, 3.3V Output DC/DC µModule Regulator
3.3V Output Efficiency (Each Channel)
5V VIN VOUT1 100
1.5V/1.2A
to 17V 22µF VFB1 47µF 95
×2 6.3V
PGOOD1 40.2k
25V 90
LTM4668A
RUN1 VOUT2 2.5V/1.2A 85
EFFICIENCY (%)

RUN2 VFB2 47µF 80

RUN3 PGOOD2 19.1k 6.3V
75
RUN4
VOUT3 70
3.3V/1.2A
VFB3 47µF 65
PGOOD3 13.3k 6.3V 60
55 VIN = 5V
INTVCC VOUT4 1.8V/1.2A VIN = 12V
MODE VFB4 47µF 50
6.3V 0.0 0.2 0.4 0.6 0.8 1.0 1.2
GND PGOOD4 30.1k
LOAD CURRENT (A)
4668a TA01a
4668a TA01b

Rev. C

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LTM4668A
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
VIN.............................................................. –0.3V to 17V FB2 PGOOD3
FB3
VOUT (per Channel)....................................... –0.3V to 6V VOUT2
7 VOUT3
RUN (per Channel)...................................... –0.3V to 17V GND
PGOOD2
6 GND
PGOOD (per Channel)................................... –0.3V to 6V RUN2 RUN3
FB (per Channel).................................... –0.3V to INTVCC 5
MODE/SYNC.................................–0.3V to INTVCC+0.3V VIN
MODE/SYNC
4 VIN
Operating Junction Temperature (Note 2)... –40 to 125°C INTVCC RUN4
Storage Temperature Range....................... –55 to 125°C 3
RUN1 PGOOD1
Peak Solder Reflow Body Temperature.................. 260°C 2
PGOOD4
1 VOUT4
VOUT1
FB1 FB4

A B C D E F G

BGA PACKAGE
49-LEAD (6.25mm × 6.25mm × 2.1mm)
TJMAX = 125°C, θJCtop = 30.5°C/W,
θJCbottom = 7.4°C/W, θJA = 29.3°C/W,
Weight = 0.7g
θ VALUES DETERMINED PER JESD51-12

ORDER INFORMATION
PACKAGE MSL TEMPERATURE RANGE
PART NUMBER PAD OR BALL FINISH PART MARKING FINISH CODE TYPE RATING (SEE NOTE 2)
LTM4668AEY#PBF 4668A
SAC305 (RoHS) e1 BGA 4 –40°C to 125°C
LTM4668AIY#PBF 1Y
• Device temperature grade is indicated by a label on the shipping container. • This product is not recommended for second side reflow.
This product is moisture sensitive. For more information, go
• Pad or ball finish code is per IPC/JEDEC J-STD-609.
to Recommended BGA PCB Assembly and Manufacturing
• BGA Package and Tray Drawings Procedures.

Rev. C

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 LTM4668A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator Section: (Per Channel)
VIN Input DC Voltage l 2.7 17 V
VOUT(RANGE) Output Voltage Range VIN = 2.7V to 17V (Step-Down Only) l 0.6 5.5 V
VOUT(DC) Output Voltage, Total Variation with CIN = 10µF, COUT = 47µF Ceramic l 3.25 3.30 3.35 V
Line and Load RFB = 13.3k, MODE = INTVCC/2
VIN = 5V to 17V, IOUT = 0A to 1.2A
VRUN RUN Pin On Threshold VRUN Rising 0.55 0.7 0.9 V
IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 3.3V, MODE = INTVCC/2 (CCM) 75 mA
VIN = 12V, VOUT = 3.3V, MODE = INTVCC (Burst) 0.5 mA
VIN = 12V, VOUT = 3.3V, MODE = GND (PS) 200 µA
Shutdown, RUN = 0, VIN = 12V 1 µA
IS(VIN) Input Supply Current VIN = 12V, VOUT = 3.3V, IOUT = 1.2A 390 mA
IOUT(DC) Output Continuous Current Range VIN = 12V, VOUT = 3.3V (Note 4) 0 1.2 A
ΔVOUT (Line) Line Regulation Accuracy VOUT = 3.3V, VIN = 5V to 17V, IOUT = 0A l 0.01 0.1 %/V
VOUT
ΔVOUT (Load) Load Regulation Accuracy VOUT = 3.3V, IOUT = 0A to 1.2A l 0.1 0.75 %
VOUT
VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 47µF Ceramic 8 mV
VIN = 12V, VOUT = 3.3V
ΔVOUT(START) Turn-On Overshoot IOUT = 0A, COUT = 47µF Ceramic, 30 mV
VIN = 12V, VOUT = 3.3V
tSTART Turn-On Time COUT = 47µF Ceramic, VIN = 12V, VOUT = 3.3V, 0.8 ms
No Load
ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load 70 mV
COUT = 47µF Ceramic, VIN = 12V, VOUT = 3.3V
tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load 30 µs
COUT = 47µF Ceramic, VIN = 12V, VOUT = 3.3V
IOUTPK Output Current Limit VIN = 12V, VOUT = 3.3V 2 A
VFB Voltage at VFB Pin IOUT = 0A, VOUT = 3.3V l 0.591 0.60 0.609 V
IFB Current at VFB Pin (Note 3) ±10 nA
RFBHI Resistor Between VOUT and VFB Pins 60.05 60.40 60.75 kΩ
tON(MIN) Minimum On-Time (Note 5) 60 ns

Rev. C

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LTM4668A
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal
operating temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VPGOOD PGOOD Trip Level VFB With Respect to Set Output
VFB Ramping Negative –11 –7.5 %
VFB Ramping Positive 7.5 11 %
RPGOOD PGOOD Resistance 275 Ω
VINTVCC Internal VCC Voltage VIN = 6V to 17V 4.7 5 5.3 V
UVLO Undervoltage Lockout VIN Ramping Up 2.3 2.5 2.7 V
UVLO(HYS) UVLO Hysteresis 250 mV
fOSC Oscillator Frequency 2.25 MHz
SYNC SYNC Capture Range 1500 3000 kHz

Note 1: Stresses beyond those listed under Absolute Maximum Ratings with statistical process controls. The LTM4668AI is guaranteed to meet
may cause permanent damage to the device. Exposure to any Absolute specifications over the full –40°C to 125°C internal operating temperature
Maximum Rating condition for extended periods may affect device range. Note that the maximum ambient temperature consistent with
reliability and lifetime. these specifications is determined by specific operating conditions in
Note 2: The LTM4668A is tested under pulsed load conditions such conjunction with board layout, the rated package thermal resistance and
that TJ ≈ TA. The LTM4668AE is guaranteed to meet performance other environmental factors.
specifications over the 0°C to 125°C internal operating temperature Note 3: 100% tested at wafer level
range. Specifications over the full –40°C to 125°C internal operating Note 4: See output current derating curves for different VIN, VOUT and TA.
temperature range are assured by design, characterization and correlation Note 5: Guaranteed by design.

Rev. C

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 LTM4668A
TYPICAL PERFORMANCE CHARACTERISTICS
CCM, Burst and Pulse Skip Mode
Efficiency vs Load Current at 5VIN Efficiency vs Load Current at 12VIN Efficiency VIN = 12V, VOUT = 3.3V
100 100 100
96 96 90
92 92 80
88 88 70
EFFICIENCY (%)

EFFICIENCY (%)

EFFICIENCY (%)
84 84 60
80 80 50
76 76 40
72 72 1.8VOUT 30
68 68 2.5VOUT 20
1.8VOUT 3.3VOUT CCM
64 2.5VOUT 64 5VOUT 10 BURST MODE
3.3VOUT PULSE-SKIP MODE
60 60 0
0 0.1 0.2 0.4 0.5 0.6 0.7 0.8 1.0 1.1 1.2 0 0.1 0.2 0.4 0.5 0.6 0.7 0.8 1.0 1.1 1.2 0.001 0.01 0.1 1 10
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4668a G01 4668a G02 4668a G03

1.8V Output Transient Response 2.5V Output Transient Response

VOUT VOUT
50mV/DIV 50mV/DIV
AC-COUPLED AC-COUPLED

LOAD STEP LOAD STEP

CURRENT CURRENT
0.2A/DIV 0.2A/DIV

4668a G06 4668a G07

50µs/DIV 50µs/DIV
VIN = 12V, VOUT = 1.8V, fS = 2.25MHz VIN = 12V, VOUT = 2.5V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF CFF = 150pF
0.3A LOAD STEP 10A/µA 0.3A LOAD STEP 10A/µA

3.3V Output Transient Response 5V Output Transient Response

VOUT VOUT
50mV/DIV 50mV/DIV
AC-COUPLED AC-COUPLED

LOAD STEP LOAD STEP

CURRENT CURRENT
0.2A/DIV 0.2A/DIV

4668a G08 4668a G09

50µs/DIV 50µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz VIN = 12V, VOUT = 5V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF CFF = 150pF
0.3A LOAD STEP 10A/µA 0.3A LOAD STEP 10A/µA

Rev. C

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LTM4668A
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up Waveform without Start-Up Waveform with 1.2A Output Short-Circuit Waveform
Load Current Load Current without Load Applied

INPUT INPUT INPUT

CURRENT CURRENT CURRENT
0.2A/DIV 0.2A/DIV 0.5A/DIV
RUN RUN
10V/DIV 10V/DIV VOUT
2V/DIV
VOUT VOUT
2V/DIV 2V/DIV

4668a G10 4668a G11 4668a G12

500µs/DIV 500µs/DIV 20µs/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz VIN = 12V, VOUT = 3.3V, fS = 2.25MHz VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR COUT = 1× 47µF CERAMIC CAPACITOR COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF CFF = 150pF CFF = 150pF

Output Short-Circuit Waveform Steady-State Output

with 1.2A Load Current Applied Start-Up into Pre-Biased Output Voltage Ripple

INPUT INPUT
CURRENT CURRENT
0.5A/DIV 0.2A/DIV VOUT
5mV/DIV
RUN AC-COUPLED
VOUT 10V/DIV
2V/DIV
VOUT
2V/DIV

4668a G13 4668a G14 4668a G15

20µs/DIV 500µs/DIV 500ns/DIV
VIN = 12V, VOUT = 3.3V, fS = 2.25MHz VIN = 12V, VOUT = 3.3V, fS = 2.25MHz, VIN = 12V, VOUT = 3.3V, fS = 2.25MHz
COUT = 1× 47µF CERAMIC CAPACITOR OUTPUT PREBIASED TO 1.5V COUT = 1× 47µF CERAMIC CAPACITOR
CFF = 150pF COUT = 1× 47µF CERAMIC CAPACITOR CFF = 150pF
CFF = 150pF

Rev. C

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 LTM4668A
PIN FUNCTIONS
VIN (A4, B4, F4, G4): Power Input Pins connect to the 400mA peak current clamp. Tie MODE/SYNC to GND for
drain of the internal top MOSFET for each switching mode pulse-skipping operation, and tie MODE/SYNC to a volt-
regulator channel and the internal 5V regulator for the age between 1V and INTVCC – 1.2V for forced continuous
control circuitry. Apply input voltages between these mode. Furthermore, connecting this pin to an external
pins and GND pins. Recommend placing input decou- clock will synchronize the switch clock to the external
pling capacitance directly between each of VIN pins and clock and put the part in forced continuous mode. Do
GND pins. not float this pin.
VOUT1 (A1, B1), VOUT2 (A7, B7), VOUT3 (F7, G7), VOUT4 INTVCC (C4): Internal 5V Regulator Output. The internal
(F1, G1): Power Output Pins of each switching mode power drivers and control circuits are powered from this
regulator channel. Apply output load between these pins voltage. Decouple each pin to GND with a minimum of
and GND pins. Recommend placing output decoupling 2.2µF local low ESR ceramic capacitor. INTVCC only starts
capacitance directly between these pins and GND pins. up if at least one of the RUN pins is high.
See the Applications Information section for paralleling RUN1 (C3), RUN2 (C5), RUN3 (E5), RUN4 (E3): Run
outputs. Control Input of each switching mode regulator channel.
GND (A2–A3, A5–A6, B2–B3, B5–B6, C2, C6, D3–D5, Enable regulator operation by tying the specific RUN pin
E2, E6, F2–F3, F5–F6, G2–G3, G5–G6): Power Ground above 1V. Tying it below 0.35V shuts down the specific
Pins for both Input and Output Returns. Use large PCB regulator channel.
copper areas to connect all GND together. FB1 (C1), FB2 (C7), FB3 (E7), FB4 (E1): The Negative
PGOOD1 (D2), PGOOD2 (D6), PGOOD3 (D7), PGOOD4 Input of the Error Amplifier for each switching mode regu-
(D1): Output Power Good with Open-Drain Logic of each lator channel. Internally, this pin is connected to VOUT of
switching mode regulator channel. PGOOD is pulled to each channel with a 60.4kΩ precision resistor. Different
ground when the voltage on the FB pin is not within ±7.5% output voltages can be programmed with an additional
of the internal 0.6V reference. resistor between FB and GND pins. In PolyPhase® opera-
tion, connect FB pins for all slave channels to INTVCC and
MODE/SYNC (E4): Burst Mode Select and External Clock
Synchronization of the switching mode regulator. Tie connect VOUT for all paralleled channels together. See the
MODE/SYNC to INTVCC for Burst Mode operation with a Applications Information section for details.

Rev. C

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LTM4668A
BLOCK DIAGRAM
MODE/SYNC PGOOD1 100k
INTVCC
INTVCC VIN VIN
6V TO 17V
2.2µF 0.1µF 10µF

RUN1 1µH VOUT1 VOUT1

5V
1.2A
47µF
GND

60.4k
FB1

8.25k

PGOOD2 100k
INTVCC
VIN
VIN
0.1µF

RUN2 1µH VOUT2 VOUT2

2.5V
1.2A
47µF
GND

60.4k
FB2

19.1k

POWER CONTROL
PGOOD3 100k
INTVCC
VIN
VIN
0.1µF

RUN3 1µH VOUT3 VOUT3

3.3V
1.2A
47µF
GND

60.4k
FB3

13.3k

PGOOD4 100k
INTVCC
VIN
VIN
0.1µF

RUN4 1µH VOUT4 VOUT4

1.8V
1.2A
47µF
GND

60.4k
FB4

30.1k

4668a BD

Rev. C

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 LTM4668A
DECOUPLING REQUIREMENTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Regulator Section: (Per Channel)
CIN External Input Capacitor Requirement IOUT = 1.2A 4.7 10 µF
(VIN = 2.7V to 17V, VOUT = 1.5V)
COUT External Output Capacitor Requirement IOUT = 1.2A 22 47 µF
(VIN = 2.7V to 17V, VOUT = 1.5V)

OPERATION
The LTM4668A is a quad output standalone non-isolated Current mode control also provides cycle-by-cycle fast
switch mode DC/DC power supply. It has built-in four overcurrent protection. An internal overvoltage and
separate regulator channels and each of them can deliver undervoltage comparator pulls the open-drain PGOOD
1.2A continuous output current with few external input output low if the output feedback voltage exits a ±7.5%
and output capacitors. Each regulator provides precisely window around the regulation point. Furthermore, in an
regulated output voltage programmable via a single exter- overvoltage condition, internal top FET is turned off and
nal resistor over 2.7V to 17V input voltage range. The bottom FET is turned on and held on until the overvoltage
LTM4688A supports output voltages of 0.6V to 5.5V. The condition clears.
typical application schematic is shown in Figure 14. Pulling the RUN pin below 0.35V forces the controller
The LTM4668A uses a constant frequency, peak current into its shutdown state, turning off both power MOSFETs
mode architecture and has integrated power MOSFETs, and most of the internal control circuitry. At light load
inductors, and other supporting discrete components. currents, pulse-skipping mode or Burst Mode operation
The typical switching frequency is set to 2.25MHz. For can be enabled to achieve higher efficiency compared to
switching noise-sensitive applications, the µModule can continuous mode (CCM) by setting MODE/SYNC pin to
be externally synchronized to a clock from 1.5MHz to GND or INTVCC accordingly. The LTM4668A has internal
3MHz. See the Applications Information section. 800µs soft-start ramp on each output channel.
With current mode control and internal feedback loop The pin compatible part LTM4668 is recommended when
compensation, the LTM4668A module has sufficient sta- operating at a lower output voltage range of 0.6V to 1.8V
bility margins and good transient performance with a wide and has a typical switching frequency of 1MHz. The dif-
range of output capacitors, even with all ceramic output ferences between LTM4668 and LTM4668A are shown
capacitors. in Table 1.
Current mode control provides the flexibility of parallel- Table 1.
ing any of the separate regulator channels with accurate RECOMMENDED VOUT RANGE SWITCHING FREQUENCY
current sharing. With a built-in clock interleaving between LTM4668 0.6V to 1.8V 1MHz
each two regulator channels, the LTM4668A could easily LTM4668A 0.6V to 5.5V* 2.25MHz
employ a 2+2, 3+1 or all 4 channels, parallel operation *There are restrictions in the maximum VIN and VOUT step-down ratio. See
which is more than flexible in a multi-rail POL application. VIN to VOUT Step-Down Ratios section.

Rev. C

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LTM4668A
APPLICATIONS INFORMATION
The typical LTM4668A application circuit is shown in Table 2. VFB Resistor Table vs Various Output Voltages
Figure 14. External component selection is primarily deter- VOUT(V) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0
mined by the input voltage, the output voltage and the RFB(k) OPEN 90.9 60.4 40.2 30.1 19.1 13.3 8.25
maximum load current. Refer to Table 8 for specific exter-
nal capacitor requirements for a particular application. For parallel operation, a single resistor as determined by
the previous equation is used for RFB and is connected
VIN to VOUT Step-Down Ratios
from a master channel’s FB pin to GND. Tie the FB pins
There are restrictions in the maximum VIN and VOUT step- of the slave channels to INTVCC and tie the VOUT pins and
down ratio that can be achieved for a given input volt- the RUN pins together for all channels in parallel. See the
age due to the minimum on-time limits of each regulator Multi-Channel Parallel Operation section.
channel. The minimum on-time limit imposes a minimum
Input Decoupling Capacitors
duty cycle of the converter which can be calculated as:
The LTM4668A module should be connected to a low
DMIN = TON(MIN) • fSW
AC-impedance DC source. One piece of 4.7µF input
where TON(MIN) is the minimum on-time, 40ns typical for ceramic capacitor is required to be placed on each side of
LTM4668A. the module for RMS ripple current decoupling. Bulk input
In the cases where the minimum duty cycle is surpassed, capacitor is only needed when the input source imped-
pulse-skipping mode (MODE/SYNC = GND) or Burst ance is compromised by long inductive leads, traces or
Mode (MODE/SYNC = INTVCC) has to be implemented not enough source capacitance. The bulk capacitor can be
instead of forced-continuous mode operation in order to an electrolytic aluminum capacitor and polymer capacitor.
allow the LTM4668A to decrease switching frequency and Without considering the inductor current ripple, the RMS
maintain output voltage in regulation. The pin compatible current of the input capacitor can be estimated as:
module LTM4668 can also be used in high VIN, low VOUT
IOUT(MAX)
application to avoid minimum on time violation with its ICIN(RMS) = • D • (1− D)
1MHz default switching frequency. η%
The LTM4668A is able to run at 100% duty cycle opera- where η% is the estimated efficiency of the power module.
tion. As the duty cycle approaches 100%, the LTM4668A
enters dropout operation. During dropout, the top PMOS Output Decoupling Capacitors
switch is turned on continuously, and all active circuitry
With an optimized high frequency, high bandwidth design,
is kept alive.
only single piece of low ESR output ceramic capacitor is
Note that additional thermal derating may be applied. See required for each regulator channel to achieve low output
the Thermal Considerations and Output Current Derating voltage ripple and very good transient response. Additional
section in this data sheet. output filtering may be required by the system designer,
if further reduction of output ripples or dynamic transient
Output Voltage Programming spikes is required. Table 8 shows a matrix of different out-
The PWM controller has an internal 0.6V reference volt- put voltages and output capacitors to minimize the volt-
age. As shown in the Block Diagram, a 60.4k 0.5% internal age droop and overshoot during a 0.3A (25%) load step
feedback resistor connects each regulator channel VOUT transient. Multiphase operation will reduce effective output
and FB pin together. Adding a resistor RFB from FB pin to ripple as a function of the number of phases. Application
GND programs the output voltage: Note 77 discusses this noise reduction versus output rip-
ple current cancellation, but the output capacitance will be
60.4k + RFB more a function of stability and transient response. The
VOUT = 0.6V •
RFB LTpowerCAD® design tool is available to download online
Rev. C

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 LTM4668A
APPLICATIONS INFORMATION
for output ripple, stability and transient response analysis Force Continuous Current Mode (CCM)
and calculating the output ripple reduction as the number
In applications where fixed frequency operation is more
of phases implemented increases by N times. critical than low current efficiency, and where the low-
est output ripple is desired, forced continuous opera-
Burst Mode Operation
tion should be used. Forced continuous operation can
The LTM4668A is capable of Burst Mode operation in be enabled by tying the MODE pin to INTVCC/2. In this
which the power MOSFETs operate intermittently based mode, inductor current is allowed to reverse during low
on load demand, thus saving quiescent current. For appli- output loads, the output of the error amplifier is in control
cations where maximizing the efficiency at very light loads of the current comparator threshold throughout, and the
is a high priority, Burst Mode operation should be applied. top MOSFET always turns on with each oscillator pulse.
To enable Burst Mode operation, simply tie the MODE/
SYNC pin to INTVCC. During start-up, the module operates in pulse-skipped
mode regardless of the mode programmed on the MODE/
During Burst Mode operation, the peak current of the SYNC pin to prevent inductor current from reversing until
inductor is set to approximately 400mA in normal opera- the LTM4668A’s output voltage is in regulation.
tion even though the output of the error amplifier (COMP)
indicates a lower value. The COMP voltage drops when Operating Frequency
the inductor’s average current is greater than the load
The operating frequency of the LTM4668A is optimized
requirement. As the COMP voltage drops below 0.2V, the
to achieve the compact package size and the minimum
burst comparator trips, causing the internal sleep line to
output ripple voltage while keeping high efficiency. The
go high and turn off both power MOSFETs.
default operating frequency is internally set to 2.25MHz.
In sleep mode, the internal circuitry is partially turned In most applications, no additional frequency adjusting
off, reducing the quiescent current. The load current is is required.
now being supplied from the output capacitors. When the If any operating frequency other than 2.25MHz is required
output voltage drops, causing COMP voltage to rise, the by application, the µModule can be externally synchro-
internal sleep line goes low, and the LTM4668A resumes nized to a clock from 1.5MHz to 3MHz.
normal operation. The next oscillator cycle will turn on
the top power MOSFET and the switching cycle repeats. Frequency Synchronization and Clock In
When all channels are in sleep mode, the LTM4668A mod- The power module has a phase-locked loop comprised
ule draws only 8µA of quiescent current from VIN. of an internal voltage controlled oscillator and a phase
detector. This allows all internal top MOSFET turn-on to
Pulse-Skipping Mode Operation be locked to the rising edge of the same external clock.
In applications where low output ripple and high efficiency The external clock frequency range must be within ±50%
at intermediate currents are desired, pulse-skipping mode around the 2.25MHz set frequency. A pulse detection cir-
should be used by grounding the MODE/SYNC pin. In cuit is used to detect a clock on the MODE/SYNC pin to
LTM4668A, pulse-skipping mode is implemented simi- turn on the phase-locked loop. The pulse width of the
larly to Burst Mode operation with the peak inductor cur- clock has to be at least 400ns. The clock high level must
rent set to be at least 66mA. This results in lower ripple be above 2V and clock low level below 0.3V. During the
than in Burst Mode operation with the trade-off of slightly start-up of the regulator, the phase-locked loop function
lower efficiency. is disabled. And once engaged in frequency sync, the
LTM4668A runs in forced continuous mode at the exter-
Both modes, Burst Mode operation and pulse-skipping
nal clock frequency.
mode, automatically switch from continuous operation to
the selected mode when the load current is low.
Rev. C

For more information www.analog.com 11

LTM4668A
APPLICATIONS INFORMATION
Multi-Channel Parallel Operation A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
For the application that demands more than 1.5A of out-
capacitors. The RMS input ripple current is reduced by,
put current, the LTM4668A multiple regulator channels
and the effective ripple frequency is multiplied by, the
can be easily paralleled to provide more output current
number of phases used (assuming that the input volt-
without increasing input and output voltage ripples. The
age is greater than the number of phases used times
LTM4668A has preset built-in 180° phase shift between
the output voltage). The output ripple amplitude is also
channel 1, 2 and 3, 4 which is suitable to employ a 2+2,
3+1 or 4 channel parallel operation. Table 3 gives the reduced by the number of phases used when all of the
phase difference between regulator channels. outputs are tied together to achieve a single high output
current design.
Table 3. Phase Difference Between Regulator Channels
CHANNEL CH1 CH2 CH3 CH4 The LTM4668A device is an inherently current mode con-
Phase Diff. 0° 180° 0°
trolled device, so parallel modules will have very good
current sharing. This will balance the thermals on the
design. When configuring the LTM4668A for parallel
Figure 1 shows a 2+2 and a 4-channels parallel concept operation, channels 1 and 4 serve as master channels
schematics for clock phasing. to slave channels 2 and 3, respectively. To configure a
channel as a slave, tie its FB pin to INTVCC to shut down
INTVCC INTVCC

FB1 RUN1 FB2 RUN2 FB3 RUN3 FB4 RUN4

CH1 0° CH2 CH3 0° CH4

(0°) (0°) (180°) (180°)

VOUT1 VOUT2 VOUT3 VOUT4

LTM4668A

2.4A 2.4A

INTVCC INTVCC INTVCC

FB1 RUN1 FB2 RUN2 FB3 RUN3 FB4 RUN4

CH1 0° CH2 0° CH3 0° CH4

(0°) (0°) (0°) (0°)

VOUT1 VOUT2 VOUT3 VOUT4

LTM4668A
4668a F01

4.8A

Figure 1. 2+2 and 4-Channel Parallel Concept Schematic

Rev. C

12 For more information www.analog.com

 LTM4668A
APPLICATIONS INFORMATION
its control circuitry. The master channel’s drive signal is Input RMS Ripple Current Cancellation
used instead to drive the slave channel’s power switches. Application Note 77 provides a detailed explanation of
Then, to complete configuration, tie its VOUT to the master multiphase operation. The input RMS ripple current can-
channel VOUT and its RUN pin to the master channel’s cellation mathematical derivations are presented, and
RUN pin. Channel 2 and 3 cannot be tied together to pro-
a graph is displayed representing the RMS ripple cur-
vide a dual channel single output. For a three-channel rent reduction as a function of the number of interleaved
single-output, or four-channel single-output, channel 1
phases. Figure 2 shows this graph.
is used as the master channel. Table 4 lists the recom-
mended channel combinations for multi-channel parallel Soft-Start and Output Voltage Tracking
operation. In parallel output application, use the master
channel’s PGOOD signal as the power good indicator. Do The LTM4668A has an internal 800µs soft-start ramp for
not tie PGOOD pins together. each channel. During soft-start operation, the switcher
operates in pulse-skipping mode regardless of the mode
Table 4. Configuration of Multi-Channel Parallel Operation
programmed on the MODE/SYNC pin. Once the soft-start
NUMBER OF OUTPUT PARALLELING MASTER PGOOD
VOLTAGE RAILS CHANNEL CHANNEL INDICATOR period is complete, the part will transition into the desired
QUAD 1/2/3/4
mode of operation.
TRIPLE (1+2)/3/4 1 PGOOD1
Power Good
DUAL (1+2)/(3+4) 1, 4 PGOOD1, 4
DUAL (1+2+4)/3 1 PGOOD1 The PGOOD pins are open drain pins that can be used to
SINGLE (1+2+3+4) 1 PGOOD1 monitor valid output voltage regulation. This pin monitors

0.60
1-PHASE
0.55 2-PHASE
3-PHASE
4-PHASE
0.50 6-PHASE

0.45

0.40
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN) 4668a F02

Figure 2. Input RMS Current Ratios to DC Load Current as a Function of Duty Cycle
Rev. C

For more information www.analog.com 13

LTM4668A
APPLICATIONS INFORMATION
a ±7.5% window around the regulation point. A resistor Surface Mount Package Thermal Measurements”). The
can be pulled up to a particular supply voltage for moni- motivation for providing these thermal coefficients in
toring. To prevent unwanted PGOOD glitches during tran- found in JESD51-12 (“Guidelines for Reporting and Using
sients or dynamic VOUT changes, the LTM4668A’s PGOOD Electronic Package Thermal Information”).
falling edge includes a blanking delay of approximately 32 Many designers may opt to use laboratory equipment and
switching cycles. a test vehicle such as the demo board to anticipate the
µModule regulator’s thermal performance in their appli-
Stability Compensation
cation at various electrical and environmental operating
The LTM4668A module internal compensation loop of conditions to compliment any FEA activities. Without
each regulator channel is designed and optimized for low FEA software, the thermal resistances reported in the
ESR ceramic output capacitors only application. Table 6 Pin Configuration section are in-and-of themselves not
is provided for most application requirements. In cases relevant to providing guidance of thermal performance;
that require bulk output capacitors for output ripple or instead, the derating curves provided in the data sheet can
dynamic transient spike reduction, an additional 10pF to be used in a manner that yields insight and guidance per-
15pF phase boost cap is recommended between VOUT taining to one’s application usage, and can be adapted to
and FB pins. The LTpowerCAD design tool is available to correlate thermal performance to one’s own application.
download for control loop optimization.
The Pin Configuration section typically gives four thermal
Run Enable coefficients explicitly defined in JESD51-12; these coef-
ficients are quoted or paraphrased below:
Pulling the RUN pin of each regulator channel to ground
forces the regulator into its shutdown state, turning off 1. θJA, the thermal resistance from junction to ambient,
both power MOSFETs and most of its internal control cir- is the natural convection junction-to-ambient air ther-
cuitry. Bringing the RUN pin above 1V will turn on the mal resistance measured in a one cubic foot sealed
entire regulator channel. enclosure. This environment is sometimes referred to
as “still air” although natural convection causes the
VIN Overvoltage Protection air to move. This value is determined with the part
mounted to a JESD51-9 defined test board, which
The LTM4668A module constantly monitors the VIN
does not reflect an actual application or viable operat-
pins for an overvoltage condition. When VIN rises above
ing condition.
19V, the corresponding regulator suspends operation by
shutting off both power MOSFETs. Once VIN drops below 2. θJCbottom, the thermal resistance from junction to the
18.7V, the regulator immediately resumes normal opera- bottom of the product case, is determined with all of
tion. The regulators execute soft-start function when exit- the component power dissipation flowing through the
ing an overvoltage condition. bottom of the package. In the typical µModule regulator,
the bulk of the heat flows out the bottom of the pack-
Thermal Considerations and Output Current Derating age, but there is always heat flow out into the ambient
The thermal resistances reported in the Pin Configuration environment. As a result, this thermal resistance value
section of the data sheet are consistent with those param- may be useful for comparing packages, but the test
eters defined by JESD51-9 and are intended for use with conditions don’t generally match the user’s application.
finite element analysis (FEA) software modeling tools that 3. θJCtop, the thermal resistance from junction to top of
leverage the outcome of thermal modeling, simulation the product case, is determined with nearly all of the
and correlation to hardware evaluation performed on a component power dissipation flowing through the top
µModule package mounted to a hardware test board— of the package. As the electrical connections of the
also defined by JESD51-9 (“Test Boards for Area Array typical µModule are on the bottom of the package, it
Rev. C

14 For more information www.analog.com

 LTM4668A
APPLICATIONS INFORMATION
is rare for an application to operate such that most of θJCbottom, respectively. In practice, power loss is ther-
the heat flows from the junction to the top of the part. mally dissipated in both directions away from the pack-
As in the case of θJCbottom, this value may be useful age—granted, in the absence of a heat sink and airflow,
for comparing packages but the test conditions don’t a majority of the heat flow is into the board.
generally match the user’s application. Within a SIP (system-in-package) module, be aware there
4. θJB, the thermal resistance from junction to the printed are multiple power devices and components dissipating
circuit board, is the junction-to-board thermal resis- power, with a consequence that the thermal resistances
tance where almost all of the heat flows through the relative to different junctions of components or die are not
bottom of the µModule and into the board, and is really exactly linear with respect to total package power loss. To
the sum of the θJCbottom and the thermal resistance of reconcile this complication without sacrificing modeling
the bottom of the part through the solder joints and simplicity—but also, not ignoring practical realities—an
through a portion of the board. The board tempera- approach has been taken using FEA software modeling
ture is measured a specified distance from the pack- along with laboratory testing in a controlled-environment
age, using a two sided, two layer board. This board is chamber to reasonably define and correlate the thermal
described in JESD51-9. resistance values supplied in this data sheet: (1) Initially,
A graphical representation of the aforementioned ther- FEA software is used to accurately build the mechanical
mal resistances is given in Figure 3; blue resistances are geometry of the µModule and the specified PCB with all
of the correct material coefficients along with accurate
contained within the μModule regulator, whereas green
power loss source definitions; (2) this model simulates
resistances are external to the µModule.
a software-defined JEDEC environment consistent with
As a practical matter, it should be clear to the reader that JESD51-9 to predict power loss heat flow and temperature
no individual or sub-group of the four thermal resistance readings at different interfaces that enable the calculation
parameters defined by JESD51-12 or provided in the of the JEDEC-defined thermal resistance values; (3) the
Pin Configuration section replicates or conveys normal model and FEA software is used to evaluate the µModule
operating conditions of a μModule. For example, in nor- with heat sink and airflow; (4) having solved for and ana-
mal board-mounted applications, never does 100% of lyzed these thermal resistance values and simulated vari-
the device’s total power loss (heat) thermally conduct ous operating conditions in the software model, a thor-
exclusively through the top or exclusively through bottom ough laboratory evaluation replicates the simulated condi-
of the µModule—as the standard defines for θJCtop and tions with thermocouples within a controlled-environment

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT

RESISTANCE RESISTANCE

JUNCTION-TO-BOARD RESISTANCE
JUNCTION AMBIENT

JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT

(BOTTOM) RESISTANCE RESISTANCE RESISTANCE

4668a F03
µMODULE DEVICE

Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients

Rev. C

For more information www.analog.com 15

LTM4668A
APPLICATIONS INFORMATION
chamber while operating the device at the same power are maintained at 120°C maximum while lowering output
loss as that which was simulated. An outcome of this current or power with increasing ambient temperature.
process and due-diligence yields a set of derating curves The decreased output current will decrease the internal
provided in other sections of this data sheet. After these module loss as ambient temperature is increased. The
laboratory test have been performed and correlated to monitored junction temperature of 120°C minus the ambi-
the µModule model, then the θJB and θBA are summed ent operating temperature specifies how much module
together to correlate quite well with the µModule model temperature rise can be allowed.
with no airflow or heat sinking in a properly define cham- As an example, in Figure 11 the load current is derated to
ber. This θJB + θBA value is shown in the Pin Configuration
~3.75A at ~80°C with no air or heat sink and the power
section and should accurately equal the θJA value because loss for the 12V to 3.3V at 3.75A output is about 2.6W. The
approximately 100% of power loss flows from the junc- 2.6W loss is calculated with the ~2W room temperature
tion through the board into ambient with no airflow or top
loss from the 12V to 3.3V power loss curve at 3.75A, and
mounted heat sink.
the 1.3 multiplying factor at 125°C junction. If the 80°C
The 1.8V, 3.3V and 5V power loss curves in Figures 4 to 6 ambient temperature is subtracted from the 120°C junc-
can be used in coordination with the load current derating tion temperature, then the difference of 40°C divided by
curves in Figures 7 to 12 for calculating an approximate 2.6W equals a 15.3°C/W θJA thermal resistance. Table 5
θJA thermal resistance for the LTM4668A with various air- specifies a 15°C/W value which is very close.
flow conditions. The power loss curves are taken at room
Table 5 to Table 7 provide equivalent thermal resistances
temperature, and are increased with multiplicative factors
for 1.8V, 3.3V and 5V outputs with and without airflow.
of 1.3 considering both MOSFET RDS(ON) and inductor The derived thermal resistances in Table 5 and Table 6
DCR increases at 120°C junction temperature when the for the various conditions can be multiplied by the calcu-
derating starts. The derating curves are plotted with the lated power loss as a function of ambient temperature to
output current starting at 4.8A with all 4 channels paral- derive temperature rise above ambient, thus maximum
leled together and the ambient temperature at 40°C. The junction temperature. Room temperature power loss
output voltages are 1.8V, 3.3V and 5V. These are chosen can be derived from the efficiency curves in the Typical
to include the lower and higher output voltage ranges for Performance Characteristics section and adjusted with
correlating the thermal resistance. Thermal models are the above ambient temperature multiplicative factors. The
derived from several temperature measurements in a con- printed circuit board is a 1.6mm thick six layer board with
trolled temperature chamber along with thermal modeling two ounce copper for the two outer layers and one ounce
analysis. The junction temperatures are monitored while
copper for the four inner layers. The PCB dimensions are
ambient temperature is increased with and without air-
94mm × 100mm.
flow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions

Rev. C

16 For more information www.analog.com

 LTM4668A
APPLICATIONS INFORMATION
3.0 3.0 3.0
VIN = 3.3V VIN = 5V VIN = 12V
VIN = 5V VIN = 12V
2.5 VIN = 12V 2.5 2.5

2.0 2.0 2.0

POWER LOSS (W)

POWER LOSS (A)

POWER LOSS (A)

1.5 1.5 1.5

1.0 1.0 1.0

0.5 0.5 0.5

0 0 0
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4668a F04 4668a F05 4668a F06

Figure 4. 1.8V Output Power Loss Figure 5. 3.3V Output Power Loss Figure 6. 5V Output Power Loss

5.0 5.0 5.0

4.5 4.5 4.5
4.0 4.0 4.0
3.5 3.5 3.5
LOAD CURRENT (A)
LOAD CURRENT (A)

LOAD CURRENT (A)

3.0 3.0 3.0
2.5 2.5 2.5
2.0 2.0 2.0
1.5 1.5 1.5
1.0 1.0 0LFM 1.0
0LFM 0LFM
0.5 200LFM 0.5 200LFM 0.5 200LFM
400LFM 400LFM 400LFM
0 0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4668a F07 4668a F08 4668a F09

Figure 7. 3.3V to 1.8V Derating Figure 8. 5V to 1.8V Derating Figure 9. 12V to 1.8V Derating
Curve, No Heat Sinking Curve, No Heat Sinking Curve, No Heat Sinking

5.0 5.0 5.0

4.5 4.5 4.5
4.0 4.0 4.0
3.5 3.5 3.5
LOAD CURRENT (A)

LOAD CURRENT (A)

LOAD CURRENT (A)

3.0 3.0 3.0

2.5 2.5 2.5
2.0 2.0 2.0
1.5 1.5 1.5
1.0 0LFM 1.0 0LFM 1.0 0LFM
0.5 200LFM 0.5 200LFM 0.5 200LFM
400LFM 400LFM 400LFM
0 0 0
30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4668a F10 4668a F11 4668a F12

Figure 10. 5V to 3.3V Derating Figure 11. 12V to 3.3V Derating Figure 12. 12V to 5V Derating
Curve, No Heat Sinking Curve, No Heat Sinking Curve, No Heat Sinking

Rev. C

For more information www.analog.com 17

LTM4668A
APPLICATIONS INFORMATION
Table 5. 1.8V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK ΘJA (°C/W)
Figures 7, 8, 9 3.3, 5, 12 Figure 4 0 None 15
Figures 7, 8, 9 3.3, 5, 12 Figure 4 200 None 13
Figures 7, 8, 9 3.3, 5, 12 Figure 4 400 None 12

Table 6. 3.3V Output

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK ΘJA(°C/W)
Figures 10, 11 5, 12 Figure 5 0 None 15
Figures 10, 11 5, 12 Figure 5 200 None 13
Figures 10, 11 5, 12 Figure 5 400 None 12

Table 7. 5V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK ΘJA(°C/W)
Figure 12 12 Figure 6 0 None 15
Figure 12 12 Figure 6 200 None 13
Figure 12 12 Figure 6 400 None 12

Table 8. Output Voltage Response vs Component Matrix (Refer to Figure 14) 0A to 0.3A Load Step Typical Measured Values
CIN CERAMIC VENDORS VALUE PART NUMBER COUT CERAMIC VENDORS VALUE PART NUMBER
MURATA 22µF, 25V GRM21BR61E226ME44L MURATA 47µF, 6.3V GRM21BR60J476ME15
TAIYO YUDEN 22µF, 25V TMK316BBJ226ML-T TAIYO YUDEN 47µF, 6.3V JMK212BJ476MG-T

P-P LOAD STEP

VOUT CIN CIN COUT1 COUT2 CFF VIN DROOP DERIVATION RECOVERY LOAD SLEW RATE RFB
(V) (CERAMIC) (BULK) (CERAMIC) (BULK) (pF) (V) (mV) (mV) TIME (µs) STEP (A) (A/µs) (kΩ)
1.8 20µF NA 47µF NA 150 5, 12 0 56 30 0.3 10 30.1
2.5 20µF NA 47µF NA 150 5, 12 0 61 35 0.3 10 19.1
3.3 20µF NA 47µF NA 150 5, 12 0 68 40 0.3 10 13.3
5 20µF NA 47µF NA 150 12 0 92 50 0.3 10 8.25
1 20µF NA 47µF NA 150 5 0 48.2 13 0.3 10 90.9
1.2 20µF NA 47µF NA 150 5 0 48.9 15 0.3 10 60.4
1.5 20µF NA 47µF NA 150 5 0 51.5 20 0.3 10 40.2

Rev. C

18 For more information www.analog.com

 LTM4668A
APPLICATIONS INFORMATION
Safety Considerations • Place a dedicated power ground layer underneath
the unit.
The LTM4668A modules do not provide galvanic isolation
from VIN to VOUT. There is no internal fuse. If required, • To minimize the via conduction loss and reduce module
a slow blow fuse with a rating twice the maximum input thermal stress, use multiple vias for interconnection
current needs to be provided to protect each unit from between top layer and other power layers.
catastrophic failure. The device does support thermal • Do not put vias directly on the pad, unless they are
shutdown and overcurrent protection. capped or plated over.
Layout Checklist/Example • Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
The high integration of LTM4668A makes the PCB board
layout very simple and easy. However, to optimize its to GND underneath the unit.
electrical and thermal performance, some layout consid- • For parallel modules, tie the VOUT, VFB and COMP pins
erations are still necessary. together. Use an internal layer to closely connect these
• Use large PCB copper areas for high current paths, pins together. The TRACK pin can be tied a common
including VIN, GND, VOUT1 and VOUT2. It helps to mini- capacitor for regulator soft-start.
mize the PCB conduction loss and thermal stress. • Bring out test points on the signal pins for monitoring.
• Place high frequency ceramic input and output capaci- Figure 13 gives a good example of the recommended
tors next to the VIN, PGND and VOUT pins to minimize layout.
high frequency noise.

VOUT2 VOUT3

GND VIN VIN GND

VOUT1 VOUT4

4668a F13

Figure 13. Recommended PCB Layout

Rev. C

For more information www.analog.com 19

LTM4668A
TYPICAL APPLICATIONS
PGOOD1 PGOOD2 PGOOD3 PGOOD4

VIN VIN PGOOD1 PGOOD2 PGOOD3 PGOOD4 VOUT1 VOUT1

6V TO 17V 3.3V/1.2A
22µF VFB1 47µF
25V 13.3k 6.3V

VOUT2
RUN1 VOUT2
2V/1.2A
RUN2 VFB2 47µF
RUN3 25.5k 6.3V
RUN4 LTM4668A
VOUT3 VOUT3
5V/1.2A
VFB3 47µF
8.25k 6.3V

INTVCC VOUT4 VOUT4

1.8V/1.2A
MODE/SYNC VFB4 47µF
GND 30.1k 6.3V
4668a F14

Figure 14. 6V to 17V Input, 3.3V, 2V, 5V, 1.8V Output at 1.2A Design

PGOOD1 PGOOD2 PGOOD3 PGOOD4

VIN VIN PGOOD1 PGOOD2 PGOOD3 PGOOD4 VOUT1 VOUT1

5V TO 17V 1.0V/2.4A
22µF VFB1 47µF
25V 90.9k 6.3V

RUN1 VOUT2
RUN2 VFB2 INTVCC
RUN3
RUN4 LTM4668A
VOUT3
VFB3 INTVCC

INTVCC INTVCC VOUT4 VOUT2

3.3V/2.4A
MODE/SYNC VFB4 47µF
GND 13.3k 6.3V
4668a F15

Figure 15. 5V to 17V Input, 1V and 3.3V Output at 2.4A Design with Pulse-Skipping Mode

PGOOD1 PGOOD2 PGOOD3 PGOOD4

VIN VIN PGOOD1 PGOOD2 PGOOD3 PGOOD4 VOUT1 VOUT

2.7V TO 17V 1.8V/4.8A
22µF VFB1 47µF
25V 30.1k 6.3V
×2

RUN1 VOUT2
RUN2 VFB2 INTVCC
RUN3
RUN4 LTM4668A
VOUT3
VFB3 INTVCC

INTVCC INTVCC VOUT4

MODE/SYNC VFB4 INTVCC
GND
4668a F16

Figure 16. 2.7V to 17V Input, Four Phase Parallel Single Output 1.8V at 4.8A Design
Rev. C

20 For more information www.analog.com

 LTM4668A
PACKAGE DESCRIPTION
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.

Table 9. LTM4668A Component BGA Pinout

PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME
A1 VOUT1 B1 VOUT1 C1 FB1 D1 PGOOD4 E1 FB4 F1 VOUT4 G1 VOUT4
A2 GND B2 GND C2 GND D2 PGOOD1 E2 GND F2 GND G2 GND
A3 GND B3 GND C3 RUN1 D3 GND E3 RUN4 F3 GND G3 GND
A4 VIN B4 VIN C4 INTVCC D4 GND E4 MODE/SYNC F4 VIN G4 VIN
A5 GND B5 GND C5 RUN2 D5 GND E5 RUN3 F5 GND G5 GND
A6 GND B6 GND C6 GND D6 PGOOD2 E6 GND F6 GND G6 GND
A7 VOUT2 B7 VOUT2 C7 FB2 D7 PGOOD3 E7 FB3 F7 VOUT3 G7 VOUT3

Rev. C

For more information www.analog.com 21

 BGA Package
49-Lead (6.25mm × 6.25mm × 2.10mm)

22
(Reference LTC DWG# 05-08-1600 Rev Ø)

Z
Z
A1 A DETAIL A SEE NOTES
6
ccc Z A2 SEE NOTES 7 6 5 4 3 2 1
2× aaa Z
3 PIN 1
LTM4668A

PIN “A1”
CORNER b B
b1
4 MOLD
C
CAP
SUBSTRATE
D F D
H1
H2 E
e
F
PACKAGE DESCRIPTION

DETAIL B

// bbb Z
G

Øb (49 PLACES)
X b e
ddd M Z X Y
E Y eee M Z G
DETAIL B
PACKAGE TOP VIEW

aaa Z
PACKAGE SIDE VIEW PACKAGE BOTTOM VIEW

2×
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS
DETAIL A 3 BALL DESIGNATION PER JEP95
4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
DIMENSIONS BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.

2.4
1.6
0.8
0.000
0.8
1.6
2.4
THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR

For more information www.analog.com

SYMBOL MIN NOM MAX NOTES
MARKED FEATURE
A 1.90 2.10 2.30
0.40 ±0.025 Ø 49x 2.4
A1 0.30 0.40 0.50 BALL HT 5. PRIMARY DATUM -Z- IS SEATING PLANE
1.6 A2 1.60 1.70 1.80 6 PACKAGE ROW AND COLUMN LABELING MAY VARY
b 0.45 0.50 0.55 BALL DIMENSION ! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
0.8
b1 0.37 0.40 0.43 PAD DIMENSION LAYOUT CAREFULLY
0.000 D 6.25
E 6.25
0.8
e 0.80
1.6 F 4.80
2.4
G 4.80
H1 0.20 SUBSTRATE THK
H2 1.50 MOLD CAP HT LTMXXXXXX
SUGGESTED PCB LAYOUT µModule
TOP VIEW aaa 0.15
COMPONENT
bbb 0.10 PIN “A1”
ccc 0.20
ddd 0.15
TRAY PIN 1
eee 0.08 BEVEL
TOTAL NUMBER OF BALLS: 49 PACKAGE IN TRAY LOADING ORIENTATION
BGA 49 0917 REV Ø

Rev. C
 LTM4668A
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 02/20 Added ground symbol to Typical Application schematics. 1
MODE/SYNC pin description: Added “Do not float this pin”. 7
INTVCC pin description: Added “INTVCC only starts up if at least one of the RUN pins is high”. 7
Added clarification on VIN to VOUT step-down ratio on LTM466A. 9
Added clarification on PGOOD in multi-channel applications. 13
Table 5: Added 3 more lines for VOUT = 1V, 1.2V, 1.5V. 18
Edited Figure 14 and 15. 20
Edited Figure 16. 21
B 08/21 Edited description of θJCbottom on Thermal Considerations and Output Current Derating. 14
C 05/22 Updated Part Marking in the Order Information table. 2
Added ink marking statement to package photos. 24

Rev. C

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implication or otherwise under any patent or patent rights of Analog Devices. 23
LTM4668A
PACKAGE PHOTOS Part marking is either ink mark or laser mark

DESIGN RESOURCES
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design: Manufacturing:
• Selector Guides • Quick Start Guide
• Demo Boards and Gerber Files • PCB Design, Assembly and Manufacturing Guidelines
• Free Simulation Tools • Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.

Digital Power System Management Analog Devices’ family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTM4668 Quad 1.2A Step-Down µModule Regulator 2.7V ≤ VIN ≤ 17V, 0.6V ≤ VOUT ≤ 1.8V, 6.25mm × 6.25mm × 2.1mm BGA
LTM4622 Ultrathin, Dual 2.5A or Single 5A Step-Down µModule 3.6V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 1.82mm LGA,
Regulator 6.25mm × 6.25mm × 2.42mm BGA
LTM4622A Higher VOUT of LTM4622 3.6V ≤ VIN ≤ 20V, 1.2V ≤ VOUT ≤ 12V, 6.25mm × 6.25mm × 1.82mm LGA,
6.25mm × 6.25mm × 2.42mm BGA
LTM4623 Ultrathin, Single 3A Step-Down µModule Regulator 4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 1.82mm LGA,
6.25mm × 6.25mm × 2.42mm BGA
LTM4624 Single 4A Step-Down µModule Regulator 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 5.01mm BGA
LTM4625 Single 5A Step-Down µModule Regulator 4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5.5V, 6.25mm × 6.25mm × 5.01mm BGA
LTM4632 Ultrathin, Triple ±3A Step-Down µModule Regulator for 3.6V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 2.5V, 6.25mm × 6.25mm × 1.82mm LGA,
DDR Memory 6.25mm × 6.25mm × 2.42mm BGA
LTM4643 Ultrathin, Quad 3A Step-Down µModule Regulator 4V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 3.3V, 9mm × 15mm × 1.82mm LGA,
9mm × 15mm × 2.42mm BGA
LTM4644 Quad 4A Step-Down µModule Regulator 4V ≤ VIN ≤ 14V, 0.6V ≤ VOUT ≤ 5.5V, 9mm × 15mm × 5.01mm BGA

Rev. C

24
05/22
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