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Assignment4

This document outlines Assignment 4 for COEN 212 - Digital Systems Design I, focusing on combinational circuit design with a deadline of November 1st, 2024. It includes multiple design tasks such as implementing functions using various logic gate configurations, designing circuits for arithmetic operations, and creating a priority encoder. Submission instructions emphasize originality, step-by-step solutions, and the requirement to submit in PDF format via Moodle.

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lord4ethan
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4 views

Assignment4

This document outlines Assignment 4 for COEN 212 - Digital Systems Design I, focusing on combinational circuit design with a deadline of November 1st, 2024. It includes multiple design tasks such as implementing functions using various logic gate configurations, designing circuits for arithmetic operations, and creating a priority encoder. Submission instructions emphasize originality, step-by-step solutions, and the requirement to submit in PDF format via Moodle.

Uploaded by

lord4ethan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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COEN 212 - Digital Systems Design I - Fall 2024

Assignment 4 – Combinational circuit design


Deadline: Friday November 1st, 2024 at 11:59 pm
Note: Some questions are from the textbook

Submission instructions:
- Please include a statement of originality in your assignment, on top of your name and student ID.
- Please show all solution steps for each question. Note that only stating the final answers would
not result in any mark.
- Please convert your assignment to pdf format before submission.
- It is recommended that you state each question followed by its solution, so that you can ensure
that the marker won’t skip any of your solutions.
- Please submit your assignment through Moodle way before the deadline.

1. Consider the following function: (16 points)


𝐹(𝑥, 𝑦, 𝑧, 𝑤) = ∑(0,2,4,6,7,8,10)
Implement the function F with 2-level implementation, assuming inputs and their complements
are available as:
• AND-OR-NOT (4 pts.)
• NAND-AND (4 pts.)
• OR-AND-NOT (4 pts.)
• NOR-OR (4 pts.)
Indicate the solution steps that lead to each implementation.

2. Design a combinational circuit with a 4-bit input A (A3A2A1A0) and a 5-bit output B
(B4B3B2B1B0), where each value of B must be according to the following equation B = A × 2.
Your design must include a truth table, K-maps, simplified Boolean equations, and final circuit.
After you complete your design, indicate your comment. (10 points)

3. Design a combinational circuit that converts a 4-bit input to its 2’s complement form. (10
points)

4. Design each of the designs specified below. (10 points)


a) Design a half-subtractor circuit with inputs x and y and outputs Diff and 𝐵𝑜𝑢𝑡. The circuit
subtracts the bits x – y and places the difference in D and the borrow in Bout.
b) Design a full-subtractor circuit with three inputs x, y, Bin and two outputs Diff and Bout.
The circuit subtracts x – y – Bin, where Bin is the input borrow, Bout is the output borrow,
and Diff is the difference.
COEN 212 - Digital Systems Design I - Fall 2024

5. Design an 8-bit Adder/Subtractor with overflow detection using Full Adders. Assume the FA
block is already available, so no need for a truth table and a k-map.
Use the following 8-bit inputs A = 𝑎7 𝑎6 𝑎5 𝑎4 𝑎3 𝑎2 𝑎1 𝑎0 , B = 𝑏7 𝑏6 𝑏5 𝑏4 𝑏3 𝑏2 𝑏1 𝑏0, where A
and B are the numbers to be added or subtracted, and a one bit input M to indicate the mode
(adder or subtractor). In the case of subtraction, use A as the minuend and B is the subtrahend.
Use the following 8-bit output S = 𝑆7 𝑆6 𝑆5 𝑆4 𝑆3 𝑆2 𝑆1 𝑆0 to indicate the sum result, and the
one-bit output C for the final carry out, and the one-bit output V for overflow. (7×4 = 21 points)

In each of the following cases, determine the values of S, C, and V:


a) M = 0, A = 0111 0111, B = 0110 0110
b) M = 0, A = 1000 1000, B = 1001 1001
c) M = 1, A = 1100 1100, B = 1000 1000
d) M = 1, A = 0101 0101, B = 1010 1010
e) M = 1, A = 0000 0000, B = 0001 0001
f) M = 0, A = 0011 1001, B = 1101 0001
g) M = 1, A = 0011 1001, B = 1101 0001

6. Implement the following function 𝐹(w,𝑥,𝑦,𝑧) = Σ(0,1,2,5,6,7,9,10,14) using a multiplexer. (11


points)

7. Consider the 4-input priority encoder explained in class. (23 points)


a) Reimplement (Redraw) the logic diagram using only NAND gates. (4 pts.)
b) Reimplement (Redraw) the logic diagram using only NOR gates. (4 pts.)
c) Using the online simulation tool CircuitVerse, apply various input values to the circuit
(original, NAND, and NOR) and show that the outputs will be as expected in all alternative
diagrams. Scan and include your simulation results. (15 pts.)

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