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Assignment5 (1)

The document outlines Assignment 5 for COEN 212 - Digital Systems Design I, due on November 11th, 2024. It includes various tasks related to combinational circuit design, such as creating logic diagrams, implementing functions using multiplexers, and designing encoders and decoders. Submission instructions emphasize the importance of originality, solution steps, and formatting before submitting through Moodle.

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8 views2 pages

Assignment5 (1)

The document outlines Assignment 5 for COEN 212 - Digital Systems Design I, due on November 11th, 2024. It includes various tasks related to combinational circuit design, such as creating logic diagrams, implementing functions using multiplexers, and designing encoders and decoders. Submission instructions emphasize the importance of originality, solution steps, and formatting before submitting through Moodle.

Uploaded by

lord4ethan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COEN 212 - Digital Systems Design I - Fall 2024

Assignment 5 – Combinational circuit design


Deadline: Monday November 11th, 2024 at 11:59 pm
Note: Some questions are from the textbook.

Submission instructions:
- Please include a statement of originality in your assignment, on top of your name and student ID.
- Please show all solution steps for each question. Note that only stating the final answers would not
result in any mark.
- Please convert your assignment to pdf format before submission.
- It is recommended that you state each question followed by its solution, so that you can ensure that
the marker won’t skip any of your solutions.
- Please submit your assignment through Moodle way before the deadline.

1. Draw the logic diagram of a 2-to-4-line decoder using (a) NOR gates only and (b) NAND gates
only. Include an enable input. Invertors are allowed. (5 points)

2. Using one decoder and external gates, design the combinational circuit defined by the following
three Boolean functions (10 points):
𝐹1(𝑥, 𝑦, 𝑧) = (𝑦 ′ + 𝑥)𝑧
𝐹2(𝑥, 𝑦, 𝑧) = 𝑦 ′ 𝑧 ′ + 𝑥 ′ 𝑦 + 𝑦𝑧′
𝐹3(𝑥, 𝑦, 𝑧) = (𝑥 + 𝑦)𝑧

3. Construct a 16 * 1 multiplexer with two 8 * 1 and one 2 * 1 multiplexer. Use block diagrams. (5
points)

4. Implement a full adder with two 4*1 multiplexers. (5 points)

5. Implement each of the following functions using a multiplexer. (10 points)


𝐹(𝑥, 𝑦, 𝑧) = ∑(0,2,5,7)
𝐹(𝑥, 𝑦, 𝑧, 𝑤) = 𝛱(0,5,13,15)

6. Design an eight-input priority encoder with input D0 having the highest priority and input D7 the
lowest priority. (10 points)

7. An 8 x 1 multiplexer has inputs A, B, and C connected to the selection inputs S2, S1, and S0,
respectively. The data inputs I0 through I7 for the functions F1 and F2 are as follows:
- For F1(A,B,C,D): I1 = I2 = I7 = 0; I3 = I5 = 1; I0 = I4 = D; and I6 = D’.
- For F2(A,B,C,D): I1 = I2 = 0; I3 = I7 = 1; I4 = I5 = D; and I0 = I6 = D’.
a) Show the multiplexer’s diagram for F1.
b) Show the multiplexer’s diagram for F2.
c) Determine the Boolean functions F1 and F2 that the multiplexer implements, and draw
their logic diagrams with the minimum number of gates. (15 points)
COEN 212 - Digital Systems Design I - Fall 2024

8. Design a digital circuit with the minimum number of gates with the 4-bit input 𝐴 = 𝑎3 𝑎2 𝑎1 𝑎0
and the 4-bit output 𝐵 = 𝑏3 𝑏2 𝑏1 𝑏0. Your design must be according to the following
specifications (15 points):
- If 𝐴 is 0, then 𝐵 must take a don’t care value.
- If 𝐴 is divisible by both 3 and 5, 𝐵 must take a don’t care value.
- If 𝐴 is divisible by 3 but not divisible by 5, then 𝐵 = 𝐴 ÷ 3.
- If 𝐴 is divisible by 5 but not divisible by 3, then 𝐵 = 𝐴 ÷ 5.
- If 𝐴 is not divisible by either 3 or 5, then 𝐵 = 𝐴 × 3. If this multiplication result exceeds
the maximum allowed range value, then 𝐵 must be replaced with a don’t care value.
a. Plot a truth table, K-maps, and derive the corresponding logic diagram. (Assume variables
and their complements are available). Your diagram must be a single circuit producing
all output bits of 𝐵.
b. Redraw the logic diagram of the circuit using only NAND gates. (Assume variables and
their complements are available)
c. Redraw the logic diagram of the circuit using only NOR gates. (Assume variables and
their complements are available)

9. Using the same design specifications in 8. above, design a decoder that provides the output 𝐵,
while replacing all don’t care values in its truth table with 1. (5 points)

10. Choose a question from this assignment’s questions above, and use the online simulation tool
(CircuitVerse) to draw the question’s schematic and simulate it by applying multiple inputs and
confirm sound outputs. Include your schematics and simulation results. (11 points)

11. Derive the state table and the state diagram of the sequential circuit shown in the given figure.
Explain the function that the circuit performs. (10 points).

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