Min H. Kao Dept.

of EECS University of Tennessee Knoxville

ECE 433 Introduction to VLSI

ECE 533 Introduction to VLSI Design
Fall 2024
Part 1: Lab Setup

In this lab, you will learn to use Cadence software to design analog circuits. Cadence is installed in the vlsi
systems (vlsi3 through vlsi11). To set up cadence, follow the instructions listed below. This is the initial
setup that you need to do only once.
Setting Up Cadence
Log in to server:
1. Download VNC Viewer, install and log into one of the vlsi (vlsi3 through vlsi11) servers. You will get
the download link, instructions for login here ( https://help.eecs.utk.edu/knowledge-base/general/remote-
access/vnc ).

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

2. After successful login, you should see the following window.

Note: To connect to the server from your personal PC (not connected to UTK network), you have to use
Pulse Secure VPN. Use this link (https://utk.teamdynamix.com/TDClient/2277/OIT-
Portal/KB/ArticleDet?ID=122938) to know how to connect to the VPN.
Creating the work area and setting it up.
After successful login, open the terminal (to open the terminal, right click on the previous window and
select the ‘Open in terminal’ option.). Now, type in the terminal:
mkdir my_directory (you can use any name instead of my_directory)
cd my_directory
mkdir Cadence
cd Cadence
cp /home/ece433/cadence_lab/setup_files/* ./
cp /home/ece433/cadence_lab/setup_files/.cdsinit ./
If you type
ls -a
you should see these files:

The above steps need to be done only once.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

The following needs to be done every time you want to run cadence:
Once you open your terminal, you need to
cd my_directory
cd Cadence
tcsh
source source_file
virtuoso &
The first window that appears is called the CIW (Command Interpreter Window).

Another window that is very handy is the Library Manager, which allows you to browse the available
libraries and create your own. To display this window, choose Tools -> Library Manager... from the CIW
Menu.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

In the Library Manager, create new library called “ADETutorial”. Select File->New->Library. This will open
new dialog window, in which you need to enter the name and directory for your library. By default, the library
will be created in the current directory. After you fill out the form, it should look something like this:

Click OK. Next, you will see a window asking you what technology you would like to attach to this library.
Select "Attach to an existing technology library" and click OK. In the next window, select
"NCSU_TechLib_FreePDK45".

You should see the library "ADETutorial" appear in the Library Manager.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Schematics
Next, select the library you just created in the Library Manager and select File->New->Cell View.... We will
create a schematic view of an inverter cell. Simply type in "myInverter" under cell-name and "schematic"
under view. Click OK or hit "Enter". Note that the "Application" is automatically set to "Schematics L", the
schematic editor.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Alternatively, you can select the "Schematics L" tool, instead of typing out the view name. This will
automatically set the view name to "schematic". Click Ok. You may see the following window. Simply click
Ok to ignore this warning.

After you hit "OK", the blank Composer screen will appear. You can now draw schematics using the buttons
on the toolbar above the black screen.
Schematic Generation:
You will first need to generate a schematic of your circuit. Press “I” and a library browser will pop up.
Generate the schematic as shown below. Most components will be in the “analogLib” and
“NCSU_Devices_FreePDK45” libraries. See the screenshots below to help guide you along the schematic
generation process. Drawing wires can be done with “W” shortcut and selecting a component and hitting “Q”
will bring up the property menu, where all parameters of the element can be changed. Also note that the
minimum length of the transistors is 50nm! Do not make your transistors 45nm as they will fail the design
rules during layout.

Complete Schematic is shown in the above picture.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Once you have the complete schematic with all the values you are ready to simulate your circuit.
Simulating the Circuit:
From the Schematic Window menu, select Launch -> ADE L. You may get another message saying that the
license need to be upgraded. Simply click YES to proceed. A window will pop-up. This window is the Analog
Design Environment Window.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Choose a Simulator.
From the Analog Artist menu, select Setup -> Simulator/Directory/Host. Enter the fields as shown below.
Choose spectre as your simulator. Your simulation will run in the specified Project Directory. You may
choose any valid pathname where to dump simulation results.

Next you will need to select the CMOS models and include them in the design environment. From the menu
select Setup -> Model Libraries. From there you will need to include the models.
The path of the model libraries is
/home/ece433/cadence_lab/pdk_ece433/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_nom
Include all the files in this directory.

Below are the screenshots showing what the outcome of adding all the right models is (Ignore the path in the
figure below). There are 4 transistor types. VLT is a low threshold device, VTG is a regular threshold device,
and VTH is a high threshold device. The low threshold voltage transistors are faster but have higher leakage.
The last flavor is a THKOX or thick oxide device.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Once the models and the simulation directories are setup you will need to select the simulation types you want
to run. From the menu again select Analyses->Choose.
Below is a capture for the transient simulation.

You will also need to run a DC simulation in order to observe static characteristics of the inverter. From the
menu copy the design variable that was defined in the input pulse source. Variables -> Copy From Cellview.
Next go to Analyses->Choose and select a DC simulation. The screenshot below shows what the end result
should look like.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

The last thing you want to do is plot the signals automatically. From the menu go to Outputs->To be Plotted
which will let you select the signals of interest. Select the input and output of the inverter and hit ESC. You
are now ready to run the simulation. Press the Green Play Butoon in the ADE-L GUI and the simulation
should run. If everything went well the output will be as follows. You can now measure the delays of the
inverter as well as its trip point.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Part 2 Introduction to Layout in FreePDK 45nm

(Adapted from http://www.eda.ncsu.edu/wiki/Tutorial:Layout_Tutorial#1 and

http://www.eda.ncsu.edu/wiki/Tutorial:Layout_Tutorial2 - Please reference these tutorials for any issues
you might have before contacting a TA)
Schematics are for verifying your design very roughly. They don‟t consider physical features like parasitic
capacitances. After determining your design variables by schematics, you need to draw layouts.
Design flow of layouts is very similar to one of schematics, but it has additional step which is LVS check. It
is for checking if your layout is identical to the schematic or not. Hence, this step is very important. If your
logic doesn’t pass this step, you may lose significant points for that.
1. Introduction
This is a guide for layout on FreePDK 45nm. It is recommended that you read through this document first
before attempting the steps.
2. Setting Calibre
If you followed the Cadence setup tutorial correctly you should be all set up to proceed with layout, DRC,
LVS, and Parasitic Extraction for your circuits.
Now you can start Cadence normally and proceed with this tutorial.
Starting the Layout
3. Create a new cell view:

Figure 1 and 2
Click Ok. You may see a warning about upgrading the license. Simply click Ok to ignore this warning. After
you hit "OK", the Virtuoso screen will appear as shown below. In addition, the LSW window (Layer Selection
Window), which shows various mask layers, will automatically pop up.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Figure 3
4. Laying out an Inverter
Some tips before you start:
You may notice that you might not be able to view all the hierarchy in the layout. To fix this hit E in the
layout window to get the Display Editor and set the maximum display level to 32 (from 0).
Another thing that you might want to do is turn off the gravity. Gravity will basically bring your cursor to the
closest edge which can be annoying at times. To turn the gravity off hit Shift-E in the layout window and
uncheck the Gravity On box.
NOTE: The NMOS and PMOS layout models (pcells) don’t work so you will need to draw all the
transistor layouts yourself!

Figure 4. A completed sample inverter layout

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Figure 5. The metals and poly

Figure 4 shows a completed inverter in FreePDK45. Create metal1 and poly for an inverter, as shown in
Figure 5. Note the little rectangles which indicate the pins (you can ignore them for now).

Figure 6: The Nwell and Pwell and implant

Using this approach, you should be able to figure out that the NMOS uses the following layers: pwell, active,
nimplant, poly, metal1, contact, and text. The PMOS is like it, except that it uses layers pimplant and nwell

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

instead of pwell and nimplant. Note also the letters "drw", "net", and "pin" next to each entry in the LSW.
These are the purposes of a shape. The purpose is used to indicate special functionality of a shape.
5. DRC
To perform a Design Rule Check (DRC), choose Calibre->Run DRC…. The DRC form appears, as shown
below. Go to the Rules tab, and change the DRC Rules File to
/home/ece433/cadence_lab/pdk_ece433/FreePDK45/ncsu_basekit/techfile/calibre/calibreDRC.rul
to point at the calibre rules file.. Now, load the calibreDRC.rul file. Then click "Run DRC".

Figure 7: DRC dialog window

Viewing DRC Errors
(Please refer to the DRC_Rules pdf file that was also uploaded to Canvas to understand the DRC rules
in more detail). You can learn about the errors by clicking on the rule in the Results Viewing Environment
(RVE) window that pops up after DRC is complete.

Figure 8. DRC RVE

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Keep modifying your layout until there are no errors. You will know that there are no errors when there are
no red boxes in the RVE. Alternatively, you can look in the file inv.drc.summary. When the layout is "DRC
Clean", the last line of this file should read "TOTAL DRC Results Generated: 0".
Lastly, we need to create pins so that the nodes in our layout have names that are human-readable. Create
these pins by selecting Create->Pin…. You should see a dialog box appear, like the one below. Type the
names vdd!, gnd!, in, and out in the “Terminal Names” text-box as shown below. Select “Display Pin Name”.
Leave all other options as they are.

Figure 9: Create Shape Pin

Next, click the “Display Pin Name Option…” button. You will see another dialog box appear

Figure 10: Pin Name Display

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Figure 11: The inverter DRC Clean

6. LVS
LVS checks your layout against your schematic. To perform a layout-vs.-schematic (LVS), choose
Calibre -> Run LVS.... The LVS form appears, as shown below.

Figure 12: LVS dialog box

There are a number of options you need to set and know what they are.
Rules: Go to the Rules tab, and change the LVS Rules File to
/home/ece433/cadence_lab/pdk_ece433/FreePDK45/ncsu_basekit/techfile/calibre/calibreLVS.rul

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

to point at the calibre rules file.

Inputs
• Select "Hierarchial", "Layout vs Netlist" Under the Layout tab
• Files : inv.calibre.gds(what names you did save as: inv would be changed) Top Cell: inv
• Layout Netlist: inv.sp
• These options are already be filled in by the tool, leave them as is
• Format: select "GDSII" and select the option "Export from layout viewer" (This is very important)
Under the Netlist tab
• Files: inv.src.net Top Cell:inv
• These options are already be filled in by the tool, leave them as it is
• Format: select "SPICE" and select the option "Export from schematic viewer" (This is very important)
Outputs
• Under the Report/SVDB
• LVS Report File: inv.lvs.report
• This option is already be filled in by the tool, leave it as is svdb directory: svdb_inv
• Select "View Report after LVS Finishes"
• Perform an LVS Check without Errors
• Set the LVS form with the options shown above. Then click the “Run LVS” button. If LVS runs
successfully, without any error, then you will see the below window with a Smilie :)
• Click on the "Transcript" tab in Calibre Interactive - LVS to see the log file.

Figure 13: LVS Report without errors

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

7. Extraction
The layout is just a picture. If you need to run simulation using the layout, you should convert it to the other
format. It is done by extracting. It’s something like compiling a code.
Create “extracted” view
In your library, open the layout view of the cell “Inv”. On the layout window click Verify -> Extract, and
then click OK. You can find the created extracted file in the library manager next to the other cell views of
Inverter as it is shown in Figure 15.

Figure 14. Extracting the design

Select “Extract_parastic_cap‟ as a switch name, otherwise your extracted design won‟t have parasitic
capacitances.

Figure 15. Library view with extracted design.

Fall 2024 ©Dr. Rakshith Saligram

Min H. Kao Dept. of EECS University of Tennessee Knoxville

Double click on extracted to open it. The extracted view should look like Figure 16.

Figure 16. Extracted View

Post layout Simulation

1. The post layout simulation is very similar to the schematic simulation. You need to open the schematic
view of the “Inv” and follow all the steps of the schematic simulation. Or, you may have saved previous
state, Session a Load state, usually the default the last state you saved. If you didn’t save, you may have
to follow above set up steps. The only difference is that you need to click Setup -> Environment and
type “extracted” before the word schematic in the switch view list.
2. That is, you first have to select “spectre” as your simulator, add the model libraries and then use the
extracted file for your simulation from Environment setting. You also need to choose the transient analysis
and select the outputs to be plotted on schematic to run the simulation. Remember that if you do not select
spectre simulation, you cannot change the environment settings, or add model libraries.
3. Click Run and see the simulation results.

Figure. 17. Change the environment for post layout simulation

Fall 2024 ©Dr. Rakshith Saligram