BECE 102L

DIGITAL SYSTEM DESIGN

Module-I
Digital Logic
Part-V
Module-I (Digital Logic)

Boolean Algebra: Basic definitions, Axiomatic definition of Boolean Algebra,

Basic Theorems and Properties of Boolean Algebra, Boolean Functions,
Canonical and Standard Forms, Simplification of Boolean functions. Gate-Level
Minimization: The Map Method (K-map up to 4 variable), Product of Sums and
Sum of Products Simplification, NAND and NOR Implementation. Logic
Families: Digital Logic Gates, TTL and CMOS logic families.

(8 hours)

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Content

• Digital Logic Gates and its electrical characteristics

• Basic and Compound Gates
• Characteristics
• TTL and CMOS logic families.
• Description
• Comparison

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Binary Logic
• Binary variables assigns two discrete values.
• Binary logic deals with binary variables and operates with
logical meaning.
• The two values of binary variables are
• True and False (or)
• Yes and No (or)
• High and Low (or)
• 1 and 0.

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Binary Logic
• Binary Logic consists of binary variables and a set of logical
operations.
• The variables are generally designated by alphabets such as A, B, x, y,
z…
• Each variable assigns a value of 0 or 1. (Two distinct states).
• Three basic logic operations
• AND
• OR
• NOT

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Logical Operations
AND operation:
• Represented using a dot or by absence of an operator.
• Example 𝑧 = 𝑥 ⋅ 𝑦 𝑜𝑟 𝑧 = 𝑥𝑦 (read it as z equal to x AND y).
OR operation:
• Represented using a + symbol.
• Example 𝑧 = 𝑥 + 𝑦 (read it as z equal to x OR y).
NOT operation
• Represented using a prime (sometimes using a overbar).
• Also called as complement operation.
• Example 𝑧 = 𝑥 ′ 𝑜𝑟 𝑧 = 𝑥 . (read as z not equal to x).

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Binary Logic operations
• Binary logic operation resembles arithmatic operations.
• In fact, AND is similar to multiplication and OR is similar to addition.
• The logic operations are given in a compact form known as Truth
Table.
AND OR NOT
S. No
x y z= x. y x y z=x + y x z=x’
1 0 0 0 0 0 0
0 1
2 0 1 0 0 1 1
3 1 0 0 1 0 1
1 0
4 1 1 1 1 1 1
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Logic Gates
• Logic gates are electronic circuits that operate on one or
more input signals to produce an output signal.
• Electrical signals such as voltage and currents are actually
analog signals and having a certain range. (say 0 to 3v)
• But in digital systems they are interpreted as either 0 or 1.
• Voltage controlled logic circuits response to separate
voltage levels that represent logic 0 or logic1.
• Example 0v as Logic 0 and 3v as Logic 1.
• The input terminals of a logic gate accepts the inputs within
the allowable range and produces an output within the
specified range.
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Logic Gates
• The gates are blocks of hardware that produce the equivalent of
logic‐1 or logic‐0 output signals if input logic requirements are
satisfied.
• The graphical symbols are

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Logic Gates
Gates are classified into 3 different groups.
1. Basic Gates (OR, AND & NOT gates)
2. Compound Gates
1. Universal Gates (NAND and NOR Gates)
2. Special Gates (Ex-OR, and Ex-NOR)
• Gates with multiple inputs also possible

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OR Gate
• A 2 input logic gate accepts two inputs and produces 1 output.
• The output is 0 if and only if both the inputs are equal to 0.
• The logical expression is 𝑂𝑢𝑡𝑝𝑢𝑡 𝑌 = 𝐴 + 𝐵 Waveform
• The logic symbol and truth table is
Truth Table
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1
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AND Gate
• A 2 input logic gate accepts two inputs and produces 1 output.
• The output is 1 if and only if both the inputs are equal to 1.
• The logical expression is 𝑂𝑢𝑡𝑝𝑢𝑡 𝑌 = 𝐴. 𝐵 Waveform
• The logic symbol and truth table is
Truth Table
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
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NOT Gate
• Not Gate accepts one input and produces 1 output.
• The output is 1 if the input is not equal to 1.
• The logical expression is 𝑂𝑢𝑡𝑝𝑢𝑡 𝑌 = 𝐴′ 𝑜𝑟 𝑌 = 𝐴. Waveform
• The logic symbol and truth table is
Truth Table
A 𝑌=𝐴
0 1

1 0

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NOR Gate
• Known as Universal gate.
• A 2 input NOR gate accepts two inputs and produces 1 output.
• Combination of OR+NOT Gates.
• The logical expression is 𝑂𝑢𝑡𝑝𝑢𝑡 𝑌 = 𝐴 + 𝐵 ′ 𝑜𝑟 𝑨 + 𝑩 Waveform
• The output is complemented form of OR output.
Truth Table
A B 𝑨+𝑩
0 0 1
0 1 0
1 0 0
1 1 0
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NAND Gate
• Known as Universal gate.
• A 2 input NAND gate accepts two inputs and produces 1 output.
• Combination of AND+NOT Gates.
• The logical expression is 𝑂𝑢𝑡𝑝𝑢𝑡 𝑌 = 𝐴. 𝐵 ′ 𝑜𝑟 𝑨. 𝑩 Waveform
• The output is complemented form of AND output.
Truth Table
A B 𝑨. 𝑩
0 0 1
0 1 1
1 0 1
1 1 0
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Ex-OR Gate
• A Special gate called as Exclusive-OR gate.
• A 2 input Ex-OR gate accepts two inputs and produces 1 output.
• The logical expression is 𝑂𝑢𝑡𝑝𝑢𝑡 𝑌 = 𝐴 ⊕ 𝐵 = 𝐴′ 𝐵 + 𝐵′ 𝐴
• Also called as XOR gate.
Waveform
Truth Table
A B 𝐴⊕𝐵
0 0 0
0 1 1
1 0 1
1 1 0
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Ex-NOR Gate
• A Special gate called as Exclusive-NOR gate.
• A 2 input Ex-NOR gate accepts two inputs and produces 1 output.
• The logical expression is 𝑂𝑢𝑡𝑝𝑢𝑡 𝑌 = 𝐴 ⊕ 𝐵 = 𝐴𝐵 + 𝐴′ 𝐵′
• Also called as XNOR gate.
Waveform
Truth Table
A B 𝐴⊕𝐵
0 0 1
0 1 0
1 0 0
1 1 1
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Logic Families
• How the Logic gates are implemented using electronic circuits?
• A logic family of monolithic digital integrated circuit devices is a group of
electronic logic gates constructed using one of several designs, usually with
compatible logic levels and power supply characteristics within a family.
• Many No. of Logic families are available. They are classified as
• Based on the Transistor technology.
• Based on Operating Point.
• Based on Logic.

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 Logic Families
RTL
• Based on the Transistor technology
used, the Logic families are classified. DTL
• RTL-Register Transistor Logic Bipolar Junction
Transistor
• DTL-Diode Transistor Logic TTL

Logic families
• TTL-Transistor Transistor Logic
• ECL-Emitter Coupled Logic ECL
• MOS- Metal Oxide Semiconductor
Logic PMOS
• 𝐼 2 𝐿- Integrated Injection Logic MOS Field Effect
Transistor NMOS

CMOS

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Positive and Negative Logic
Voltage Levels are the values associated with the operation of Logic Gates.
• Based on the assignment of voltage levels to 0 and 1.
• Two types
• Positive Logic
• Logic 1 is assigned to High level Voltage (1 to H).
• Logic 0 is assigned to Low level Voltage (0 to L).
• Negative Logic
• Logic 0 is assigned to High level Voltage (0 to H).
• Logic 1 is assigned to Low level Voltage (1 to L).

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Positive and Negative Logic Truth Table
x y z
• Positive Logic AND gate L L L
L H L
H L L
H H H
• Negative Logic
Truth Table
x y z
H H H Positive Logic AND
H L H gate is equal to
Negative Logic OR
L H H Gate.
L L L

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Characteristics of Logic Families
Useful to compare logic families and their performances.
• Some important parameters are
• Fan-out.
• Fan-in.
• Power Dissipation.
• Propagation Delay.
• Noise Margin.
• Operating Temperature.

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FAN-OUT
• The No. of standard loads that can be connected to the output of the
gate without degrading its normal operation.
• A standard load is usually defined as the amount of current needed by
an input of another gate in the same logic family.
• Maximum No. of inputs that can be connected to the output of a gate.
• Also called as Loading.
• Exceeding the maximum limit of Fan-out leads to malfunctioning.
• Crossing the limit is overloading.

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FAN-OUT
• Calculated from the amount of current
available in the output of a gate and the
amount of current needed in each input of a
gate. 𝐼𝑂𝐻

Loading gates
Fan out = Driving
𝐼𝐼𝐻 gate
• Current Source.
• High level output drives other gates.
• In TTL IOH= 400µA and IIH= 40µA , then
the Fan-out is 10.

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FAN-OUT
• Calculated from the amount of current
available in the output of a gate and the
amount of current needed in each input of a

Loading gates
gate. 𝐼𝑂𝐿
Fan out = Driving
𝐼𝐼𝐿
gate
• Current Sink.
• Low level output drives other gates.
• In TTL IOL= 16mA and IIL= 1.6mA , then
the Fan-out is 10.

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 Current Sourcing and Current Sinking
• Current Sourcing: It is the amount of
current that the driving gate produces
as outgoing current that flow into the
load gate
• Current Sinking: It is the amount of
incoming current that the driving gate
receives from the loaded gate

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FAN-IN
• Fan-in is the number of inputs a logic gate can handle.
• Physical logic gates with a large fan-in tend to be slower than those with a small
fan-in.
• Large Fan-in Slower the Gate.

• Gates with More No. of inputs requires More complex input circuit.
• The complexity of the input circuitry increases the input capacitance of the device.

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POWER DISSIPATION
• The amount of power required for the gate.
• Expressed in mW.
• Power delivered from the power supply to the gate.
• Generally the product of Supply Voltage (Vcc) and Supply Current (Icc).
𝐼𝐶𝐶𝐻 +𝐼𝐶𝐶𝐿
• The Supply current 𝐼𝑐𝑐 𝑎𝑣𝑔 =
2
• ICCH : Current drawn during HIGH state. ICCL : Current drawn during LOW state

• The average power dissipation 𝑃𝐷 𝑎𝑣𝑔 = 𝐼𝑐𝑐 (𝑎𝑣𝑔) × 𝑉𝑐𝑐 .

• In a standard TTL Gate the for a Vcc=5V, the Icc(avg)=(3+1)/2=2 mA.
• The Average Power Dissipation is 5*2m= 10 mW.
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PROPAGATION DELAY
• The average transition delay time for
the signal to propagate from input to
output when the binary signal
changes its value (0 to 1 or 1 to 0).
• Measured in ns.
• It is customary to measure the time
from 50% point.
• Average propagation delay is In a standard TTL gate
TPLH=11 ns and TPHL= 7ns so
(𝑇𝑃𝐿𝐻 + 𝑇𝑃𝐻𝐿 )
𝑡𝑝(𝑎𝑣𝑔) = the average delay is 9 ns.
2
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NOISE MARGIN
• The unwanted signals are referred as Noise.
• Spurious electrical signals from industrial and other sources.
• Two types
• DC noise due to the drift in the voltage levels of signals.
• AC noise due to random pulse (switching signals).
• Noise Margin is the maximum noise voltage added to an input signal of a digital
circuit that does not cause an undesirable change in the circuit’s output.
• Noise Margin is the ability of circuits to operate reliably in an environment with
noise.
• Expressed in Volts.
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NOISE MARGIN
• Range of input and output Vcc Vcc
voltages available to a circuit.
• In output voltage range
• Between Vcc and VOH Logic 1.
• Between 0v to VOL Logic 0.
• In input voltage range
• Between 0v to VIL Logic 0.
• Between VIH to Vcc Logic 1.
• Noise Margin: 0v 0v

• VNH=VOH-VIH Smaller One

• VNL=VIL-VOL In TTL, VOH=2.4 v, VOL=0.4 v, VIH=2 v, VIL=0.8 v
VNH=0.4 v and VNL=0.4 v
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OPERATING TEMPERATURE
• IC’s are semiconductor devices that are temperature sensitive by
nature.
• Operating temperature ranges for an IC’s
• 0𝑜 𝐶 𝑡𝑜 70𝑜 𝐶 for consumer and Industrial applications
• −55𝑜 𝐶 𝑡𝑜 125𝑜 𝐶 for military applications

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TTL Family
• Transistor-Transistor Logic.
• Original TTL is a slight modification of the DTL Circuit.
• Various sub-families are available with many improvement in the basic TTL.
• Available in SSI, MSI and LSI form.
• Basically available in 3 different form.
• Open-collector output.
• Totem-pole output.
• Three-state output.

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Transistor ON/OFF

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A A A A
L H L L
H L H H
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TTL-Open Collector Output Gate
• The modified DTL NAND gate.
• Here the collector of output transistor (i.e.) Q3 is left
open.
• A resistor (RL) connected to the Vcc must be inserted
externally to the IC package for the output to “pull-
up” to the high voltage level when Q3 is OFF.
• Otherwise the output acts as open circuit.
• The Logic Levels are
• 0-0.2vLogic 0
• 2.4 to 5v Logic 1

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TTL-Open Collector Output Gate

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 Inputs Q1 Q2 Q3 Output
Any one input is zero ON (EB/FB, CB/RB) OFF OFF V0 = VCC-ICRC (logic 1)
Less collector voltage
All input High OFF (EB/RB, CB/FB) ON ON V0=VCE(Sat) = 0.2V (logic 0)
High collector voltage
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TTL-Open Collector Output Gate
• If any input is low, the corresponding base-emitter junction in Q1 is forward
biased.
• The voltage at the base of Q1 is equal to the input voltage of 0.2 V plus a VBE drop
of 0.7V, or 0.9 V.
• In order for Q3 to start conducting, the path from Q1 to Q3 must overcome a
potential of one diode drop in the base-collector PN junction of Q1 and two VBE
drops in Q2 and Q3 or 3 x 0.6 = 1.8 V.
• Since the base of Q1 is maintained at 0 .9 V by the input signal, the output
transistor cannot conduct and is cut off.
• The output level will be high if an external resistor is connected between the
output and Vcc.
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TTL-Open Collector Output Gate
• If all inputs are high, both Q2 and Q3 conduct and saturate.
• The base voltage of Q1 is equal to the voltage across its base-collector PN
junction plus two VBE drops in Q2 and Q3, or 0.7X 3=2.1V.
• Since all inputs are high, the base-emitter junctions of Q1 are reverse biased.
• When the output transistor Q3 saturates, the output voltage goes low to 0.2V.
• Works without external resistor but noise is more due to open circuit nature.
• Applications
• Driving a Lamp or relay.
• Performing wired logic.
• Common bus systems

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TTL Totem-pole Output
• Circuit of Totem-pole arrangement is except Output
transistor Q4 and Diode D1.
• When the output Y is in the low state. Q2 and Q3 are
driven into saturation as in the open-collector gate.
• The voltage in the collector of Q2 is VBE(Q3) +
VCE(Q2) or 0.7 + 0.2 = 0.9 V.
• The output Y = VCE(Q3) = 0.2 V.
• Transistor Q4 is cut off because its base must be one
VBE drop plus one diode drop, or 2 x 0.6 = 1.2 V, to
start conducting.

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TTL Totem-pole Output

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 Inputs Q1 Q2 Q3 Q4 Output
Any one input is ON (EB/FB, CB/RB) OFF OFF ON V0 = VCC-ICR4-VCE(Sat)-VD (logic 1)
zero Less collector voltage
All input High OFF (EB/RB, CB/FB) ON ON OFF V0=VCE(Sat) = 0.2V (logic 0)
High collector voltage

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TTL Totem-pole Output
• Since the collector of Q2 is connected to the base of Q4, the latter's voltage is only
0.9 V instead of the required 1.2 V, so Q4 is cut off.
• The reason for placing the diode in the circuit is to provide a diode drop in the
output path and thus ensure that Q4 is cut off when Q3 is saturated.
• The wired-logic connection is not allowed with totem-pole output circuits.
• When two totem-poles are wired together, with the output of one gate high and the
output of the second gate low, the excessive amount of current drawn can produce
enough heat to damage the transistors in the circuit.

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TTL Three state Output
• Totem-pole arrangement with Common Bus capability.
• A three -state gate exhibits three output states:
1. a low-level state when the lower transistor in the totem pole is on and the upper
transistor is off,
2. a high -level state when the upper transistor in the totem pole is on and the lower
transistor is off, and
3. a third state when both transistors in the totem pole are off. The third state is an
open-circuit, or high-impedance, state that allows a direct wire connection of
many outputs to a common line.
• Three-state gates eliminate the need for open-collector gates in bus configurations.

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TTL Three state Output

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TTL Three state Output

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 MOS
• MOS transistors as electrically controlled switches
• Two types of transistors, nMOS and pMOS
• The three terminals are gate (the control), source and drain
• Voltage (logic 0 or 1) on the gate controls source-drain path
• The nMOS (pMOS) switch passes a 0 (1) well

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Complementary MOS
• Complementary MOS (CMOS) circuits take advantage of the fact that
both n ‐channel and p ‐channel devices can be fabricated on the same
substrate.

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Complementary MOS
• CMOS circuits consist of both types of MOS devices, interconnected
to form logic functions.
• The basic circuit is the inverter, which consists of one p ‐channel
transistor and one n ‐channel transistor.
• The source terminal of the p ‐channel device is at VDD,(5 to 15V) and
the source terminal of the n ‐channel device is at ground.
• The two voltage levels are 0 V for the low level and VDD for the high
level (typically, 5 V).

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Complementary MOS-NOT Gate
Three rules to understand CMOS are
1. The n ‐channel MOS conducts when its gate‐to‐source voltage is
positive.
2. The p ‐channel MOS conducts when its gate‐to‐source voltage is
negative.
3. Either type of device is turned off if its gate‐to‐source voltage is
zero.

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 Complementary MOS-NOT Gate
1. When the input is low, both gates are at zero potential. The input is
at-VDD relative to the source of the p ‐channel device and at 0 V
relative to the source of the n ‐channel device.
2. The result is that the p‐channel device is turned on and the
n‐channel device is turned off.
3. Under these conditions, there is a low‐impedance path from VDD
to the output and a very high impedance path from output to
ground. Therefore, the output voltage approaches the high level
VDD under normal loading conditions.
4. When the input is high, both gates are at VDD and the situation is
reversed: The p ‐channel device is off and the n ‐channel device is
on. The result is that the output approaches the low level of 0 V
Vin PMOS NMOS Vout
0 VGS = VG – VS = 0-VDD = -VDD ;PMOS ON VGS = VG – VS = 0-0 =0; NMOS OFF VDD (High) ; 1
1(VDD) VGS = VG – VS = VDD-VDD = 0 VGS = VG – VS = 1-0 =1 GND (Low) ; 0
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CMOS Inverter

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Complementary MOS-NAND Gate

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Complementary MOS-NAND Gate

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Complementary MOS-NOR Gate

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Complementary MOS-NOR Gate

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CMOS-AND and CMOS-OR

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Comparison of Logic families
• Performance of Various Logic families

Logic family Power dissipation Propagation Fan in Fan out Noise

(mW) delay (ns) immunity
RTL 12 12 < 10 5 Poor
DTL 8-12 30 <10 8 Good
TTL 10 10 12-14 10 Very good
ECL 40-55 2 >10 25 Poor
CMOS 1.01 70 >10 50 Excellent

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Boolean function realization using CMOS
• PMOS
• AND - parallel connection
• OR - Series connection

• NMOS
• AND - series connection
• OR - parallel connection

• The complementary gate is naturally inverting, implementing only functions

such as NAND, NOR and XNOR. To implement non-inverting functions
(AND, OR, XOR, etc.) we must add an Inverter after the initial stage.

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Boolean function realization using CMOS

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Boolean function realization using CMOS

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Boolean function realization using CMOS
Practice problems
1. F= ((A+B) C + D)'
2. F= (A (B C + D))'
3. F= (A +(B' + CD)')‘
4. F= (A' + B'C)
5. F= [((CD) +B) A]'
6. F= (A+D+C)(B+E)

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Summary
• Binary Logic
• Logic Gates
• Basic Gates
• Universal Gates
• Special Gates.
• Electrical characteristics of Gates.
• Logic Families
• RTL, DTL
• TTL, ECL and
• CMOS.
• Comparison
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