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Release Notes

The Release Notes for ModelSim Intel FPGA 10.6, dated December 13, 2016, provide proprietary information about the software, including licensing details, supported platforms, and enhancements. Key changes include updates to licensing versions, compatibility issues, and various defects repaired across SystemVerilog, VHDL, and SystemC. Additionally, the document outlines how to obtain support and lists trademarks associated with Mentor Graphics Corporation.

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0% found this document useful (0 votes)
5 views

Release Notes

The Release Notes for ModelSim Intel FPGA 10.6, dated December 13, 2016, provide proprietary information about the software, including licensing details, supported platforms, and enhancements. Key changes include updates to licensing versions, compatibility issues, and various defects repaired across SystemVerilog, VHDL, and SystemC. Additionally, the document outlines how to obtain support and lists trademarks associated with Mentor Graphics Corporation.

Uploaded by

huy.th
Copyright
© © All Rights Reserved
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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Release Notes For ModelSim Intel FPGA 10.

Dec 13 2016
Copyright 1991-2016 Mentor Graphics Corporation
All rights reserved.
This document contains information that is proprietary to Mentor
Graphics
Corporation. The original recipient of this document may duplicate this
document in whole or in part for internal business purposes only,
provided
that this entire notice appears in all copies. In duplicating any part
of
this document the recipient agrees to make every reasonable effort to
prevent the unauthorized use and distribution of the proprietary
information.
TRADEMARKS: The trademarks, logos and service marks ("Marks") used
herein
are the property of Mentor Graphics Corporation or other third parties.
No one is permitted to use these Marks without the prior written
consent
of Mentor Graphics or the respective third-party owner. The use herein
of a third-party Mark is not an attempt to indicate Mentor Graphics as
a
source of a product, but is intended to indicate a product from, or
associated with, a particular third party. The following are trademarks
of
of Mentor Graphics Corporation: Questa, ModelSim, JobSpy, and Signal
Spy.
A current list of Mentor Graphics trademarks may be viewed at
www.mentor.com/terms_conditions/trademarks.cfm.
End-User License Agreement: You can print a copy of the End-User
License
Agreement from: www.mentor.com/terms_conditions/enduser.cfm.
_______________________________________________________________________

* How to Get Support


ModelSim Intel FPGA is supported by Intel
+ World-Wide-Web Support
[1]http://www.altera.com/mySupport
_______________________________________________________________________

Index to Release Notes

* [2]Key Information
* [3]Release Announcements in 10.6
* [4]Base Product Specifications in 10.6
* [5]Compatibility Issues with Release 10.6
* [6]User Interface Defects Repaired in 10.6
* [7]SystemVerilog Defects Repaired in 10.6
* [8]VHDL Defects Repaired in 10.6
* [9]SystemC Defects Repaired in 10.6
* [10]General Enhancements in 10.6
* [11]SystemVerilog Enhancements in 10.6
* [12]SystemC Enhancements in 10.6
_______________________________________________________________________

Key Information
* The following lists the supported platforms:
+ win32aloem - Windows 7, Windows 8.1, Windows 10
+ linuxaloem - RedHat Enterprise Linux 6, SUSE Linux Enterprise
Server 11
_______________________________________________________________________

Release Announcements in 10.6


* [nodvtid] -
There is no licensing change between 10.5 and 10.6. However, if you
are migrating to 10.6 from a release like 10.4 and older, please
note that release 10.6 uses FLEXnet v11.13.1.2 server, v11.13.0.2
client.
For floating licenses, it will be necessary to verify that the
vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd)
have FLEXnet versions equal to or greater than 11.13.0.2. If the
current FLEXnet version of your vendor daemon and lmgrd are less
than 11.13.0.2 then it will be necessary to stop your license
server and restart it using the vendor daemon and lmgrd contained
in this release.
If you use node locked licenses you don't need to do anything. This
release will update licensing to MSL v2015_1_patch2 with MGLS
v9.13_5.4 and PCLS v9.13.5.2
In summary, this release uses the following license versions:
+ FLEXnet v11.13.1.2 server, v11.13.0.2 client
+ MSL v2015_1_patch2
+ MGLS v9.13_5.4
+ PCLS v9.13.5.2
+ [nodvtid] - Beginning with 10.6 release, support for Linux
RHEL 5 x86/x86-64 and SLES 10 x86/x86_64 have discontinued.
+ [nodvtid] - Beginning with 10.6 release,
gcc-4.3.3-linux/gcc4.3.3-linux_x86_64 GCC Compilers for
SystemC have been discontinued.
+ [nodvtid] - Beginning with 10.6 release, support for Windows 8
series is limited to 8.1. Windows 8.0 has discontinued.
___________________________________________________________________

Base Product Specifications in 10.6

* [nodvtid] -
[Supported Platforms]
Linux RHEL 6 x86/x86-64
Linux RHEL 7 x86/x86-64
Linux SLES 11 x86/x86-64
Windows 7 x86/x64
Windows 8.1 x86/x64
Windows 10 x86/x64
[Supported GCC Compilers (for SystemC)]
gcc-5.3.0-linux/gcc-5.3.0-linux_x86_64
gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
gcc-4.2.1-mingw32vc12
[OVL (shipped with product)]
v2.8.1
[VHDL OSVVM (shipped with product)]
v2014.07
[Licensing]
FLEXnet v11.13.1.2 server, v11.13.0.2 client
MSL v2015_1_patch2
MGLS v9.13_5.4
PCLS v9.13.5.2
_______________________________________________________________________
Compatibility Issues with Release 10.6

SystemVerilog Compatibility
* [nodvtid] - (source) Modports declared within generate blocks
within interfaces have been removed from the language by the IEEE.
This is Mantis item 343.
* dvt84871 - (results) vsim crashed when annotating SDF to a full
specify path ( "*>") with path selects on source and destination
terminals. This happened only when the specify block contained more
than 64 paths and the width of the source and destination
part-selects were different. E.g. (a[17:9] *> y[36:18]) = (0);
* dvt66421 - (results) When vsim was run with any "-radix" other than
"binary", UVM backdoor functions uvm_hdl_deposit and uvm_hdl_force
didn't deposit/force the correct value into VHDL data objects.
* dvt85937 - (results) Fixed the issues that DPI disable protocol was
not followed when a thread is terminated either by "disable fork"
or "process:kill"
* dvt89393 - (results) A concatenation of nets connected to an out or
inout unpacked net array port was connected in reverse order.
* dvt87656 - (results) The implicit sensitivity for @* has been
enhanced beyond the LRM specification to include bit-selects and
part-selects in the sensitivity according to the same rule for
always_comb, which is to use the "longest static prefix" of any
select expressions read in the block rather than the identifier for
the whole variable. This can improve performance and better match
the intention of the code. Use the compiler option -svext=sas to
revert back to the old behavior.

VHDL Compatibility
* dvt88164 - (results) In some specific mixed language cases where
both numeric_std and 1164 packages were included vcom used to give
an incorrect error saying "Cannot resolve expression type of
association element". This has been fixed.
* dvt93451 - (results) Vsim crashed when bit slices wider than 256,
of VHDL signals, were read through built-in UVM backdoor functions.

SystemC Compatibility
* [nodvtid] - (results) sccom would invoke scparse with the '--c++0x'
option by default, which would enable the c++11 standard. The
enabling of the c++11 standard by default would lead to scparse
compilation errors in certain cases, while the g++ compilation
would run fine. sccom has been fixed not to pass '--c++0x' by
default. If a design has c++11 constructs, sccom needs to be
invoked with the '-std=c++11' option so that both, g++ and scparse
will run with the c++11 standard enabled during compilation.
_______________________________________________________________________

User Interface Defects Repaired in 10.6


* dvt90155 - A force operation on a wreal interconnect would resault
in a crash. This issue has been resolved.
_______________________________________________________________________

SystemVerilog Defects Repaired in 10.6


* dvt84871 - (results) vsim crashed when annotating SDF to a full
specify path ( "*>") with path selects on source and destination
terminals. This happened only when the specify block contained more
than 64 paths and the width of the source and destination
part-selects were different. E.g. (a[17:9] *> y[36:18]) = (0);
* [nodvtid] - Extended Mac OS new-line warning message to cover line
comments when the line comments is the first text found within a
source file.
* dvt84189 - Inline randomization constraints with type casts would
sometimes generate compilation errors like:
** Error: test.sv(10): Illegal field 'my_type'
* dvt85773 - vsim crashed with "+bitblast" when a module contained a
wide port in $setuphold (or $recrem) but not corresponding delayed
nets. For example, "$setuphold(posedge CLK, posedge A,
0,0,notify);" where A is a wide port. In comparison,
"$setuphold(posedge CLK, posedge A, 0,0,notify,,, dCLK, dA);",
which has the delayed nets specified, did not crash.
* dvt66421 - (results) When vsim was run with any "-radix" other than
"binary", UVM backdoor functions uvm_hdl_deposit and uvm_hdl_force
didn't deposit/force the correct value into VHDL data objects.
* dvt85937 - (results) Fixed the issues that DPI disable protocol was
not followed when a thread is terminated either by "disable fork"
or "process:kill"
* dvt86203 - Fix a crash in vsim when automatic variables for a class
are declared within an if-then-else statement with a fork/join and
wait.
* dvt87810 - Vopt would give errors like this:
** Error: test.sv(17): (vopt-2132) Instance 'dut' has a
non-optimizable form of recursive instantiation.
with recursively instantiated modules within generate loops and
conditions.
* dvt89393 - (results) A concatenation of nets connected to an out or
inout unpacked net array port was connected in reverse order.
_______________________________________________________________________

VHDL Defects Repaired in 10.6


* dvt83738 - Incorrect code was generated for constant-index signal
assignments when the array elements are generic types. As a result,
the simulator could crash.
* dvt81426 - If an array-valued signal has only constant-index signal
assignments in a particular process, and the process contains an
expression involving either the 'driving or 'driving_value
attribute, incorrect code was generated for the attribute
expression. As a result, the simulator could crash during
evaluation of the expression.
* dvt85740 - The compiler (vcom) would issue an Internal error
message when an array aggregate expression was associated with a
port of a direct instantiation (ENTITY) when that port was of an
array-of-unconstrained array type and the port subtype was fully
constrained at the inner array and the constraint depended on
generics of the ENTITY, different from the ENTITY of the design
unit that contains the direct instantiation statement.
* dvt85842 - If a subprogram contained a formal of mode IN and of
type TIME and the declaration of the formal included a default
expression, then a call to the subprogram that had an explicit
association element for that formal would result in the subprogram
being called with the value of the default expression, not the
value of the actual.
* dvt86029 - The simulator would crash when a port map associated an
array subelement of a record type signal with an array type port,
when the array subelement was defined as an unconstrained array
(i.e, the record type was record-with-unconstrained array
subelement).
* dvt86918 - When an inner nested GENERATE block contained a slice
name whose slice range depended in an outer FOR-GENERATE's loop
parameter, and when a component instantiation in the inner GENERATE
contained a GENERIC MAP association element that had an actual that
depended on this slice name, then the compiler would create bad
code that could crash the simulator.
* dvt86935 - Fixed a crash where a VHDL port which is an array of
std_logic, the actual of the port is a slice of a static expression
and the port is connected to a Verilog port.
* dvt86813 - A CASE GENERATE statement that contained an external
name in the expression or in a choice in an alternative would
sometimes cause a simulator crash.
* dvt88164 - (results) In some specific mixed language cases where
both numeric_std and 1164 packages were included vcom used to give
an incorrect error saying "Cannot resolve expression type of
association element". This has been fixed.
* dvt35748 - When +cover was specified to vcom, implicit operators
were included in the set of subprograms that were added to the
Structure window in the GUI, along with user-defined subprograms.
Implicit operators are no longer part of this set.
* dvt89183 - Concatenation expressions involving a qualified
expression whose operand was also a concatenation expression could
sometimes cause a vcom internal error.
* dvt90896 - Vcom could crash when trying to report an invalid field
of a record if the prefix of the selected name was an index on an
array access type.
* dvt91137 - A generic of a record type might receive an incorrect
actual value when the actual was a function call and there existed
another different function call actual for a different formal.
* dvt91565 - If an architecture called a subprogram in a package, and
if that subprogram contained a call to another subprogram, defined
only in the package body and found via a forward declaration also
in the package body, then subprogram inlining could produce bad
code that would crash the simulator when the design was loaded.
* dvt92840 - Access to a shared variable through an interface package
could cause the elaboration phase of the simulator to crash.
* dvt93089 - A call to a shared variable's method from within a
subprogram of an uninstantiated package could cause the simulator
to crash.
* dvt93451 - (results) Vsim crashed when bit slices wider than 256,
of VHDL signals, were read through built-in UVM backdoor functions.
_______________________________________________________________________

SystemC Defects Repaired in 10.6


* [nodvtid] - (results) sccom would invoke scparse with the '--c++0x'
option by default, which would enable the c++11 standard. The
enabling of the c++11 standard by default would lead to scparse
compilation errors in certain cases, while the g++ compilation
would run fine. sccom has been fixed not to pass '--c++0x' by
default. If a design has c++11 constructs, sccom needs to be
invoked with the '-std=c++11' option so that both, g++ and scparse
will run with the c++11 standard enabled during compilation.
* [nodvtid] - Fixed DPI and SystemC link time errors due to different
standard library installation paths on some linux distributions.
Library paths looked up at link time will be "/usr/lib64",
"/usr/lib/x86_64-linux-gnu" for 64-bit and
"/usr/lib/i386-linux-gnu", "/usr/lib/i686-linux-gnu", "/usr/lib32"
for 32-bit platforms
* dvt86850 - In certain scenarios, where systemc.so would not unload
during shared library cleanup and the design has global SystemC
objects, vopt or vsim may crash at exit time trying to print an
error message. This issue is now fixed.
_______________________________________________________________________

General Enhancements in 10.6


* [nodvtid] - For IP protection using encryption for VHDL and SV, we
have added a new public key named MGC-VERIF-SIM-RSA-2 that has 2048
bit key length. This enhances our security and conforms to the
recommendations in IEEE 1735-2014. All users of IP protection are
encouraged to begin using this key. IP authors should verify that
their Modelsim and Questasim product version requirements are
satisfied. This key is not supported in older releases.
* dvt84671 - For IP protection in VHDL and SV, a new 2048 bit public
key named MGC-VERIF-SIM-RSA-2 has been added. This provides
enhanced security and conforms to recommendations in IEEE
1735-2014. IP authors are encouraged to start using this key
immediately. They should confirm that the supported Modelsim and
Questa versions for this key satisfy their needs.
* dvt78423 - When the design unit being instantiated was contained
inside library 'work', and the design unit of the scope of the
instantiation statement was contained in a library that was not
named 'work', vopt (and vsim in -novopt flow) would fail to find
the instantiated design unit in spite of using -L work. Using -L
./work would make the test pass. This has been fixed, and now -L
./work is no longer required.
* dvt85061 - Added a sub-option 'compress' to option -createlib to
automatically create compressed missing libraries. i.e. whenever a
new library is created based on -createlib option, it is created
compressed. The syntax is -createlib=compress.
* [nodvtid] - Usability improvements and bug fixes have been made to
Questa's library search features. There are no known
incompatibilities with earlier library search operations. All
working designs will continue to elaborate as they have in the
past.
The following new features have been added to Questa's library
search algorithm:
1. A new option called -Ldir has been added to vopt and vsim.
This option allows users to pass container folders for the
libraries specified with -L/-Lf options. Once a container folder
has been specified, the libraries contained in this folder can be
directly referenced using their logical names. When multiple -Ldir
options are used, the tool searches in the order in which -Ldir
paths are specified on the command line. $cwd is always searched
before any -Ldir options, as if there was an implicit "-Ldir ."
specified first on the command line.
2. Vopt now detects inconsistencies between its -L/-Lf options and
the options passed to vlog. Any inconsistency that can possibly
result in a difference in the composition of the design will
generate a warning.
3. A new option -libverbose=libmap has been added to display
library map pattern matching information during compilation.
4. Some design units were missing source information next to their
loading messages with -libverbose=prlib. This has been fixed. All
design units now consistently show their source libraries when
-libverbose=prlib is used.
5. A new option -work has been added to vsim. This is an optional
option; When used, it would override the library in which vsim
writes the optimized design generated by the internally invoked
vopt command in the 2-step flow.
6. Error messages vsim-19 and vopt-19, generated for non-existent
-L/-Lf libraries, are now suppressible.
* [nodvtid] - The "find signals", "find nets", and "find instances"
commands are now supported in -batch mode.
_______________________________________________________________________

SystemVerilog Enhancements in 10.6


* dvt83697 - SV variables having an initializer in the declaration
are not allowed to trigger an always block at time zero, whereas in
V2K mode those assignments do trigger top-blocking always blocks.
Use the -svext=defervda compiler option to have these SV
initializers trigger top-blocking always blocks.
* [nodvtid] - Added a vlog and vopt -svext=tzas option that runs a
top-blocking always @* at time zero, same as is done for an
always_comb, meaning that the always block will behave as though
triggered at time zero even if none of the variables and nets in
the implied sensitivity change value at time zero.
* [nodvtid] - vlog's -E output would not emit `line directives with
anything other than '0' for the "level" parameter. Valid values for
the "level" parameter are 0, 1 or 2.
* [nodvtid] - (source) Modports declared within generate blocks
within interfaces have been removed from the language by the IEEE.
This is Mantis item 343.
* dvt87656 - (results) The implicit sensitivity for @* has been
enhanced beyond the LRM specification to include bit-selects and
part-selects in the sensitivity according to the same rule for
always_comb, which is to use the "longest static prefix" of any
select expressions read in the block rather than the identifier for
the whole variable. This can improve performance and better match
the intention of the code. Use the compiler option -svext=sas to
revert back to the old behavior.
* dvt93489 - The vlog/vopt -svext=dmsbw option can be used to drive
the MSB unconnected bits of the wider hiconn (output) or the wider
loconn (input) in an otherwise collapsible port connection. With
the option, the unconnected bits are driven with zero, otherwise
they float.
_______________________________________________________________________

SystemC Enhancements in 10.6


* [nodvtid] - GNU compiler enhancements for SystemC.
For SystemC-2.3.1 (IEEE 1666-2011)
+ Platforms supported: linux, linux_x86_64 and win32
+ Compilers supported: gcc-5.3.0, gcc-4.7.4, gcc-4.5.0 for linux
and linux_x86_64, and gcc-4.2.1 for win32.
For SystemC-2.2 (IEEE 1666-2005)
+ Platforms supported: linux, linux_x86_64 and win32
+ Compilers supported: gcc-4.5.0 for linux and linux_x86_64 and
gcc-4.2.1 for win32.

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