VLSI System Design

Lecture 8

Course handler: Dr. T. Pradheep

Asst.Prof (Sr.), SENSE
Office: SJT 510 A-12
Contact e-mail: [email protected]
Open hours : Friday 14.00 P.M-15.00 P.M
 Last class..
• Problems and solutions
What is a Delay in logic circuits?
 Different types of Delay
• We sometimes differentiate between the delays for the output
rising, tpdr /tcdr , and the output falling, tpdf /tcdf . Rise/fall times
are also sometimes called slopes or edge rates.

• Propagation and contamination delay times are also called

max-time and min-time, respectively.

• The gate that charges or discharges a node is called the driver

and the gates and wire being driven are called the load.

• Propagation delay is usually the most relevant value of

interest, and is often simply called delay.
 Delay
• The user must specify the arrival time of inputs and the time
data is required at the outputs.

• The slack is the difference between the required and arrival

times.

• Positive slack means that the circuit meets timing.

• Negative slack means that the circuit is not fast enough.

 Delay Definitions
• tpdr: rising propagation delay
– From input to rising output
crossing VDD/2
• tpdf: falling propagation delay
– From input to falling output
crossing VDD/2
• tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
• tr: rise time
– From output crossing 0.2 VDD
to 0.8 VDD
• tf: fall time
– From output crossing 0.8 VDD
to 0.2 VDD
 Delay Definitions
• tcdr: rising contamination delay
– From input to rising output crossing VDD/2
• tcdf: falling contamination delay
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tcd = (tcdr + tcdf)/2
 Why is Delay so important?
• In most designs there will be • The critical paths can be
many logic paths that do not affected in four major levels
require any conscious effort when
it comes to speed.
– The
architectural/microarchitectural
• These paths are already fast level
enough for the timing goals of the
system. However, there will be a – The logic level
number of critical paths that limit – The circuit level
the operating speed of the system – The layout level
and require attention to timing
details.
 Delay: Architectural level
• The most leverage is achieved with a good microarchitecture.
This requires a broad knowledge of both the algorithms that
implement the function and the technology being targeted,
such as how many gate delays fit in a clock cycle, how quickly
addition occurs, how fast memories are accessed, and how
long signals take to propagate along a wire.

• Trade-offs at the microarchitectural level include the number

of pipeline stages, the number of execution units (parallelism),
and the size of memories.
 Delay: Logic level
• The next level of timing optimization comes at the logic level.

• Trade-offs include types of functional blocks (e.g., ripple carry

vs. lookahead adders), the number of stages of gates in the
clock cycle, and the fan-in and fan-out of the gates. The
transformation from function to gates and registers can be
done by experience, by experimentation, or, most often, by
logic synthesis.

• Remember, however, that no amount of skillful logic design

can overcome a poor microarchitecture.
 Delay: Circuit and layout level
• Once the logic has been selected, the delay can be tuned at the
circuit level by choosing transistor sizes or using other styles
of CMOS logic.

• Finally, delay is dependent on the layout. The floorplan (either

manually or automatically generated) is of great importance
because it determines the wire lengths that can dominate delay.
Good cell layouts can also reduce parasitic capacitance.
 Transient response
• The most fundamental way to compute delay is to develop a physical
model of the circuit of interest, write a differential equation describing the
output voltage as a function of input voltage and time, and solve the
equation.
• The solution of the differential equation is called the transient response,
and the delay is the time when the output reaches VDD /2.
• The differential equation is based on charging or discharging of the
capacitances in the circuit. The circuit takes time to switch because the
capacitance cannot change its voltage instantaneously. If capacitance C is
charged with a current I, the voltage on the capacitor varies as:
Transient response
Transient response
 RC Delay Models
• RC delay models approximate the nonlinear transistor I-V and
C-V characteristics with an average resistance and capacitance
over the switching range of the gate.

• This approximation works remarkably well for delay

estimation despite its obvious limitations in predicting detailed
analog behavior.

• The RC delay model treats a transistor as a switch in series

with a resistor. The effective resistance is the ratio of Vds to Ids
averaged across the switching interval of interest.
 Simulated Inverter Delay
• Solving differential equations by hand is too hard
• SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
• But simulations take time to write, may hide insight
2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)
 Delay Estimation
• We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
• The step response usually looks like a 1st order RC response
with a decaying exponential.
• Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
• Characterize transistors by finding their effective R
– Depends on average current as gate switches
 Effective Resistance
• Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
• Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
• Too inaccurate to predict current at any given time
– But good enough to predict RC delay
 RC Delay Model
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width
d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d
 RC Values
• Capacitance
– C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
– Gradually decline to 1 fF/mm in 65 nm
• Resistance
– R  10 KW•mm in 0.6 mm process
– Improves with shorter channel lengths
– 1.25 KW•mm in 65 nm process
• Unit transistors
– May refer to minimum contacted device (4/2 l)
– Or maybe 1 mm wide device
– Doesn’t matter as long as you are consistent
 Inverter Delay Estimate
• Estimate the delay of a fanout-of-1 inverter
2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = 6RC
Delay Model Comparison
 Example: 3-input NAND
• Sketch a 3-input NAND with transistor widths chosen to achieve
effective rise and fall resistances equal to a unit inverter (R).

2 2 2

3
3

3
 3-input NAND Caps
• Annotate the 3-input NAND gate with gate and diffusion capacitance.

2C 2C 2C
2C 2C 2C
2 2 2
2C 2C 2C
9C
3 3C
5C 3C
3C
3
5C 3C
3C
3
5C 3C
3C
Falling and Rise Delays-3 input
NAND gate
Transient response-RC Delay
Model
The system has a transfer function

Where τ = RC
Transient response-RC Delay
model

Where ln 2= 0.69
Transient response-RC delay
model (2nd order system)
The system has a transfer function
 Transient response-RC delay
model (2nd order system)

• This approximation works best when one time constant is significantly bigger than
the other .
• For example, if R1 = R2 = R and C1 = C2 = C, then τ1 = 2.6 RC, τ2 = 0.4 RC, τ = 3
RC and the second-order response and its first-order approximation are shown in
next slide.
• The error in estimated propagation delay from the first-order approximation is less
than 7%. Even in the worst case, where the two time constants are equal, the error is
less than 15%.
• The single time constant is a bad description of the behavior of intermediate nodes.
For example, the response at n1 cannot be described well by a single time constant.
However, CMOS designers are primarily interested in the delay to the output of a
gate, where the approximation works well.
 Transient response-RC delay
model (2nd order system)

• In the next section, we will see how to find a simple single time constant
approximation for general RC tree circuits using the Elmore delay model.
Thank you for your listening