TRANSISTROS ENCODER DECODER SRAM

transmission gate

NOT NOR
NMOS (PDN)

PMOS (PUN)
NAND AND
TIMING ANALYSIS
ONE HOT MEALY Tmin = 1/Fmax
Tmin = t + 3(t ) + t + t u = 6.4ns
cQ AND XOR s

Fmax = 1/6.4 ns = 156.25 MHz

t + t = 0.8 + 1.2 = 2.0 ns. Since 2.0 ns > th = 0.4 ns
cQ XOR

there are no hold time violations.

WITH CLOCK SKEW:
tcQ + 3(tAND) + tXOR + tsu − tskew = 6.4 − 1.5 ns = 4.9 ns
There is now a different critical path through the circuit
Tmin = tcQ + 2(tAND) + tXOR + tsu = 5.2 ns
T = t +t +t −t
min cQ L su skew

t +t <t +t
cQ l h skew

COUNTERS
4 bit counter

1000, 0100, 0010, and 0001

3 bit up counter ring counter

johnson
0000, 1000,
1100, 1110,
1111, 0111,
0011, 0001, BCD
0000

mux2to1 rate divider

module mux2to1(x, y, s, m); module rateDivider(input clock, input [25:0]
input x; //select 0 upperBound, output reg enable, output reg [25:0]
input y; //select 1 counter);
input s; //select signal always @(posedge clock) begin
output m; //output if (counter === 26'bx)
counter <= 26'b0;
//assign m = s & y | ~s & x; else if (counter == upperBound) begin
// OR enable= 1'b1;
assign m = s ? y : x; counter <= 26'b0;
end
endmodule else begin
enable = 1'b0;
shift register counter <= counter + 1 ;
module ShiftReg( end
input [3:0] D, end
input Clock, endmodule
Resetn,
Loadn, function select
output SerialOut); module FunctionSelect(input [3:0] X, Y, input
reg [3:0] Q; [2:0] Sel,
output reg [3:0] Fout);
always @(posedge Clock) wire [3:0] w1, w2;
if (!Resetn) ModA U1(.X(X), .Y(Y), .ModAout(w1));
Q <= 0; ModB U2(.X(X), .Y(Y), .ModBout(w2));
else if (!Loadn) always @(*)
Q <= D; case (Sel)
else begin 3'b000: Fout = w1;
Q[0] <= 1'b1; 3'b001: Fout = ~X;
Q[1] <= Q[0]; 3'b010: Fout = {X[3:2],Y[1:0]};
Q[2] <= Q[1]; 3'b011: Fout = w2;
Q[3] <= Q[2]; 3'b100: Fout = ~(X & Y);
end default: Fout = 3'b000;
assign SerialOut = Q[3]; endcase // case (Sel)
endmodule endmodule // FunctionSelect .do
4 bit register 3 bit add
module reg4bit (D, Clock, Resetb, module adder(A, B, S, cin, cout);
Enable, Q); input [2:0] A, B;
input [3:0] D; input cin;
input Clock, Resetb, Enable; output [2:0] Sum; vlib work
output reg [3:0] Q; output cout; vlog mux.v
vsim mux
wire [1:0] f_cout; log {/*}
always @(posedge Clock)
if (!Resetb) full_adder F0(cin, A[0], B[0], S[0], f_cout[0]); add wave {/*}
Q <= 0; full_adder #signal names need to be in {} brackets
else if (Enable) F1(f_cout[0]), A[1]), B[1]), S[1]), f_cout[1]); force {SW[0]} 0
Q <= D; full_adder force {SW[1]} 0
endmodule F2((f_cout[1]), (A[2]), (B[2]), (S[2]), (cout) ); force {SW[9]} 0
endmodule run 10ns
 ECE241 FINAL
BOOLEAN ALGEBRA GATES AND LATCHES
10a. x · y = y · x 10b. x + y = y + x commutative MUX NAND
11a. x · (y · z) = (x · y) · z 11b. x + (y + z) = (x + y) + z
5a. x · 0 = 0 5b. x + 1 = 1
12a. x · (y + z) = x · y + x · z 12b. x + y · z = (x + y) · (x + z) associative
6a. x · 1 = x 6b. x + 0 = x
13a. x + x · y = x 13b. x · (x + y) = x absorption
7a. x · x = x 7b. x + x = x
14a. x · y + x · y̅ = x 14b. (x + y) · (x + y̅ ) = x combining
8a. x · x̅ = 0 8b. x + x̅ = 1
15a. x · y = x̅ + y̅ 15b. x + y = x̅ · y̅ DeMorgan’s
9. !x̅ = x XOR NOR
16a. x + x̅ · y = x + y 16b. x · (x̅ + y) = x · y covering

High on odd values of 1

17a. xy + yz + x̅ z = xy + x̅ z 17b. (x + y)(y + z)(x̅ + z) = (x + y)(x̅ + z)
XOR = xy̅ + yx̅
XNOR = xy + x̅y̅

ADDERS full adder

Time: 3 gate delays
fast adder

BASIC (SR) LATCH

CAUTION: When S = R = 1 then S = R = 0, oscillation occurs

GATED SR LATCH
ripple carry adder

multiplication

Time: 2n+1

OTHER FLIP FLOPS AND REGISTERS

t flip flop

GATED D LATCH / D FLIP FLOP

jk flip flop

4 bit right shift register

4 bit parallel load shift register NEG EDGE TRIGGERED D FLIP FLOP
master slave D flip flop
mod sim
vlib: set the working directory, where all the compiled
Verilog goes, use vlib work

vlog: compiles Verilog modules to working directory, use

vlog <filename>.v

vsim: starts vsim simulator, use vsim <filename>

log 2 signals: log {SigA, SigB}
add a wave to show two signals: add wave {SigA, SigB}
DE1_SoC.qsf file: maps port names in top-level module to
pin numbers in the FPGA chip
POS EDGE TRIGGERED D FLIP FLOP
FPGA: Field Programmable Gate Array, a prog. device for
implementing digital circuits
latch is level sensitive, flip flop is edge-sensitive
Why is simulation important?
• shows design works before implementation
• makes debugging easier and faster
• in simulation you can see any logic signal, not just
input and output
• you can see responses that cannot be observed in Use NOR gates to construct
hardware neg edge triggered gate

anais poirier