Name of the Course: Intoduction to VLSI Design

Topic for the class: MODULE 1-Introduction to Verilog

Date & Time :1/24/2022

Dr T.Gowri
Assistant Professor
Department of EECE
GITAM Institute of Technology (GIT)
Visakhapatnam – 530045
Email: gthumbur@gitam.edu

24 January 2022 Department of EECE, GIT 1

 INTRODUCTIONTO VLSI DESIGN

The word digital has made a dramatic impact on our society. More significant is a
continuous trend towards digital solutions in all areas – from electronic instrumentation,
control, data manipulation, signals processing, telecommunications etc., to consumer
electronics. Development of such solutions has been possible due to good digital system
design and modeling techniques.

CONVENTIONAL APPROACH TO DIGITAL DESIGN

• SSI
• MSI
• LSI
• VLSI
• ULSI
• GSI
With comparatively larger circuits, the task mostly reduces to one of identifying the set of ICs necessary
for the job and interconnecting.

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The accepted approach to digital design here is a mix of the top-down and bottom-up approaches
as follows
• Decide the requirements at the system level and translate them to circuit
requirements.
• Identify the major functional blocks required like timer, DMA unit, register-fil
etc., say as in the design of a processor.
• Whenever a function can be realized using a standard IC, use the same –for
example programmable counter, mux, demux, etc.
• Whenever the above is not possible, form the circuit to carry out the block
functions using standard SSI – for example gates, flip-flops, etc.
• Use additional components like transistor, diode, resistor, capacitor, etc
wherever essential.

➢ Once the above steps are gone through, a paper design is ready. Starting with the paper design,
one has to do a circuit layout.
➢ The physical location of all the components is tentatively decided; they are interconnected and
the ‘circuit-on- paper’ is made ready.
➢ Once a paper design is done, a layout is carried out and a net-list prepared. Based on this, the
PCB is fabricated, and populated and all the populated cards tested and debugged.
➢ The24procedure
January 2022
is shown as a process flowchart in Figure.
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 At the debugging stage one may encounter three types of problems:
Functional mismatch: The realized and expected functions are different. One may have to go
through the relevant functional block carefully and locate any error logically. Finally the
necessary correction has to be carried out in hardware.
Timing mismatch: The problem can manifest in different forms. One possibility is due to the
signal going through different propagation delays in two paths and arriving at a point with a
timing mismatch. This can cause faulty operation. Another possibility is a race condition in a
circuit involving asynchronous feedback. This kind of problem may call for elaborate
debugging. The preferred practice is to do debugging at smaller module stages and ensuring
that feedback through larger loops is avoided: It becomes essential to check for the existence of
long asynchronous loops.
Overload: Some signals may be overloaded to such an extent that the signal transition may be
unduly delayed or even suppressed. The problem manifests as reflections and erratic behavior
in some cases (The signal has to be suitably buffered here.). In fact, overload on a signal can
lead to timing mismatches.

The above have to be carried out after completion of the prototype PCB manufacturing; it
involves cost, time, and also a redesigning process to develop a bugfree(with out error) design.
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 VLSI DESIGN

The complexity of VLSIs being designed and used today makes the
manual approach to design impractical. Design automation is the order of
the day.

The status of VLSI technology is characterized by the following:

1. A steady increase in the size and hence the functionality of the ICs.
2.A steady reduction in feature size and hence increase in the speed of
operation as well as gate or transistor density.
3.A steady improvement in the predictability of circuit behavior.
4.A steady increase in the variety and size of software tools for VLSI design

It is the basis for development and use of CAD tools in VLSI design at
various levels.

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ASIC DESIGN FLOW

ASIC design and development flow

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 ROLE OF HDL
• An HDL provides the framework for the complete logical design of the ASIC.
• Verilog and VHDL are the two most commonly used HDLs today. Both have constructs
with which the design can be fully described at all the levels.
• Verilog as an HDL was introduced by Cadence Design Systems; they placed it into the
public domain in 1990. It was established as a formal IEEE Standard in 1995. The revised
version has been brought out in 2001.

Verilog as HDL

Verilog has a variety of constructs as part of it. All are aimed at providing a functionally tested and a
verified design description for the target FPGA or ASIC.

The language has a dual function – one fulfilling the need for a design description and the other fulfilling
the need for verifying the design for functionality and timing constraints like propagation delay, critical
path delay, slack, setup, and hold times.

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Levels of Design Description

• The components of the target design can be described at different levels with the help of the constructs in Verilog.
• In Verilog HDL a module can be defined using various levels of abstraction. There are four levels of abstraction in
verilog.
They are: 1. Circuit Level 2. Gate Level 3. Data Flow Level 4. Behavioral Level

1. Circuit Level
• The below Figure1 shows the circuit of an inverter suitable for description with the switch level constructs of Verilog.
• At the circuit level, a switch is the basic element with which digital circuits are built.
• Switches can be combined to form inverters and other gates at the
next higher level of abstraction.
• Verilog has the basic MOS switches built into its constructs, which can be used to
build basic circuits like inverters, basic logic gates. Figure 1 CMOS inverter

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 Gate Level

• At the next higher level of abstraction, design is carried out in terms of basic gates.
• All the basic gates are available as ready modules called “Primitives.”
• Each such primitive is defined in terms of its inputs and outputs.
• Primitives can be incorporated into design descriptions directly.
Figure 2 shows an AND gate suitable for description using the gate primitive of Verilog.
Data Flow
• Data flow is the next higher level of abstraction.
• All possible operations on signals and variables are represented here in terms of assignments.
• The assignments define the continuous functioning of the concerned block.
• At the data flow level, signals are assigned through the data manipulating equations.
• All such assignments are concurrent in nature. The design descriptions are more compact than those at the
gate level.

Figure 3 shows an A-O-I relationship suitable for description with the Verilog constructs at the data flow level.

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 Behavioral Level

• Behavioral level constitutes the highest level of design description; it is essentially at the system level itself.
• With the assignment possibilities, looping constructs and conditional branching possible, the design description
essentially looks like a “C” program.

• A module can be implemented in terms of the design algorithm. The designer no need to have any knowledge of
hardware implementation.

Figure 4 shows an A-O-I gate expressed in pseudo code suitable for description with the behavioral level constructs
of Verilog.

The Overall Design Structure in Verilog

• The possibilities of design description statements and assignments at different levels necessitate their
accommodation in a mixed mode.
• Thus Verilog facilitates the mixing of the above-mentioned levels of design.
• A design built at data flow level can be instantiated to form a structural mode design. Data flow assignments can
be incorporated in designs which are basically at behavioral level.
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Concurrency

• In an electronic circuit all the units are to be active and functioning concurrently.
• The voltages and currents in the different elements in the circuit can change simultaneously.
• In turn the logic levels too can change. Simulation of such a circuit in an HDL calls for concurrency of
operation.
• A number of activities – may be spread over different modules – are to be run concurrently here.
Verilog simulators are built to simulate concurrency. (This is in contrast to programs in the normal
languages like C where execution is sequential.)
• Concurrency is achieved by proceeding with simulation in equal time steps.
• The time step is kept small enough to be negligible compared with the propagation delay values.
• In some cases the circuit itself may demand sequential operation as with data transfer and memory-
based operations. Only in such cases sequential operation is ensured by the appropriate usage of
sequential constructs from Verilog HDL.

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Simulation and Synthesis

➢ Simulation is a technique of applying different input stimulus to the design at different times to check if the
RTL code behaves the intended way. Essentially, simulation is a well-followed technique to verify the
robustness of the design.
➢ It is also similar to how a fabricated chip will be used in the real world and how it reacts to different inputs.
Synthesis
➢ The design that is specified and entered as described earlier is simulated for functionality and fully debugged.
Translation of the debugged design into the corresponding hardware circuit (using an FPGA or an ASIC) is called
“synthesis.”
➢ The tools available for synthesis relate more easily with the gate level and data flow level modules [Smith MJ].
The circuits realized from them are essentially direct translations of functions into circuit elements.
➢ In contrast many of the behavioral level constructs are not directly synthesizable; even if synthesized they are
likely to yield relatively redundant or wrong hardware.
➢ The way out is to take the behavioral level modules and redo each of them at lower levels. The process is carried
out successively with each of the behavioral level modules until practically the full design is available as a pack of
modules at gate and data flow levels (more commonly called the “RTL level”).

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 Programming Language Interface (PLI)

❖ PLI provides an active interface to a compiled Verilog module. The

interface adds a new dimension to working with Verilog routines from a
C platform. The key functions of the interface are as follows:
➢ One can read data from a file and pass it to a Verilog module as input.
Such data can be test vectors or other input data to the module. Similarly,
variables in Verilog modules can be accessed and their values written to
output devices.
➢ Delay values, logic values, etc., within a module can be accessed and
altered.
➢ Blocks written in C language can be linked to Verilog modules.

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 MODULE

➢ Any Verilog program begins with a keyword – called a “module.”

➢ A module is the name given to any system considering it as a block box with input and output terminals as
shown in Figure 1.
➢ The terminals of the module are referred to as ‘ports’.

➢ The ports attached to a module can be of three types:

▪ Input ports through which one gets entry into the module; they signify the input signal terminals of the module.
▪ Output ports through which one exits the module; these signify the output signal terminals of the module.
▪ Inout ports: These represent ports through which one gets entry into the module or exits the module; These
are terminals through which signals are input to the module sometimes; at some other times signals are output
from the module
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• In Verilog any program which forms a design description is a “module.”
• Any program written to test a design description is also a “module.”
• The latter are often called as “stimulus modules” or “test benches.”
• A module used to do simulation has the form shown in Figure 2.
• Verilog takes the active statements appearing between
the “module” statement and the “endmodule” statement
and interprets all of them together as forming the body of the module

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 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG
• Any source file in Verilog (as with any file in any other programming language) is made
up of a number of ASCII characters.
• The characters are grouped into sets — referred to as “lexical tokens.” A lexical token in Verilog can be
a single character or a group of characters.
• Verilog has 7 types of lexical tokens- operators, keywords, identifiers, white spaces, comments,
numbers, and strings.
❖ A module comprises a number of “lexical tokens” arranged according to some predefined order. The
possible tokens are of seven categories:
• White spaces
• Comments
• Operators
• Numbers
• Strings
• Identifier
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Case Sensitivity

Verilog is a case-sensitive language like C. Thus sense, Sense, SENSE, sENse,… etc., are all related as
different entities / quantities in Verilog.
Keywords

• The keywords define the language constructs.

• A keyword signifies an activity to be carried out, initiated, or terminated.
• As such, a programmer cannot use a keyword for any purpose other than that it is intended for.
• All keywords in Verilog are in small letters and require to be used as such (since Verilog is a case-sensitive
language). All keywords appear in the text in New Courier Bold-type letters.
Examples

module -- signifies the beginning of a module definition. endmodule -- signifies

the end of a module definition.
begin -- signifies the beginning of a block of statements. end --signifies the end of a
block of statements.
if -- signifies a conditional activity to be checked while -- signifies a conditional
activity to be carried out.
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Identifiers

• Any program requires blocks of statements, signals, etc., to be identified with an attached nametag.
• Such nametags are identifiers.
• It is good practice for us to use identifiers, closely related to the significance of variable, signal, block, etc.,
concerned.
e.g., clock, enable, gate_1, . . .
• There are some restrictions in assigning identifier names.
• All characters of the alphabet or an underscore can be used as the first character.
• Subsequent characters can be of alphanumeric type, or the underscore (_), or the dollar ($) sign –

for example : name, _name. Name, name1, name_$, . . . -- all these are allowed as identifiers

• name aa -- not allowed as an identifier because of the blank ( “name” and “aa” are interpreted as two different
identifiers)
• $name -- not allowed as an identifier because of the presence of “$” as the first character. 1_name -- not
allowed as an identifier, since the numeral “1” is the first character

• @name -- not allowed as an identifier because of the presence of the character “@”. A+b m not allowed
as an identifier because of the presence of the character “+”.

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White Space Characters

• Blanks (\b), tabs (\t), newlines (\n)------- white space characters in Verilog.
• In any design description the white space characters are included to improve readability.
• Functionally, they separate legal tokens.
• They are introduced between keywords, keyword and an identifier, between two identifiers, between
identifiers and operator symbols, and so on.
• White space characters have significance only when they appear inside strings.
Comments

• Comments can be inserted in the code for readability and documentation.

• There are two ways to write comments. A one-line comment starts with "//".
• Verilog skips from that point to the end of line. A multiple-line comment starts with "/*" and ends with
"*/". Multiple-line comments cannot be nested.
• However, one-line comments can be embedded in multiple-line comments.

a = b && c; // This is a one-line comment

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Operators
• Operators are of three types: unary, binary, and ternary.
• Unary operators precede the operand.
• Binary operators appear between two operands.
• Ternary operators have two separate operators that separate three operands.Eg,
a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands

Number Specification
There are two types of number specification in Verilog: sized and unsized.

Sized numbers
• Sized numbers are represented as <size> '<base format> <number>.
• <size> is written only in decimal and specifies the number of bits in the number.
• Legal base formats are decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or 'B) and octal ('o or 'O).
• The number is specified as consecutive digits from 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f.

4'b1111 // This is a 4-bit binary number

12'habc // This is a 12-bit hexadecimal number

16'd255 // This is a 16-bit decimal number.

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Unsized numbers

• Numbers that are specified without a <base format> specification are decimal numbers by default.
• Numbers that are written without a <size> specification have a default number of bits that is simulator- and
machine-specific (must be at least 32).
X or Z values

• Verilog has two symbols for unknown and high impedance values.
• These values are very important for modeling real circuits.
• An unknown value is denoted by an x. A high impedance value is denoted by z.
12'h13x // This is a 12-bit hex number; 4 least significant bits unknown
6'hx // This is a 6-bit hex number
32'bz // This is a 32-bit high impedance number
Negative numbers

Negative numbers can be specified by putting a minus sign before the size for a constant number. Size constants
are always positive. It is illegal to have a minus sign between <base format> and <number>. An optional signed
specifier can be added for signed arithmetic.
-6'd3 // 8-bit negative number stored as 2's complement of 3
-6'sd3 // Used for performing signed integer math
4'd-2 // Illegal specification
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Underscore characters and question marks

• An underscore character "_" is allowed anywhere in a number except the first character. Underscore
characters are allowed only to improve readability of numbers and are ignored by Verilog.
A question mark "?" is the Verilog HDL alternative for z in the context of numbers. 12'b1111_0000_1010 //
Use of underline characters for readability
4'b10?? // Equivalent of a 4'b10zz

Strings

A string is a sequence of characters that are enclosed by double quotes. The restriction on a string is that it must be
contained on a single line, that is, without a carriage return. It cannot be on multiple lines. Strings are treated as a
sequence of one-byte ASCII values.

"Hello Verilog World" // is a string "a / b" // is a string

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Strengths

• The logic levels are also associated with strengths.

• In many digital circuits, multiple assignments are often combined to reduce silicon area or to reduce pin-outs.
• To facilitate this, one can assign strengths to logic levels.
• Verilog has eight strength levels – four of these are of the driving type, three are of capacitive type and one of
the hi-Z type. Strength Level Type Degree

supply Driving strongest

strong Driving

pull riving

large Storage ↑
weak Driving

medium Storage

small Storage

highz High Impedance weakest

• In addition to logic values, strength levels are often used to resolve conflicts between drivers of different
strengths in digital circuits
• If two signals of strength strong1 and weak0 contend, the result is resolved as a strong1.
• If two signals of equal strengths are driven on a wire, the result is unknown.
• If two signals of strength strong1 and strong0 conflict, the result is an x. Strength levels are particularly
useful for accurate modeling of signal contention, MOS devices, dynamic MOS, and other low-level devices.
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 Data Types

The data handled in Verilog fall into two categories:

(i) Net data type
(ii) Variable data type

• The two types differ in the way they are used as well as with regard to their respective hardware structures.
• Data type of each variable or signal has to be declared prior to its use.
• The same is valid within the concerned block or module.

Nets
• A net signifies a connection from one circuit unit to another.
• Such a net carries the value of the signal it is connected to and transmits to the circuit blocks connected to it.
• If the driving end of a net is left floating, the net goes to the high impedance state.
• A net can be specified in different ways.
wire: It represents a simple wire doing an interconnection. Only one output is connected to a wire and is driven by that.

tri: It represents a simple signal line as a wire. Unlike the wire, a tri can be driven by more than one signal outputs.
• Nets are one-bit values by default unless they are declared explicitly as vectors.
• The terms wire and net are often used interchangeably.

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Variable Data Type

• A variable is an abstraction for a storage device.

• It can be declared through the keyword reg and stores the value of a logic level: 0, 1, x, or z.
• A net or wire connected to a reg takes on the value stored in the reg and can be used as input to other
circuit elements.
• The value stored in a reg is changed through a fresh assignment in the program.

time, integer, real, and realtime are the other variable types of data;

Time
• Verilog simulation is done with respect to simulation time.
• A special time register data type is used in Verilog to store simulation time.
• A time variable is declared with the keyword time.
• The width for time register data types is implementation-specific but is at least 64 bits.
• The system function $time is invoked to get the current simulation time.

time save_sim_time; // Define a time variable save_sim_time initial save_sim_time =$time;

// Save the current simulation time

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Scalars and Vectors

• Entities representing single bits — whether the bit is stored, changed, or transferred — are called “scalars.”
• Often multiple lines carry signals in a cluster – like data bus, address bus, and so on.
• Similarly, a group of regs stores a value, which may be assigned, changed, and handled together.
• The collection here is treated as a “vector.”
• Figure below illustrates the difference between a scalar and a vector.
• wr and rd are two scalar nets connecting two circuit blocks circuit1 and circuit2.
• b is a 4-bit-wide vector net connecting the same two blocks. b[0], b[1], b[2], and b[3] are the individual bits of
vector b. They are “part vectors.”
Examples:

wire[3:0] a; /* a is a four bit vector of net type;

the bits are designated as a[3], a[2], a[1] and a[0]. */
reg[2:0] b; /* b is a three bit vector of reg type;
the bits are designated as b[2], b[1] and b[0]. */
reg[4:2] c; /* c is a three bit vector of reg type;
the bits are designated as c[4], c[3] and c[2].*/
wire[-2:2] d ; /* d is a 5 bit vector with individual bits
designated as
24 January d[-2], d[-1], d[0], d[1] and d[2]. */
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