Visvesvaraya Technological University, Belagavi-

590018, Karnataka

University B.D.T. College of Engineering

Department of Electronics & Instrumentation Engineering
(Govt. of Karnataka & AICTE Approved, Affiliated to VTU)
A Constituent College of VTU, Belagavi

Davangere - 577004, Karnataka, India

Laboratory Manual
Digital Design and HDL Laboratory
(18EIL38)
Semester-III
202- 2

Name: _________________________________

USN: _________________________________

Prepared By
Smt. Pushpalatha S A
Associate Professor, Dept. of E&IE, UBDTCE, Davangere

Smt. Rachna H B
Assistant Professor (Ad-Hoc), Dept. of E&IE, UBDTCE, Davangere
 INSTITUTE VISION
To be a Centre-of-Excellence in engineering education, technology and research with an emphasis on
regional and societal needs.

INSTITUTE MISSION
 To impart quality technical education through practice based teaching-learning process in the present
and emerging technological scenario.
 To inculcate employability skills, research culture, entrepreneurship, and human values.

DEPARTMENT VISION

To achieve excellence by imparting quality technical education in a progressive teaching learning

environment to make the program a top choice for undergraduate and research studies.

DEPARTMENT MISSION
 To prepare professionally skilled and technically competent Electronics & Instrumentation Engineers
to meet the needs of modern industry and emerging technology.
 To inculcate the spirit of entrepreneurship, passion to work, professional attitude, innovation, and
human values to create knowledge centric society.

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

1. The Program aims to inculcate professional skills to produce globally competent Electronics &
Instrumentation Engineers.
2. The graduates of Electronics & Instrumentation engineering will be able to analyze, design, develop
and realize solutions to complex engineering problems of their specialization.
3. The graduates continue to develop professionally through life-long learning, higher education, and
other creative pursuits in advanced technology, with professional ethics, social and human values.

PROGRAM OUTCOMES (POs)

1. Engineering Knowledge: Apply the knowledge of mathematics, science, engineering fundamentals,
and an engineering specialization to the solution of complex engineering problems.
2. Problem Analysis: Identify, formulate, research literature, and analyze complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural sciences,
and engineering sciences.
3. Design/Development of Solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the
public health and safety, and the cultural, societal, and environmental considerations.
4. Conduct Investigations of Complex Problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern Tool Usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
6. The Engineer and Society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal, and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.

7. Environment and Sustainability: Understand the impact of the professional engineering solutions
in societal and environmental contexts, and demonstrate the knowledge of need for sustainable
development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of
the engineering practice.

9. Individual and Team Work: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports
and design documentation, make effective presentations, and give and receive clear instructions.

11. Project Management and Finance: Demonstrate knowledge and understanding of the engineering
and management principles and apply these to one‘s own work, as a member and leader in a team, to
manage projects and in multidisciplinary environments.

12. Life-long Learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs)

1. PSO-1: Demonstrate the use of electronic circuits design, communication technology and
programming in development of embedded systems for industrial and real-time applications.

2. PSO-2: Adapt the basic concepts of instrumentation and measurement, signal conditioning and
controlling for industrial automation.
 Digital Design and HDL Laboratory
Experiments
Sub code : BEI302 (IPCC) Hours/ Week:2 Total Hours:24 CIE marks: 20
Sl. No. Name of the Experiments Page No.
Design and test BJT Common emitter voltage amplifier without feedback
for the given specification. Also determine the gain-bandwidth product,
1 input, and output impedance 2-6

Design and test BJT Common emitter voltage amplifier with feedback for
the given specification. Also determine the gain-bandwidth product, input,
2 and output impedances 7-10

3 Conduct an experiment to draw the Drain and Transfer characteristics of

JFET 11-13
Conduct an experiment to test of Complementary symmetry class B push-
4 pull 14-17
Amplifier
5 Design and conduct Crystal oscillator using BJT 18-20
6 Design and conduct Instrumentation amplifier using three operational 21-23
amplifiers
Design and test Astable and Monostable Multivibrator circuits using 555
7 Timer 24-28
For different duty cycle.
8 Conduct an experiment to verify Static V –I characteristics of UJT 29-32
Demonstration Experiments (For CIE)
9 Study of the Drain and Transfer characteristics of MOSFET. 33-37
10 Study of the Common Source JFET amplifier and plot its frequency 38-41
response
11 Study of RC phase shift oscillator using BJT 42-44
12 Study of Tuned oscillator circuit for the given frequency of Hartley oscillator. 45-46

Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:

1. Analyze the performance parameters of BJT circuits using re and approximate Hybrid model.
2. Explain the construction, working, and performance parameters of JFET and MOSFET.
3. Evaluate the performance of FET amplifiers and Power amplifiers.
4. Analyze the performance parameters of 555 Timer application circuits.

CO-PO-PSO CORRELATION MATRIX

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO1 3 2 3 2 - - - 1 2 1 - 1 3 -

CO2 3 2 3 2 - - - 1 2 1 - 1 3 -

CO3 2 2 3 2 - - - 1 2 1 - 1 3 -

CO4 2 2 3 2 - - - 1 2 1 - 1 3 -
 -:INDEX:-

SL PAGE
EXPERIMENTS
NO NO

1
Simplification of Boolean Expression Using K-Map

Design and Implementation of HALF ADDER,FULL ADDER

and
2
HALF SUBTRACTOR,FULL SUBTRACTOR using Logic Gates
Parallel Adder/Subtractor using IC 7483 Chip

Realisation of Binary to Grey Conversion and Vice-Versa

3 Single Bit Comparator Two Bit Comparator
Priority Encoder

4 Verification of Flip-flops

5 Design and Implementation of Mod-N Counter

Adder and Subtractor Circuit using Verilog dataflow

6
Description

7 Flip-Flops using Verilog Behavioural Description

8 3 bit Counters using Verilog Behavioural Description

Realisation of Logic Gates

2 Input AND 7408

Truth Table
A B C
0 0 0
0 1 0
1 0 0
1 1 1

3 Input AND 7411

Truth Table
A B C D
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
2 Input OR 7432

Truth Table
A B C
0 0 0
0 1 1
1 0 1
1 1 1

NOT 7404

Truth Table
A A|
0 1
1 0
2 Input EXOR 7486

Truth Table

A B C
0 0 0
0 1 1
1 0 1
1 1 0

2 Input NOR 7402

Truth Table

A B C
0 0 1
0 1 0
1 0 0
1 1 0
2 Input NAND 7400/7426

Truth Table
A B C
0 0 1
0 1 1
1 0 1
1 1 0
Realisation of Basic Gates using Universal Gates

1. Using NAND Gates

NAND as AND Truth Table

A B AB
0 0 0
0 1 0
1 0 0
1 1 1

NAND as OR

Truth Table
A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

NAND as NOT

Truth Table

A A|
0 1
1 0

NAND as NOR Truth Table

A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
NAND as EX-OR Truth Table
A B 𝐴 𝐵
0 0 0
0 1 1
1 0 1
1 1 0

2. Using NOR Gate

NOR as AND

Truth Table
A B AB
0 0 0
0 1 0
1 0 0
1 1 1

NOR as OR Truth Table

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

NOR as NOT

Truth Table

A A|
0 1
1 0
NOR as NAND
Truth Table

A B (AB)’
0 0 1
0 1 1
1 0 1
1 1 0

NOR as EX-OR
Truth Table
A B 𝐴 𝐵
0 0 0
0 1 1
1 0 1
1 1 0
 SIMPLIFICATION OF BOOLEAN EXPRESSION USING K-MAP
Aim: To simply the Boolean Expressions using K-Map.

Components Reqiured: IC 7400,7402, IC Trainer Kit, Path chords.

Theory: A Karnaugh Map(K-Map) is a pictorial or graphical display of

the fundamental product in a truth table. K-map is nothing but a
rectangle made up of creation number of squares, each square representing a
maxterm/minterm.

Procedure:
1. Connections are made as shown in Figure.
2. Refer Pin diagrams for connections.
3. Connect all IC’s which take point in circuit to ground and VCC.
4. Switch on the kit power supply and note down output for all
possible combination of input.

1. Q=f(a,b,c)=∑(1, 2, 3, 6, 7)

Truth Table

a b c Q=b+a’c
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
Q=f(a,b,c)=b+a’c 1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
2. Q=f(a,b,c,d)=∑(O, 2, 5, 7, 8, 1O, 13, 15)

Truth Table

a b c d L=b’d’+bd
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 1
Q=f(a,b,c,d)=bd+b’d’ 1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

3. P=f(a,b,c,d)=∑(O, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) Truth Table

a b c d P=c’+a’d’+bd’
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
P=f(a,b,c,d)=c’+a’d’+bd’ 1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
DESIGN AND IMPLEMENTATION OF HALF ADDER, FULL ADDER ,HALF
SUBTRACTOR,FULL SUBTRACTOR USING LOGIC GATES.
Aim: To realize half adder,fulladder,half & full subtractor using gates.

Components Required: IC 7408,7432,7404,7486, IC Trainer Kit, Path chords.

Theory:

1] Half adder: The addition of 2 bits is done using a combinational circuit called
half adder. The input variables are augend and addend bits and output
variables are sum and carry bits.

2] Full adder : The full adder is the adder which adds three input and produces
two outputs, The first two inputs are A and B (auged and addend) and the third
input is an input carry as Cin, The output carry is designated as count and
another output is (S),

3] Half subtractor : The binary Half subtractor subtracts two input bits and
gives two output bits with one of them determining the difference (D) and the
other is giving the borrow bit (Br).

4] Full subtractor : The Full substractor is a combinational circuit which is used

to performs substraction of three input bits, The minuend, subtrated and
borrow in, The full subtractor generates two outputs, The difference and the
borrow out.

Half Adder

A B S C

0 0 0 0 S=A’B+AB’=𝐴
0 1 1 0
𝐵 C=AB
1 0 1 0
1 1 0 1
 A Adder
Full B C S Ci S=𝐴 𝐵 𝐶i
0 0 0 0 0
0 0 1 1 0 C=BCi+ACi+AB
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Half Subtractor D=𝐴

A B D Br 𝐵 Br=A’
0 0 0 0
0 1 1 1 B
1 0 1 0
1 1 0 0

Full Subtractor
D=A 𝐵 𝐵in
X Y Bin D Br
0 0 0 0 0
0 0 1 1 1 Br=BBin+A’B+A’Bin
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Procedure:

*] Check all the components are in good condition or not .

*] Develop the truth table.

*] Write the Boolean expression .

*] Make connections as shown in circuit diagram.

*] Connect pin no, 14 to Vcc and pin no, 7 to ground for each IC.

*] Switch ON the supply of trainer kit.

*] Verify the truth table sequence by using switches to provides input and
observe the output.

Result: Verified Half adder, Full adder, Half subtractor and Full subtractor.
 PARALLEL ADDER/SUBTRACTOR USING 7483 IC CHIP
AIM : To design and set up the following circuit using IC 7483
a] 4 - bit binary parallel adder.
b] 4 – bit binary parallel substractor .

Components required : IC 7483,7486, IC Trainer Kit, Patch chords.

Theory :

1. Parallel Adder ; A single full adder performs the addition of two onbe bit
numbers and an input carry “Parallel Adder” is a digital circuit capable of
finding the arithmetic sum of two binary numbers that is greater than one bit
in length by operating on corresponding pairs of bits in parallel. It consist of full
adders connected in a chain where the output carry from each full adder is fed
to carry input of the next high order full adder in the chain.

2. Parallel Subtractor: A n-bit parallel subtractor is used to subtract a number

consisting of n-bits. We get a n-bit parallel subtractor by cascading a series of
full subtractors.

For adder circuit For subtractor circuit

Cin=0 Cin=1
Tabular Column

Adder Circuit

A3 A2 A1 A0 B3 B2 B1 B0 Cin S3 S2 S1 S0 Cout
1 0 0 0 0 1 0 0 0 1 1 0 0 0
1 0 0 1 0 0 1 0 0 1 0 1 1 0
1 0 1 0 0 0 0 1 0 1 0 1 1 0
0 1 0 0 0 0 1 1 0 0 1 1 1 0
0 1 0 1 0 0 1 0 0 0 1 1 1 0

Subtractor Circuit

A3 A2 A1 A0 B3 B2 B1 B0 Cin S3 S2 S1 S0 Cout
1 0 0 0 0 0 1 0 1 0 1 1 0 1
1 0 1 0 0 1 0 0 1 0 1 1 0 1
1 1 0 0 1 0 0 0 1 0 1 0 0 1
1 1 1 1 1 0 0 1 1 0 1 1 0 1
0 1 0 1 0 0 1 0 1 0 1 0 0 1

Procedure:

*Make the connections as shown in figure.

*For Addition make Cin=0 and apply 4 bits of input for A and apply a set of 4bit
to B.

*Observe output at S3,S2,S1,S0 and carry generated at Cout. Repeat the steps
for different inputs and tabulate the results.

*For subtraction make Cin=1 and add EX-OR gate at the input side of B.

*Verify difference at S0,S1,S2,S3 and Cout.

*Repeat the above steps and tabulate the results.

*If Cout is 1, difference is +ve and if Cout is 0 difference is –ve.

Result: Parallel adder and subtractor is verified using tabular column.

 REALISATION OF BINARY TO GRAY CONVERSION AND VICE-VERSA
Aim: To convert Binary to Gray and vice versa.

Components required: IC trainer kit, IC7486, Patch chords.

Theory:

Binary to Gray: It is a code converter which is used to convert the binary code
into its equivalent gray code.

Gray to Binary: It is a code converter which is used to convert the gray code
into its equivalent binary code.

Code Conversion of Binary to Gray

Decimal B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
G3=B3
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 1
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0
Code Conversion of Gray to Binary

Decimal G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 0 1 1 0
6 0 1 1 0 0 1 0 0
7 0 1 1 1 0 1 0 1
8 1 0 0 0 1 1 1 1
9 1 0 0 1 1 1 1 0
10 1 0 1 0 1 1 0 0
11 1 0 1 1 1 1 0 1
12 1 1 0 0 1 0 0 0
13 1 1 0 1 1 0 0 1
14 1 1 1 0 1 0 1 1
15 1 1 1 1 1 0 1 0
Procedure:

*Connections are made as shown in circuit diagram.

*Fix IC to IC trainer kit.
*connect 7 to GND and 14 to Vcc.
*Verify the truth table respectively.

Result: The truth table is verified for code conversion of Binary to Gray and
vice-versa.
 SINGLE BIT COMPARATOR.
Aim: To compare between 2 bits and verify the truth table using comparator.

Components required: IC trainer kit, IC7486,IC7404,IC7408, and patch chords.

Theory:
A comparator used to compare two bits is called a single bit comparator. It
consist of two inputs each for two single bit numbers and three outputs to
generate less than, equal to and greater than between two binary numbers.

A B G E L
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

Procedure:
*Fix all IC to IC trainer kit.
*Connect 7 to GND and 14 to Vcc.
*Connections are made as shown in circuit diagram.
*Verify truth table respectively.

Result: Hence the Truth Table is verified.

 TWO BIT COMPARATOR.

Aim: To obtain two bit comparator using logic gates.

Components Required: IC trainer kit,IC7404,IC7408,IC7486,IC7432,Patch

chords.

Theory:
A Comparator used to compare two binary numbers each of two is called 2 bit
comparator. Its consists of four inputs and three outputs to generate less than,
equal and greater than between two binary numbers.

A1 A0 B1 B0 G E L
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

G=A1B1’+A0B0’(A1+B1’)

E=A0⊙B0⊙A1⊙B1

L=A0’B0(A1’+B1)+A1’B1

Procedure:
*Fix the IC to IC trainer kit.
*Connections are made as shown in circuit diagram.
*Verify the truth table respectively.

Result: Hence the Truth Table is verified.

 PRIORITY ENCODER .

Aim: Realization of truth table for priority encoder.

Components Required: IC trainer kit, IC 74148,Patch chords.

Theory:
A encoder is a combinational circuit that performs the reverse operation of
decoder. It has maximum of 2n input lines and ‘n’ output lines.

EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS
1 X X X X X X X X 1 1 1 1
0 X X X X X X X 0 0 0 0 0
0 X X X X X X 0 1 0 0 1 0
0 X X X X X 0 1 1 0 1 0 0
0 X X X X 0 1 1 1 0 1 1 0
0 X X X 0 1 1 1 1 1 0 0 0
0 X X 0 1 1 1 1 1 1 0 1 0
0 X 0 1 1 1 1 1 1 1 0 1 0
0 0 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 1 1 1 1 1

Procedure:
*Connect IC to IC trainer kit.
*Connections are made as shown in figure.
*Verify the truth table respectively.

Result: Hence the Truth Table is verified.

 VERIFICATION OF FLIPFLOPS.
Aim: Truth table verification of flip-flops.
1) JK Master Slave flip-flop.
2) T-type flip-flop.
3) D-type flip-flop

Components Required: IC trainer kit,IC7400,IC7410,patch chords

Theory:
1) JK-Master Slave flip-flop.
The master slave flip-flop both master and slave are enabled alternately. When
clock pulse is high master gets enabled and when clock pulse is high master
gets enabled and when clock pulse is low slave gets enabled. In JK flip-flop the
function is similar to SR flipflop, but during S=R=1 the output Q+=1&Q’+=1 is
overcome by toggling effect in JK flip-flop[i.e.Q+=Q’ & Q+’=Q].

2) T-flip-flop.
In T-flip-flop the JK flip-flop is connected to single in-put as shown in figure
(B).Here when T input is high and clock is high the output of the flip-flop
toggles [i.e. Q+=Q’ & Q+’=Q]

3) D-flip-flop.
In D-flip-flop, the gated SR flip-flop is given single input D, where one input S is
directly connected through not gate to input D. This flip-flop performs the
function of data transfer when clock is high.
Master Slave JK Flip-Flop
 Clock J K Qn+1 (Qn+1)’ Result
↑ 0 0 Qn (Qn)’ No Change
↑ 0 1 0 1 Reset
↑ 1 0 1 0 Set
↑ 1 1 (Qn)’ Qn Toggle
0 X X Qn (Qn)’ No Change

T-Flip-Flop

Clock T Q (Q)’ Result

↑ 0 Q (Q)’ No Change
↑ 1 (Q)’ Q Toggle
0 X Q (Q)’ No Change

D Flip-Flop
 Clock D Q (Q)’ Result
↑ 0 0 1 Reset
↑ 1 1 0 Set
0 X Q (Q)’ No Change

Procedure:
*Connect IC of each flipflop separately to IC trainer kit.
*Make the connections as shown in figure.
*Verify the truth table respectively.

Result: Hence the Truth Table is verified.

DESIGN AND IMPLEMENTATION OF MOD-N COUNTER.

Aim: Design and implementation of synchronous counter.

Components required: IC7476,Patch chords,IC7408,IC trainer kit.

Theory:
Synchronous counter is a counter consisting of an inter connected series of
flip-flop in which all the flip-flops output change state at the same instant,
normally on application of pulse at the counter input.

Excitation Table
Q1 Q2 Q3 Q1 Q2* Q3 J1 K1 J3 K2 J3 K3
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
Clock Q1 Q2 Q3
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Procedure:
*Connect IC to IC trainer kit.
*Make the connections as shown in figure.
*Verify the truth table respectively.

Result: Hence the Truth Table is verified.

 ADDER AND SUBTRACTOR CIRCUIT USING VERILOG DATA FLOW

DESCRIPTION.
1) Half Adder

module half_adder (a,b,S,C);

input a,b;

output S,C;

assign S=a^b;

assign C=a&b;

endmodule

2) Full adder

module full_adder (a,b,c,S,Ci);

input a,b,c;

output S,Ci;

assign S=a^b^c;

assign Ci=(a&b)|(a&c)|(b&c);

endmodule
3) Half subtractor

module half_sub (a,b,D,B);

input a,b;

output D,B;

assign D=a^b;

assign B=(~a)&b;

endmodule

4) Full subtractor

module full-sub(a,b,c,D,Br);

Input a,b,c;

Output D,Br;

assign D=a^b^c;

assign Br=((~a)&b)|((~a)&c)|(b&c);

endmodule
 FLIP-FLOPS USING VERILOG BEHAVIOURAL DISCRIPTION
1) JK Flip-Flop

module JK_ff(

input [1:0]JK,

input clk,

output q,qb

);

Reg q,qb;

always@ (posedge clk)

begin

case (JK)

2’d0:q=q;

2’d1:q=0;

2’d2:q=1;

2’d3:q=~q;

Endcase

qb=~q;

end

endmodule
2) D Flip-Flop
module D_ff(

input D,clk,

output q,qb

);

reg q,qb;

always @ (posedge clk)

begin

case (D)

1’b0:q=0;

1’b1:q=1;

endcase

qb=~q;

end

endmodule
3) SR Flip-Flop

module SR_ff(

input [1:0]SR,

input clk,

output q,qb

);

reg q,qb;

always@ (posedge clk)

begin

case (SR)

2’d0:q=q;

2’d1:q=1;

2’d2:q=0;

2’d3:q=1’bx;

Endcase

qb=~q;

end

endmodule
4) T Flip-Flop

module T_ff(

input T,clk,

output q,qb

);

reg q,qb;

always@ (posedge clk)

begin

case (T)

1’b0:q=1’b0;

1’b1:q=(~q);

endcase

qb=~q;

end

endmodule
 3 BIT UP COUNTER USING VERILOG BEHAVIOURAL DISCRIPTION.
module Counter_3_bit(
input clr, clk,
output [2:0]q
);
reg [2:0]q;
initial
q=3’b111;
always @ (posedge clk)
begin
if (clr==0)
begin

case(q)

3’d0:q=3’d1;

3’d1:q=3’d2;

3’d2:q=3’d3;

3’d3:q=3’d4;

3’d4:q=3’d5;

3’d5:q=3’d6;

3’d6:q=3’d7;

3’d7:q=3’d0;

endcase

end

else

q=3’dz;

end

endmodule
 3 BIT DOWN COUNTER USING VERILOG BEHAVIOURAL DISCRIPTION.

module Counter_3_bit_down(
input clr,clk,
output [2:0]q
);
reg [2:0]q;
initial
q=3’b000;
always @ (posedge clk)
begin
if (clr==0)
begin

case (q)

3’d0:q=3’d7;

3’d7:q=3’d6;

3’d6:q=3’d5;

3’d5:q=3’d4;

3’d4:q=3’d3;

3’d3:q=3’d2;

3’d2:q=3’d1;

3’d1:q=3’d0;

endcase

end

else

q=3’dz;

end

endmodule