Rohit Vippagunta

Dallas, TX | +1 945-246-0140 | [email protected] | linkedin

EDUCATION
The University of Texas at Dallas, Richardson TX Graduated May 2024
Masters of Science in Electrical and Electronics Engineering GPA 3.7/4.0
Courses: ASIC Design, Functional Verification, Computer Architecture, VLSI Design, Reconfigurable Systems, Testing Designs,
Microprocessor and Embedded Systems, Advanced Digital Logic, Analog IC Systems.
National Institute of Technology, Puducherry, India Graduated April 2021
Bachelors of Technology in Electronics and Communication Engineering GPA 7.3/10

TECHNICAL SKILLS
Tools: Virtuoso, DesignCompiler, Hspice, WaveView, SiliconSmart, Library Compiler, Genus, Innovus, Encounter, Design Compiler, IC
Compiler, Tempus, PrimeTime, VCS, ISE Vivado, Icarus Verilog, ModelSim, VCS Code Coverage, IMC, Confrml, Formality, Tetramax,
Modus, Quartus Prime Lite, Vivado HLx, NEC CyberWorkbench.
Scripting Languages: Python, C, C++, Bash, Perl.
Operating Systems: Linux, Windows.
Certifications : SystemVerilog for Design and Verification (Cadence), Basic Static Timing Analysis (Cadence),
PROJECTS
ASIC Design of Mini Stereo Digital Audio Processing (MSDAP) chip
● Designed a C-modeled golden reference and developed hardware behavioral models for the MSDAP chip.
● Executed the full RTL-to-GDSII flow, including RTL development, synthesis, place-and-route (PnR), UPF, clock tree synthesis (CTS),
Power Analysis and static timing analysis (STA)
● Performed sign-off checks, including DRC and LVS, leading to a successful tapeout.
Design and Implementation of a Scan-Enabled Circuit with Timing Closure Optimization
● Developed RTL code, created a comprehensive testbench to ensure high code coverage, synthesized the design using a 45nm
technology library, and conducted formal verification using LEC to validate the netlist's correctness.
● Implemented floorplanning, placement, clock tree synthesis, routing, and power analysis, followed by gate-level simulation to verify
functional correctness. Performed timing closure by addressing hold violations with delay cells.
Verification of 4- Ports Switch Using UVM
● Performed detailed verification of switch design in UVM, developed necessary blocks such as sequencer, driver, agent, interface and
other blocks for UVM implementation. Data packets with randomized parameter conditions like singlecast, multicast with randomized
data value are used to achieve greater functional coverage.
Memory Testing Using Scope-Based Randomization
● Developed a memory testbench to use constrained scope-based randomization for data and address values. Added constraints like
limit data to be a printable ASCII character, weights to the constraints so that 80% of the time, randomization chooses an uppercase
letter and 20% of the time it chooses a lowercase letter.
Optimizing Functional Coverage for Memory Systems
● Implemented functional coverage in a memory testbench by adding covergroups for address and data values. Simulated using
Cadence tools and analyzed coverage with IMC. Refined coverage model to optimize sampling for the “Random Data” test.
Enhancing Cross Coverage in ALU Testing
● Enhanced ALU testbench by adding cross coverage for opcode, accum, and data inputs. Reduced irrelevant cross-coverage bins
based on opcode functionality. Refined stimulus to cover gaps in high/low data value distributions.
Verification of 8-bit RISC CPU
● Assembled CPU components including the Program Counter, MUX, Memory, Instruction Register, Accumulator Register, and ALU.
Performed verification of RISC CPU using three diagnostic programs with microcode for various operations, ensuring the operating
correctness of the CPU through comprehensive testing and debugging.
DFT by Scan Chain insertion
● Designed a sequential circuit in Synopsys Design vision, then incorporated scan flip-flops (SFFs) with scan chain insertion to improve
test coverage. It improved from 68% to 100% with its trade-offs, i.e., area increase of 140%.
FPGA Implemented Artificial Neural Network – Intel Quartus Prime Lite
● A handwritten digit recognition HW/SW co-design implemented on Cyclone-V board. It includes a trained ANN in its FPGA component
as well as an AXI interface for sending picture data to hardware. The Powerplay Analyzer tool was used to estimate power
consumption. The accuracy was around 92%, and 10,023 ALMs were used.
8-bit Pipelined CPU Design – Xilinx Vivado
● Designed a functional 8-bit four-stage pipelined RISC microcontroller. Data hazard and Branch Hazard conditions are handled using
stalls and reset. Synthesized and implemented it on a FPGA board [Digilent Nexys A7 - 100T].

WORK EXPERIENCE
Hardware Trainee Engineer December 2020 - April 2022
● Worked alongside a team developing RTL for a high-speed interface chip.
● Assisted in scripting automation processes using Python and Bash to streamline design verification and testing workflows.
Product Development Intern – RoboSlog June 2020 - July 2020
● Involved in design and development of heart pulse monitor module which includes an ARM3 microprocessor and an ECG
sensor (MAX3000T).