VLSI System Design (Graduate Level) Fall 2022

Innovus

Speaker: Chun-Sheng Cheng

Instructor: Lih-Yih Chiou
Date: 2022.11.09

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 VLSI System Design (Graduate Level) Fall 2022

Outline
Introduction
Import design
Floorplan
Powerplan
Clock Tree Synthesis
Routing
DRC / LVS / Antenna
Save / Export Files
Report Design
Reference

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 VLSI System Design (Graduate Level) Fall 2022

Introduction
Innovus, successor of SoC Encounter, which developed by
Cadence, is an Automatic Placement & Routing (APR) tool.
With this tool, you can export the synthesized gate level netlist to
the GDS layout.
GDS: Graphic Design System, a database file format for IC layout

Import Floorplan Powerplan Placeplan CTS Routing

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Open GUI
[innovus/build] $ innovus Do not use &
[innovus] $ make innovus
In this exercise & homework

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Import design

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Set the design constraints

Uniquify instantiated cell types
Let the multiple modules have different name, which means each module is
different.
For example, there are 2 SRAM modules, but they are different. If we don’t
uniquify the modules, the process will stop and have errors.

Prevent tool from adding any new assign statements to the

Verilog netlist

Low Power High Performance VLSI Design Lab

 VLSI System Design (Graduate Level) Fall 2022

Import Design
1.

2.

4.

file in ./script/

5.

6.
3.

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Default.globals
Design setup, including the design node LEF file and the MMMC
view file.
LEF file: Physical library, including process technology and APR technology

LEF File

MMMC View

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MMMC View
MMMC: Multi-Mode Multi Corner
Using different constraints to optimize the design
Timing libraries(Max, Min, Typical)
Capacitance Table

Capacitance table

Different timing library(Max, Min, Typical

Design constraint
Combine timing & RC table to create delay corner

Set different analysis view for different timing issues

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IO Pins(1/2)

7
1
2 8

4
5 10

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IO Pins(2/2)

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Floorplan
Place the macro

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First Floorplan View

1.

Submodules Core Area

Macros

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Purpose and Set environment

Purposes
IO Pads locations, Power pads number and location
Macro placement, such as memory
Placement & Routing blockage
Set environment
Remove assign statements from the Verilog

Set process mode

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Connect Global Nets

1.

2.
3.

4.

5.
6.

Repeat Step 3. -> 7.

7.
First: VCC
Second: GND 8. 9. 10.

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Specify Floorplan
1.

2.
Height/Width ratio

3.
4.

𝑠𝑡𝑑 𝑐𝑒𝑙𝑙 + 𝑚𝑎𝑐𝑟𝑜 𝑐𝑒𝑙𝑙

Core utilization =
𝑐𝑜𝑟𝑒 𝑎𝑟𝑒𝑎

5.

6.

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Plan Design(1/4)
1.

2.

3.

Result in physical view

You can use this icon to move macro 4.

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Plan Design(2/4)
If the first-time placement is not what you
prefer to be, you can use the “Incremental”
option to re-allocate the location of macros
based on the current placement
With few times of incremental placement,
the placement will be fix.

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Plan Design(3/4)
Tips for macro placement
Place macros around chip periphery
Consider connections to fixed cells
Orient macros to minimize distance between pins
Reserve space for power grid and signal routing and possible buffer insertion
Keep edges pf macros aligned if possible

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Plan Design(4/4)
Floorplan -> Floorplan Toolbox • All kinds of tools
• Shift
• Spacing
• Alignment
• Rotation

Click the icon in Toolbox

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Add Halo
1. Blockage is used to avoid unwanted wire in certain area
Halo is the blockage for blocks such as memory
Two types of Halo
Placement Halo
Prevent the placement of blocks and standard cells in order to reduce the
congestion around blocks
Routing Halo
Reduce the possibility of long wire routing closed to the blocks
Long wire has higher cost and has DRC violations if too close to the
blocks.

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Add Placement Halo (1/2)

1.

2.

4.

5.

3.

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Add Placement Halo (1/2)

Click redraw icon

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Add Routing Halo (1/2)

1.

4.

2.

5.

3.

6.

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Add Routing Halo (2/2)

Click redraw icon

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Powerplan
Place the power wires for all kinds of cells/blocks

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Power wire
There are many types of power wire for different objectives.
Core Ring
Power ring supply power from IO Pad for the core
Block Ring
Power ring supply power from Core ring for the block
Block Pins
Connect the block ring to the core ring
Power Stripe
Additional power wires (same metal as ring) to reduce the IR drop
Follow Pins
The power wires for standard cells

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Create Core Ring(1/2)

1.
4.

2. 5.
3.

7. 6.

8.
3 layers of VCC/GND
and interleaving

9.
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Create Core Ring(2/2)

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Create Block Ring (1/2)

2.
9.

5.
3.
4.
6.
7.

8.

1.

Select the block

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Create Block Ring (2/2)

10.

The location of Ring side should

consider the location of blocks

The block is surrounded by the

power ring(Core/Block ring)

11.
Repeat step 1~11 for all blocks

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Connect Block Pins (1/2)

1.

3.
2. 4.

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Connect Block Pins (2/2)

5.

6.

7.

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Create Power Stripe (1/3)

1.
9.

4.
2. 3. 5.
6.
7.

8.

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Create Power Stripe (2/3)

12.

10.

11.

13.

14.

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Create Power Stripe (3/3)

Repeat Step 5. -> 14.

• First: metal 4 / Vertical
• Second: metal 5 / Horizontal

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Connect Follow Pins (1/2)

1.
5.

3.
2. 4.

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Connect Follow Pins (2/2)

6.

7.

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Verify DRC
1.

2.

3.

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Verify Connectivity
1.

2.
3.

4.

5.

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Placement
Place the standard cell

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Place Standard Cells

Placement + pre-CTS Optimization

Check timing report

If worst negative slacks (WNS) < 0, you need to optimize design

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Optimize Design (Optional)

1.

2. 3.

4.
5.

If worst negative slacks (WNS) < 0,

you need to optimize design
6.

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Clock Tree Synthesis

Create the clock tree which is the most important in the design

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CCOpt
Clock Concurrent Optimization
Create the clock tree and optimize the design at the same time

Two steps
CCOpt design
Setup & hold time optimization

ERROR IMPCCOPT-5054 can be ignored

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Report Timing - Setup

1.

3.
2.

4.

5.
If worst negative slacks (WNS) < 0, you need to optimize design

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Optimize Design – Setup (Optional)

1.

2. 3.

4.
5.

If worst negative slacks (WNS) < 0,

you need to optimize design
6.

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Report Timing - Hold

1.

3.
2.

4.

5.
If worst negative slacks (WNS) < 0, you need to optimize design

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Optimize Design – Hold (Optional)

1.

2. 3.

4.
5.

6.

If worst negative slacks (WNS) < 0, you need to optimize design

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Add Tie Hi/Lo Cells

1.

4.

5.
2.

3.
Tiehi/Tielo cell connect tiehi/tielo net to supply voltage or ground with resister
Tiehi/Tielo cell is added for ESD protection

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Routing
Adding wires to connect the whole design

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Route
1.

4.
2.
5.
6.
3.

• Optimize Via
• Add via for yield issue
• Optimize Wire
• Some wires can use
same metal in different
direction
• Antenna
• Fix antenna effect
• SI Driven
• Prevent signal integrity 7.

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Specify Analysis Mode

1.

2.

4.
3.
5.

7.

6.
CPPR: Clock Path Pessimism Removal

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Report Timing (Setup)

1.

3.
2.

4.

5.
If worst negative slacks (WNS) < 0,
you need to optimize design

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Optimize Design (Setup)

1.

2. 3.

4.
5.

If worst negative slacks (WNS) < 0,

you need to optimize design 6.
7.

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Report Timing (Hold)

1.

3.
2.

4.

5.
If worst negative slacks (WNS) < 0,
you need to optimize design

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Optimize Design (Hold)

1.

2. 3.

4.
5.

If worst negative slacks (WNS) < 0,

you need to optimize design 6.
7.

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Add Core Filler

1.

4.

5.

2. 8. 6.

3.

7.
• Fill the empty space of the layout
• Connect the NWELL/PWELL layer in core rows

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DRC / LVS / Antenna

Check the design

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Verify DRC
• Design Rule Check
• Check if the layout violate the foundry
constraint or not.
• Including
• Minimum Width
• Minimum Spacing
• Short
• and other characteristics
1.

2. 3.

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Verify Connectivity (LVS)

• Layout versus Schematic
• Check if the layout is same as the netlist
3.

1.
4.

2.
5.

6.

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Verify Process Antenna

• Process Antenna
• Check if the layout has antenna effect or not

1.

2.

3.

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Check violations

• Make sure at least

the LVS has no error
• Affect the
functionality of
the circuit
• Other violations can
use the Violation
Browser to check.
• Or double click
the cross icon
in physical view.

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Floorplan View
• The location of hard macro
• The layout of power wiress

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Amoeba View
• The distribution of soft modules
• Soft module
• Composed by standard
cells
• For example, CPU is the
soft module in our design.

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Physical View
• All the wires and modules
• Hard macro – Memory
• Soft module – standard cells
• Metal
• Via

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Save / Export Files

Saving the netlist, SDF file and the GDS file

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Save Netlist
1.

4.
5.

2.

3.

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Save SDF File

1.

3.

4.
5.
2.

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Save GDS File

1.

4.
5.

6.
2. 7.

8.

3. Or use: (This one is better!!!)

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Save Design
1.

3.
4.
2.

5.

• You can save the design after each stage in case of

the Innovus suddenly break down.
• Remember to change the saving directory in case
that you make clean to remove the build directory.

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Restore Design
• Restoring the previous
1. stage if the current stage
2. 3. has some problem.

4.

7.

6.
5.

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Area

• After analyzeFloorplan command, the layout will be destroyed, so remember saving

the design before using this command.

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Power(1/2)
★ Step 1 ★ Step 3

Modify the frequency

for your design

★ Step 2 ★ Step 4

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Power(2/2)

mW

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 VLSI System Design (Graduate Level) Fall 2022

Reference
CIC Training Manual – Cell-Based IC Physical Design and
Verification with Innovus, January 2021
Training Course of SoC Encounter
(http://www.ee.ncu.edu.tw/~jfli/vlsidi/lecture/soc)
Cell-Based IC Physical Design and Verification - SoC Encounter
(http://mspic.ee.nchu.edu.tw/class_course/university/97_VLSI-
design/handout/4-1.Soc_Encounter.pdf)
Cadence Help

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Thanks for your participation

and attendance ! !

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