AN6115

Application note

STPMIC25 application hints

1. How to connect unused PINs

In some STPMIC25 + STM32MP25x lines MPU applications, not all the peripherals and functions may be required, and to
minimize any possible issues and useless power consumption, the relative pins must be connected correctly.
The following tables provide guidance on how to connect unused pins of the STPMIC25, and they are valid for all pins except
VIN, VIO, and all GNDs.
Note 1: To avoid any damage to the STPMIC25, the VIN must be the first and the highest input supply. VBUS input voltage can
be applied before the VIN.
Note 2: The DC-DC converter input pins (pins #20, #24, #25, #38, #39, #49, and #50) cannot be separated from the main input
pin (pin #11).

Figure 1. Pin configuration WFQFN 56L top view

AN6115 - Rev 2 - November 2024 www.st.com

For further information contact your local STMicroelectronics sales office.
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Table 1 shows the possible configuration of the STPMIC25 input/output digital pins if they are not used in the final application:

Table 1. STPMIC25 digital pin configuration

Pin number Pin name Type If not used

1 PONKEYn I Floating
30 WAKEUPn I Floating
31 RSTn I/O Floating
32 INTn O Floating
33 SCL I VIO
34 SDA I/O VIO
54 PWRCTRL3 I Floating
55 PWRCTRL2 I Floating
56 PWRCTRL1 I Floating

Table 1 shows the possible configuration of the STPMIC25 input/output analog pins if they are not used in the final application:

Table 2. STPMIC25 power analog I/O pin configuration

Pin number Pin name Type If not used

2 LDO8OUT O Floating
3 LDO78IN I VIN
4 LDO7OUT O Floating
5 LDO6OUT O Floating
6 LDO56IN I VIN
7 LDO5OUT O Floating
12 VBUS I Floating
13 LDO4OUT O Floating
14 LDO1OUT O Floating
15 LDO12IN I VIN
16 LDO2OUT O Floating
17 VOUT4 I Floating
19 VLX4 O Floating
20 BUCK4IN I VIN
21 VOUT3 I Floating
23 VLX3 O Floating
24 BUCK3IN I VIN
25 BUCK2IN I VIN
26 VLX2 O Floating
28 VOUT2 I Floating
35 VOUT5 I Floating
37 VLX5 O Floating
38 BUCK5IN I VIN
39 BUCK1IN I VIN

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Pin number Pin name Type If not used

40 VLX1 O Floating
42 VOUT1 I Floating
43 LDO3IN I VIN
44 LDO3OUT O Floating
45 VREFDDR O Floating
46 VOUT6 I Floating
48 VLX6 O Floating
49 BUCK6IN I VIN
50 BUCK7IN I VIN
51 VLX7 O Floating
53 VOUT7 I Floating

If the passive components (inductors, capacitors) of the unused LDOs and BUCK converters are not mounted (for cost
constraints, to reduce the occupied area around the STPMIC25, etc.), it is mandatory to disable these IPs, setting their
respective ranks to 0 in the NVM memory of STPMIC25. This avoids the risk of any possible oscillation or other saturation of the
internal circuitry, and at each power ON cycle the unused IPs are not automatically turned ON.

2. STPMIC25 default NVM content shadow register map

Below table shows the default NVM content shadow register map of STPMIC25A, STPMIC25B and STPMIC25D versions.

Table 3. STPMIC25 NVM shadow register map

STPMIC25A/B/D default NVM shadow register map

Reg R/
Register Name BITS[7:0]
(Hex) W (1) Hex
7 6 5 4 3 2 1 0

NVM_WD AUTO_TU
VINOK_HYST[1:0] VINOK_RISE[1:0] NVM_WDG_TMR_SET[ 1:0]
G_EN RNON
A:
1 1 1 1 0 0 0 1
NVM_MAIN_CTRL_ R/ 0xF1
0x90
SHR1 W B:
1 1 0 1 0 0 0 1
0xD1
D:
1 1 1 1 0 0 0 1
0xF1
NVM_PKEY_LKP_CON NVM_PKEY_LKP_TM
RANK_DLY[1:0] RST_DLY[1:0]
FIG[1:0] R[1:0
A:
0 0 0 0 1 0 1 0
NVM_MAIN_CTRL_ R/ 0x0A
0x91
SHR2 W B:
0 0 0 0 1 0 1 0
0x0A
D:
0 0 0 0 1 0 1 0
0x0A
- - BUCK2_RANK[2:0] BUCK1_RANK[2:0]
NVM_RANK_CTRL_ R/
0x92 A:
SHR1 W 0 0 0 1 0 0 1 1
0x13

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 AN6115

STPMIC25A/B/D default NVM shadow register map

Reg R/
Register Name BITS[7:0]
(Hex) W (1) Hex
7 6 5 4 3 2 1 0

B:
0 0 0 1 0 0 1 1
NVM_RANK_CTRL_ R/ 0x13
0x92
SHR1 W
D:
0 0 0 1 0 0 1 1
0x13
- - BUCK3_RANK[2:0] BUCK3_RANK[2:0]
A:
0 0 0 0 1 0 0 0
0x08
NVM_RANK_CTRL_ R/
0x93 B:
SHR2 W 0 0 0 0 1 0 0 0
0x08
D:
0 0 0 0 1 0 0 0
0x08
- - BUCK6_RANK[2:0] BUCK5_RANK[2:0]
A:
0 0 0 0 0 0 1 1
0x03
NVM_RANK_CTRL_ R/
0x94 B:
SHR3 W 0 0 0 0 0 0 1 1
0x03
D:
0 0 0 0 0 0 1 1
0x03
- - REFDDR_RANK[2:0] BUCK7_RANK[2:0]
A:
0 0 0 0 0 1 0 0
0x04
NVM_RANK_CTRL_ R/
0x95 B:
SHR4 W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 1 0 0
0x04
- - LDO2_RANK[2:0] LDO1_RANK[2:0]
A:
0 0 1 0 0 0 0 1
0x21
NVM_RANK_CTRL_ R/
0x96 B:
SHR5 W 0 0 1 0 0 0 0 1
0x21
D:
0 0 1 0 0 0 0 1
0x21
- - LDO4_RANK[2:0] LDO3_RANK[2:0]
A:
0 0 1 0 1 0 0 0
0x28
NVM_RANK_CTRL_ R/
0x97 B:
SHR6 W 0 0 1 0 1 0 0 0
0x28
D:
0 0 1 0 1 0 0 0
0x28
- - LDO6_RANK[2:0] LDO5_RANK[2:0]
A:
0 0 0 0 0 0 0 0
0x00
NVM_RANK_CTRL_ R/
0x98 B:
SHR7 W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00

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STPMIC25A/B/D default NVM shadow register map

Reg R/
Register Name BITS[7:0]
(Hex) W (1) Hex
7 6 5 4 3 2 1 0

- - LDO8_RANK[2:0] LDO7_RANK[2:0]
A:
0 0 0 0 0 0 0 0
0x00
NVM_RANK_CTRL_ R/
0x99 B:
SHR8 W 0 0 0 0 0 0 0 0
0x00
D:
0 0 1 0 0 1 0 0
0x24
BUCK4_PREG_MODE[ 1:0] BUCK3_PREG_MODE[ 1:0] BUCK2_PREG_MODE[ 1:0] BUCK1_PREG_MODE[ 1:0]
A:
0 0 0 0 0 0 0 0
0x00
NVM_BUCK_MODE R/
0x9A B:
_SHR1 W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00
- - BUCK7_PREG_MODE[ 1:0] BUCK6_PREG_MODE[ 1:0] BUCK5_PREG_MODE[ 1:0]
A:
0 0 0 0 0 0 0 0
0x00
NVM_BUCK_MODE R/
0x9B B:
_SHR2 W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00
- NVM_VOUT[6:0]
A:
0 0 0 1 1 1 1 0
0x1E
NVM_BUCK1_VOUT R/
0x9C B:
_SHR W 0 0 0 1 1 1 1 0
0x1E
D:
0 0 0 1 1 1 1 0
0x1E
- NVM_VOUT[6:0]
A:
0 0 1 0 0 0 0 0
0x20
NVM_BUCK2_VOUT R/
0x9D B:
_SHR W 0 0 1 0 0 0 0 0
0x20
D:
0 0 1 0 0 0 0 0
0x20
- NVM_VOUT[6:0]
A:
0 0 0 0 0 0 0 0
0x00
NVM_BUCK3_VOUT R/
0x9E B:
_SHR W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00
- NVM_VOUT[6:0]
A:
NVM_BUCK4_VOUT R/ 0 1 1 1 0 1 1 0
0x9F 0x76
_SHR W
B:
0 1 1 0 0 1 1 1
0x67

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 AN6115

STPMIC25A/B/D default NVM shadow register map

Reg R/
Register Name BITS[7:0]
(Hex) W (1) Hex
7 6 5 4 3 2 1 0
NVM_BUCK4_VOUT R/ D:
0x9F 0 1 1 1 0 1 1 0
_SHR W 0x76
- NVM_VOUT[6:0]
A:
0 1 1 0 0 1 1 1
0x67
NVM_BUCK5_VOUT R/
0xA0 B:
_SHR W 0 1 1 0 0 1 1 1
0x67
D:
0 1 1 0 0 1 1 1
0x67
- NVM_VOUT[6:0]
A:
0 0 0 0 0 0 0 0
0x00
NVM_BUCK6_VOUT R/
0xA1 B:
_SHR W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00
- NVM_VOUT[6:0]
A:
0 1 1 1 0 1 1 0
0x76
NVM_BUCK7_VOUT R/
0xA2 B:
_SHR W 0 0 0 0 0 0 0 0
0x00
D:
0 1 1 1 0 1 1 0
0x76
NVM_BYP
- NVM_VOUT[4:0] -
ASS
A:
0 0 1 1 0 0 0 0
R/ 0x30
0xA3 NVM_LDO2_SHR
W B:
0 0 1 0 1 0 0 0
0x28
D:
0 0 1 1 0 0 0 0
0x30
NVM_BYP
SNK-SRC NVM_VOUT[4:0] -
ASS
A:
0 0 0 0 0 0 0 0
R/ 0x00
0xA4 NVM_LDO3_SHR
W B:
0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00
NVM_BYP
- NVM_VOUT[4:0] -
ASS
A:
0 0 0 0 0 0 0 0
R/ 0x00
0xA5 NVM_LDO5_SHR
W B:
0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00

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 AN6115

STPMIC25A/B/D default NVM shadow register map

Reg R/
Register Name BITS[7:0]
(Hex) W (1) Hex
7 6 5 4 3 2 1 0

NVM_BYP
- NVM_VOUT[4:0] -
ASS
A:
0 0 0 0 0 0 0 0
R/ 0x00
0xA6 NVM_LDO6_SHR
W B:
0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00
NVM_BYP
- NVM_VOUT[4:0] -
ASS
R/ A:0x00 0 0 0 0 0 0 0 0
0xA7 NVM_LDO7_SHR
W
B:0x00 0 0 0 0 0 0 0 0
D:0x40 0 1 0 0 0 0 0 0
NVM_BYP
- NVM_VOUT[4:0] -
ASS
A:
0 0 0 0 0 0 0 0
R/ 0x00
0xA8 NVM_LDO8_SHR
W B:
0 0 0 0 0 0 0 0
0x00
D:
0 1 0 0 0 0 0 0
0x40
NVM_BUCK4_PD[1:0] NVM_BUCK3_PD[1:0] NVM_BUCK2_PD[1:0] NVM_BUCK1_PD[1:0]
A:
0 1 0 1 0 1 0 1
0x55
R/
0xA9 NVM_PD_SHR1 B:
W 0 1 0 1 0 1 0 1
0x55
D:
0 1 0 1 0 1 0 1
0x55
NVM_REF
- NVM_BUCK7_PD[1:0] NVM_BUCK6_PD[1:0] NVM_BUCK5_PD[1:0]
DDR_PD
A:
1 0 0 1 1 0 0 1
R/ 0x99
0xAA NVM_PD_SHR2
W B:
1 0 0 1 1 0 0 1
0x99
D:
1 0 0 1 1 0 0 1
0x99
NVM_LDO NVM_LDO7_ NVM_LDO6 NVM_LDO5 NVM_LDO4 NVM_LDO3 NVM_LDO2 NVM_LDO1_
8_PD PD _PD _PD _PD _PD _PD PD
A:
1 1 1 1 1 1 1 1
R/ 0xFF
0xAB NVM_PD_SHR3
W B:
1 1 1 1 1 1 1 1
0xFF
D:
1 1 1 1 1 1 1 1
0xFF
BUCK4_ILIM[1:0] BUCK3_ILIM[1:0] BUCK2_ILIM[1:0] BUCK1_ILIM[1:0]
NVM_BUCKS_IOUT R/
0xAC A:
_SHR1 W 1 0 1 1 1 1 0 1
0xBD

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 AN6115

STPMIC25A/B/D default NVM shadow register map

Reg R/
Register Name BITS[7:0]
(Hex) W (1) Hex
7 6 5 4 3 2 1 0

B:
0 1 1 1 1 1 0 1
NVM_BUCKS_IOUT R/ 0x7D
0xAC
_SHR1 W
D:
1 0 1 1 1 1 0 1
0xBD
HICCUP_DLY[1:0] BUCK7_ILIM[1:0] BUCK6_ILIM[1:0] BUCK5_ILIM[1:0]
A:
0 1 1 1 1 0 0 1
0x79
NVM_BUCKS_IOUT R/
0xAD B:
_SHR2 W 0 1 1 1 1 0 0 1
0x79
D:
0 1 1 1 1 0 0 1
0x79
LDO7_ILIM[1:0] LDO6_ILIM[1:0] LDO5_ILIM[1:0] LDO2_ILIM[1:0]
A:
1 1 1 1 1 1 1 1
0xFF
NVM_LDOS_IOUT R/
0xAE B:
_SHR1 W 1 1 1 1 1 1 1 1
0xFF
D:
1 1 1 1 1 1 1 1
0xFF
NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_
NVM_FS_
OCP_REF OCP_BUC OCP_BUC OCP_BUC OCP_BUC OCP_BUC OCP_BUC
OCP_BUC K7
DDR K6 K5 K4 K3 K2 K1
A:
NVM_FS_OCP_SHR R/ 0 0 0 1 1 0 1 1
0xAF 0x1B
1 W
B:
0 0 0 1 1 0 1 1
0x1B
D:
0 0 0 1 1 0 1 1
0x1B
NVM_FS_
NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_ NVM_FS_
OCP_LDO
OCP_LDO7 OCP_LDO6 OCP_LDO5 OCP_LDO4 OCP_LDO3 OCP_LDO2 OCP_LDO1
8
A:
NVM_FS_OCP_SHR R/ 0 0 0 0 0 0 0 1
0xB0 0x01
2 W
B:
0 0 0 0 0 0 0 1
0x01
D:
0 0 0 0 0 0 0 1
0x01
VIN_FLT_CNT_MAX[3:0] PKEY_FLT_CNT_MAX[3:0]
A:
1 1 1 1 1 1 1 1
0xFF
R/
0xB1 NVM_FS_SHR1 B:
W 1 1 1 1 1 1 1 1
0xFF
D:
1 1 1 1 1 1 1 1
0xFF
TSHDN_FLT_CNT_MAX[3:0] OCP_FLT_CNT_MAX[3:0]
R/
0xB2 NVM_FS_SHR2 A:
W 1 1 1 1 1 1 1 1
0xFF

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 AN6115

STPMIC25A/B/D default NVM shadow register map

Reg R/
Register Name BITS[7:0]
(Hex) W (1) Hex
7 6 5 4 3 2 1 0

B:
1 1 1 1 1 1 1 1
R/ 0xFF
0xB2 NVM_FS_SHR2
W
D:
1 1 1 1 1 1 1 1
0xFF
FS_L
- OCK RST_FLT_CNT_TMR[1:0] WDG_FLT_CNT_MAX[3:0]
_DIS
A:
R/ 0 1 1 1 1 1 1 1
0xB3 NVM_FS_SHR3 0x7F
W
B:
0 1 1 1 1 1 1 1
0x7F
D:
0 1 1 1 1 1 1 1
0x7F
LOCK_NVM I2C_ADDR[6:0]
A:
0 0 1 1 0 0 1 1
0x33
NVM_I²C_ADDR_SH R/
0xB5 B:
R W 0 0 1 1 0 0 1 1
0x33
D:
0 0 1 1 0 0 1 1
0x33
NVM_USER1[7:0]
A:
0 0 0 0 0 0 0 0
0x00
R/
0xB6 NVM_USER_SHR1 B:
W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00
NVM_USER2[7:0]
A:
0 0 0 0 0 0 0 0
0x00
R/
0xB7 NVM_USER_SHR2 B:
W 0 0 0 0 0 0 0 0
0x00
D:
0 0 0 0 0 0 0 0
0x00

1. This column contains the STPMIC25 default values of NVM content shadow register for STPMIC25A/B/D versions in hexadecimal format.

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Revision history
Table 4. Document revision history

Date Version Changes

14-May-2024 1 Initial release.

07-Nov-2024 2 Added new Section 2. STPMIC25 default NVM content shadow register map .

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 AN6115
Contents

Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

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List of figures

List of figures
Figure 1. Pin configuration WFQFN 56L top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

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 AN6115

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