MD BIHAR STATE EXAM 2024

LOGIC GATE MCQ

1. Fathers of digital logic
a) George Boole
b) Claude Elwood Shannon (digital signal)
c) Michael Fraday (Digital electronics)
d) Dr. Vannevar Bush (Analog)

2. The smallest integer that can be represented by an 8-bit number

in 2’s complement form is
a) -127
b) -128
c) -256
d) -64

3. The range of integers that can be represented by an n bit 2’s

complement number system is?
a) –2(n-1) +2(n-1)-1
b) –2(n-1) -2(n-1)-2
c) –2(n-1) +2n(n-1)-2
d) –2(n-1) -2(n-1)-1

4. The 2’s complement representation of (-539)10 In Hexadecimal is

a) ABE
b) DE5
c) DBC
d) 9E7
5. In 16-bit 2’s complement representation, the decimal number -
28 is:
a) 1111 1111 0001 1100
b) 1111 1111 1110 0100
c) 1000 0000 1110 0100
d) 0000 0000 1110 0100

6. The code used to reduce the error due to ambiguity in reading of

a binary optical encoder is-
a) Octal code
b) Excess-3 code
c) Gray code
d) BCD code

7. In the -------- encoding, scheme each 24 bits become four 6 bit

chunks, and eventually are sent as 32 bits.
a) Base 64
b) Binary
c) Bit
d) None of the above

8. ASCII code is required for representing more than ------

characters.
a) 16
b) 8
c) 64
d) 32
9. The output of an AND gate with three inputs, A, B and C is High
when.
a) A=1, B=1, C=0
b) A=0, B=0, C=0
c) A=1, B=1, C=1
d) A=1, B=0, C=1

10. The output of an OR gate with three inputs A, B, C is low

when.
a) A=1, B=1, C=0
b) A=0, B=0, C=0
c) A=1, B=1, C=1
d) A=1, B=0, C=1

11. The output of NOR gate is High if---

a) All inputs are High
b) Any input is High
c) Any input is Low
d) All inputs are Low

12. EXOR is the ------ of the binary number

a) MSB to the next bit
b) LSB to the next bit
c) MSB of the previous bit
d) LSB of the previous bit

13. Which of the following is not correct regarding EBCDIC?

a) It is used to represent more than 64 characters.
b) It is a 7-bit code
c) A maximum of 128 different characters can be represented
by this code.
d) None of the above
14. In N-bits you can represent the signed integers ranging from---
a) 2^(n-1) to 2^(n+1)
b) -2^(n-1) to 2^(n-1)-1
c) 2^(n+1) to 2^(n-1)+1
d) 2^(n) to 2^(n+1)

15. How many get (S) would be required to implement the

Following Boolean Expression after simplification?
Expression: AC + ABC
a) 1
b) 2
c) 4
d) 5

16. How many entries would a truth table for a four input NAND
gate have?
a) 2
b) 8
c) 16
d) 32

17. Boolean expression for three input AND gate is:-

a) A.B.C=D
b) A+B+C=D
c) 3A.B.C=D
d) A.B+C=D

18. The addition of these binary numbers 101001 + 010011 would

generate
a) 101110
b) 111100
c) 000111
d) 010100
19. The Substraction of these binary numbers 101001 – 010110
would generate:-
a) 010010
b) 010011
c) 011001
d) 100110

20. The Min term Expression of f(P,Q,R)= PQ+QR-+PR- is:-

a) M0 + m1 + m3 + m4
b) M0 + m1 + m6 + m7
c) M2 + m4 + m6 + m7
d) M0 + m1 + m3 + m4

21. In a DRAM(Dynamic RAM)

a) Information is stored in a latch
b) Information stored in a capacitor
c) Periodic refreshing is not required
d) Both READ and WRITE operations can be performed
simultaneously

22. A 10 bit unsigned integer has the following range:

a) 0 to 1000
b) 0 to 1024
c) 1 to 1025
d) 0 to 1023
23. Consider the following statements regarding PROM/EPROM
I) The erasable programmable ROM using ultra violet
erasing is known as EPROM.
II) The ROM that makes use of the electrical voltage for
erasing is known as electrically alterable ROM.
III) A PROM can programmed many times after fabrication.
Which of the above statements are correct?
a) 1 and 2
b) 1 and 3
c) 1, 2 and 3
d) 2 and 3

24. What are the basic gates in MOS logic family

a) NAND and NOR
b) AND and OR
c) NAND and OR
d) AND and NOR

25. How many 4 bit parallel binary adders will be required to

construct a 4 bit parallel multiplier?
a) 1
b) 2
c) 4
d) 3

26. In IEEE 32-bit representations the mantissa of the fraction is

said to occupy------ bits.
a) 24
b) 23
c) 20
d) 16
27. Of the logic families mentioned below, the one which
consumes the least power is
a) Low power TTL
b) Low power Schottky TTL
c) CMOS (low power consumption)
d) ECL (high power consumption)

28. TTL stands for

a) Transistor-Transistor Logic
b) Transistor Thermocouple Logic
c) Transistor Thermostat logic
d) Transistor thermistor logic

29. How many gate(s) would be required to implement the

following Boolean expression after simplification?
Expression:- AC+ABC
a) 1 (AND gate)
b) 2 (AND gate)
c) 3 (AND gate)
d) 4 (AND gate)
30. Arrange the following logic families in the order of increasing
speed:-
CMOS, low power Schottky TTL, ECL, Schottky TTL,
Low power TTL, TTL.
a) CMOS, low power TTL, TTL, Low power Schottky TTL,
Schottky TTL and ECL.
b) ECL Schottky TTL, low power Schottky TTL, TTL, low power
TTL and CMOS.
c) TTL,ECL Schottky TTL, low power Schottky TTL, low power
TTL and CMOS.
d) ECL Schottky TTL, low power Schottky TTL,low power TTL
and CMOS, TTL.

31. Convert hexadecimal value 16 to decimal

a) 22
b) 16
c) 10
d) 20

32. Convert the following decimal number to 8- bit binary(187)

a) 10111011
b) 11011101
c) 10111101
d) 10111100

33. Convert the binary number 1001.00102 to decimal.

a) 90.125
b) 9.125
c) 125
d) 12.5
34. Which of the following is the most widely used alphanumeric
code for computer input and output.
a) GRAY
b) ASCII
c) BCD
d) EBCDIC

35. Convert (59.72)10 to BCD.

a) 111011
b) 01011001.01110010
c) 1110.11
d) 0101100101110010

36. Assign the proper odd parity bit to the code 111001.
a) 1111011
b) 1111001
c) 0111111
d) 0011111

37. What is the octal equivalent of the hexadecimal number

132A.
a) (11452)8
b) (10452)8
c) (10145)8
d) (11405)8

38. The output from a NAND gate is divided into two in parallel
and fed to another NAND gate. The resulting gate is a.
a) AND GATE
b) NOR GATE
c) OR GATE
d) NOT GATE
39. The expression for Absorption law is given by.
a) A+AB=A
b) A+AB=B
c) AB+AA’=A
d) A+B=B+A

40. De Morgan’s theorem states that.

a) (AB)’=A’+B’
b) (A+B)’=A’*B
c) A’+B’=A’B’
d) (AB)’=A’+B

41. The basic building block of sequential logic circuit is-

a) OR gate
b) NAND gate
c) Flip Flop
d) AND gate

42. Minimize the following Boolean function-

F(A,B,C,D)= sum M(0,1,3,5,7,8,9,11,13,15)
a) D+B’C’
b) A+BC
c) C+AB’
d) D+BC

43. Which of the following represents the binary equivalent of the

hexadecimal number “A3”
a) 10100011
b) 11000010
c) 1111001
d) 10100001
44. The number of bits required to represent decimal number
4096 in binary form is---
a) 10
b) 13
c) 12
d) 16

45. Binary numbers need more places for counting because:

a) They are always big numbers
b) Any no of 0’s can be added in front of them
c) Binary base is small
d) 0’s and 1’s have to be properly spaced apart

46. A 24 bit word consist of---

a) 4 bytes
b) 8 bytes
c) 10 bytes
d) 12 bytes

47. How many 2k*8 ROM chips would be required to build a

16k*8 memory system?
a) 2
b) 4
c) 8
d) 16

48. The simplified SOP form of the expression F= sop

M(1,5,6,12,13,14) +d(2,4) is
a) F =BC’+BD’+A’C’D
b) F=BC’+ABD’+A’C’D
c) F= BC’D+BD’_A’C
d) F=ABC’+BD’+C’D
49. Simplify the SOP form and obtain the result in SOP only.
F(A,B,C,D)= A’BC’D’ + A’BC’D + A’BCD + AB’C’D’ + AB’C’D +ABC’D’
+ ABCD’
a) BC’D’ + A’BD +AB’C’ +ABD’
b) ABC +ACD + ACB’ + CDA’
c) None of the above

50. Binary equivalent of (CA5)16 is

a) 110010100101
b) 100010010011
c) 1111001101100
d) 1010101010101

51. Which Boolean law is represented below?

A+A=A
a) Associative law
b) Commutative law
c) Idempotent law
d) Dominant law

52. In which logic gate, the output is complement of the input?

a) NOT (also called inverter gate)
b) AND
c) OR
d) XOR

53. Which of the following is not a combinational circuit?

a) Adder
b) Sub tractor
c) Multiplexer
d) Counter
54. Cartesian product in relational algebra
a) Unary operator
b) Binary operator
c) Ternary operator
d) None of these

55. The Octal equivalent of hexadecimal (D.C) 16 is

a) (15.3)8
b) (15.6)8
c) (61.3)8
d) (61.6)8

56. Given Ethernet address 01011010 00010001 01010101

00011000 10101010 00001111 in binary, what is the address in
hexadecimal notation?
a) 5A : 88 : AA : 18 : 55: F0
b) 5A : 81 : BA : 81 : AA : 08
c) 5A : 18 : 5A : 18 : 55 : 0F
d) 5A : 11 : 55 : 18 : AA : 0F

57. A switching circuit whose output depends not only on the

present state of its input but also on its previous state is called
a) Combinational circuit
b) Sequential circuit
c) Multiplexer
d) Counter

58. SR flip flop can be converted to T type flip flop if

a) S is connected to Q
b) R is connected to Q
c) Both S and R- are shortened
d) S and R are connected to Q and Q respectively
59. In modern digital computer a sub tractors is normally not used
because
a) Sub tractors are very expensive
b) The design of a sub tractors is very complex
c) The adder geared for doing subtraction also
d) Most of the programs do not require subtraction

60. The logic circuit of binary adder which is used to add two 4-
bits binary numbers requires …… half adder (s) and ………… full
adder(s)
a) 4,0
b) 1,3
c) 2,2
d) 3,1

61. The maximum number of outputs for a decoder with 6 bit

word would be
a) 64
b) 6
c) 24
d) 256

62. A logic circuit which is used to change a BCD number into an

equivalent decimal number is
a) Decoder
b) Encoder
c) Multiplexer
d) Code converter
63. Which of the following combinational circuit converts binary
information of n input lines to a maximum of 2n unique output
lines
a) Encoder
b) Multiplexer
c) Decoder
d) De multiplexer

64. The number of bits require to represent decimal number 4096

in binary form is
a) 16
b) 10
c) 12
d) 13

65. A combinational circuit which is used to send data coming

from a single source to two or more separate destinations is
called as
a) Decoder
b) Multiplexer
c) End coder
d) De multiplexer

66. An RS latch is
a) Combinational circuit
b) Synchronous sequential circuit
c) One bit memory element
d) One clock delay element
67. A master slave flip flop has the characteristic that
a) Change in the input immediately reflected in output
b) Change in the output occurs when the state of the slave is
affected
c) Change in the output occurs when the state of master is
affected
d) Both the master and the slaves states are affected at same time

68. A full adder logic circuit will have

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two output

69. A half adder logic circuit will have

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two output

70. Advantage of synchronous sequential circuits over

asynchronous ones is
a) Faster operation
b) Lower hardware requirement
c) Case of avoiding problems due to hazards
d) Better noise immunity

71. This difference in the address and data connection b/w

DRAM’s and SDRAM’s is……
a) The requirement of more address lines in SDRAM’s
b) The usage of a buffer in SDRAM’s
c) The usage of more number of pins in SDRAM’s
d) None of the mention
72. In full adders the sum circuit is implemented using
a) AND OR GATE
b) NAND GATE
c) XOR
d) XNOR

73. The addition sum of the numbers 0110 & 0110 is…
a) 1101
b) 1111
c) 1001
d) 1100

74. Circuits that can hold their state as long as power is applied is
a) Dynamic memory
b) Static memory
c) Registers
d) Hard disk
e) a & b

75. Fastest data access is provided using….

a) Caches
b) DRAM’s
c) SRAM’s
d) Registers

76. De Morgan’s theorem states that

a) (AB)’=A’+B’
b) (A+B)’=A’*B
c) A’+B’=A’B’
d) (AB)’=A’B’
77. Convert the binary number (01011.1011)2 into decimal
a) (11.6875)10
b) (11.5874)10
c) (10.9876)10
d) (10.5475)10

78. (A U B) U C =AU (B U C) this is

a) Idempotent laws
b) Associative laws
c) Commutative laws
d) Distributive laws

79. A ^ (B U C ) = ( A^ B) U (A ^C ) this is
a) Idempotent laws
b) Associative laws
c) Commutative laws
d) Distributive laws

80. Which of the following equations would accurately describe a

four input OR gate when A= 1, B=1, C=0 and D=0
a) 1+1+0+0=01
b) 1+1+0+0=1
c) 1+1+0+0=0
d) 1+1+0+0=00

81. From the truth table for a three input NOR gate, what is the
only condition of inputs A, B and C that will make the output X
high?
a) A=1,B=1,C=1
b) A=1,B=0,C=0
c) A=0,B=0,C=1
d) A=0,B=0,C=0
82. Which of the following describes the operation of a positive
edge triggered D flip flop?
a) If both inputs are high the output will toggle
b) The output will follow the input on the leading edge of the
clock
c) When both inputs are low an invalid state exists.
d) The input is toggled into the flip flop on the leading edge of the
clock and is passed to the output on the trailing edge of the
clock.

83. The D flip flop has…. Input

a) 1
b) 2
c) 3
d) 4

84. The D flip flop has……. Output

a) 1
b) 2
c) 3
d) 4

85. If both inputs of as SR flip flop are Low what will happen
When the clock goes high?
a) No change will occur in the output
b) An invalid state will exist
c) The output will toggle.
d) The output will reset
86. Which of the following is an important feature of the sum of
products SOP form of expression?
a) All logic circuits are reduced to nothing more than simple AND
& OR gates
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not
including inverters
d) The maximum number of gates that any signal use pass though
is reduced by a factor of two

87. Parity systems are defined as either ……. Or ……. And will add
an extra …. To the digital information being transmitted.
a) Positive, negative, byte
b) Odd, even, bit
c) Upper, lower, digit
d) On, off, decimal

88. Determine odd parity for each of the flowing data words?
1011101 11110111 10001101
a) P=1, p=1, p=0
b) P=0, p=0, p=0
c) P=1, p=1, p=1
d) P=0, p=0, p=1

89. The 2’s complement system is to be used to add the signed

binary numbers 11110010 and 11110011 determine in decimal
the sign and value of each number and their sum
a) -113 and -114, -227
b) -14 and -13, -27
c) -11 and -16, -27
d) -27 and -13, -40
90. Solve this binary problem 01110010 – 01001000 =?
a) 00011010
b) 00101010
c) 01110010
d) 00111100

91. What type of register would have a complete binary number

shifted in one bit at a time and have all the stored bits shifted
out one at a time?
a) Parallel in , parallel out
b) Parallel in , serial out
c) Serial in , parallel out
d) Serial in , serial out

92. The instruction that adds immediate data/contents of

memory location specified in an instruction/ register to the
contents of another register/ memory location is
a) SUB
b) ADD
c) MUL
d) DIV

93. In which of these modes, the immediate operand is included

in the instruction itself?
a) Register operand mode
b) Immediate operand mode
c) Register and immediate operand mode
d) Index operand mode
94. The instructions which after execution transfer control to the
next instruction in the sequence are called?
a) Sequential control flow instructions
b) Control transfer instructions
c) Sequential control flow and control transfer instructions
d) Register control instructions

95. The type of the interrupt may be passed to the interrupt

structure of CPU from
a) Interrupt service routine
b) Stack
c) Interrupt controller
d) Register

96. If exploiting and finding parallelism across branches require

scheduling code, a substantially very difficult algorithms is
a) Global scheduling
b) Local scheduling
c) Pre scheduling
d) Post scheduling

97. Decimal representation of this binary (1011)2 is

a) (9)10
b) (10)10
c) (11)10
d) (1)10

98. Loops when gets vectored then do not have dependences

among iterations of a loop, which are called
a) Data dependencies
b) Control dependencies
c) Loop-control dependencies
d) Loop carried dependencies
99. Addressing mode which is set to index arrays is applied to
indexed addressing mode, in computers is
a) Register addressing mode
b) Immediate addressing mode
c) Scaled addressing mode
d) Register indirect addressing mode

100. Which of the following addressing mode is best suited to

access elements of an array of contiguous memory locations?
a) Indexed addressing mode
b) Base registers addressing mode
c) Relative address mode
d) Displacement mode