COEN 212 - Digital Systems Design I - Fall 2024

Assignment 3 – Gate-level minimization and K-map; Design

1. Draw logic diagrams to implement the following functions (without simplification): (4 points)
a) 𝐹 = (𝑢 + 𝑦)′ + 𝑥
b) 𝐹 = 𝑢(𝑥 + 𝑧) + 𝑦′
c) 𝐹 = 𝑢 + 𝑥 + 𝑥′(𝑢 + 𝑦 ′ )
d) 𝐹 = (𝑢𝑥 + 𝑢′ 𝑥 ′ )(𝑦𝑧 ′ + 𝑦 ′ 𝑧)
COEN 212 - Digital Systems Design I - Fall 2024
2- Implement the Boolean function: (6 points)
F = xy + x ‘y ‘ + y ‘z
a) With AND, OR, and inverter gates
b) With NAND and inverter gates
c) With NOR and inverter gates

b)

c)
COEN 212 - Digital Systems Design I - Fall 2024
3- Consider the Boolean function 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(1, 3, 5) . (16 points)
Using K-map, derive the SOP and POS of F. Then, implement F with two levels of logic as:
a) AND-NOR
b) NAND-AND
c) OR-NAND
d) NOR-OR

Answer 3:

wx yz 00 01 11 10
00 0 1 1 0
01 0 1 0 0
11 0 0 0 0
10 0 0 0 0

F = w’x’z + w’y’z → SOP

From the K-map, F’ = w + z’ + xy
F = (F’)’ = (w + z’ + xy)’ = w’.z.(x’+ y’) → POS

a) F = (w + z’ + xy)’ → AND-NOR

b) F = (w)’.(z’)’.(x.y)’ = w’.z. (x.y)’ → NAND-AND

c) From the SOP of F,

F’ = (w’x’z + w’y’z)’
F’ = (w + x + z’)(w + y + z’)
F = (F’)’ = [(w + x + z’)(w + y + z’)]’ → OR-NAND
COEN 212 - Digital Systems Design I - Fall 2024

d) F = (w + x + z’)’ + (w + y + z’)’ → NOR-OR

4- Convert each of the following functions to its canonical form, and express each of them in the
forms of sum of minterms and product of maxterms: (9 points)
a) (c’+d)(b+c’)
b) bd’ + acd’ + ab’c + a’c’
c) b’d +a’d + bd

Answer 4:

This problem can be solved using either Boolean Algebra or a truth table.
a) (𝑐 ′ + 𝑑)(𝑏 + 𝑐 ′ ) = c’b + c’c’ + bd + c’d =
c’b(d + d’) + c’(b + b’) + bd(c + c’) + (b + b’)c’d =
bc’d + bc’d’ + bc’ + b’c’ + bcd + bc’d + bc’d + b’c’d =
bc’d + bc’d’ + bc’(d + d’) + b’c’(d + d’) + bcd + b’c’d =
bc’d + bc’d’ + bc’d + bc’d’ + b’c’d + b’c’d’ + bcd + b’c’d =
bc’d + bc’d’ + b’c’d + b’c’d’ + bcd =
∑(5, 4, 1, 0, 7) =
∑(0, 1, 4, 5, 7) =
∏(2, 3, 6).

b) bd’ + acd’ + ab’c + a’c’ = (a + a’)bd’ + a(b + b’)cd’ + ab’c(d + d’) + a’(b + b’)c’ =
abd’(c + c’) + a’bd’(c + c’) + abcd’ + ab’cd’ + ab’cd + ab’cd’ + a’bc’(d + d’) + a’b’c’(d +
d’)
= abcd’ + abc’d’ + a’bcd’ + a’bc’d’ + abcd’ + ab’cd’ + ab’cd + a’bc’d + a’bc’d’ + a’b’c’d
+ a’b’c’d’
= abcd’ + abc’d’ + a’bcd’ + a’bc’d’ + ab’cd’ + ab’cd + a’bc’d + a’b’c’d + a’b’c’d’
= ∑(14, 12, 6, 4, 10, 11, 5, 1, 0)
= ∑(0, 1, 4, 5, 6, 10, 11, 12, 14)
= ∏(2, 3, 7, 8, 9, 13, 15).
COEN 212 - Digital Systems Design I - Fall 2024
c) F = b’d + a’d + bd
a b d F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
From the truth table, F = ∑(1, 3, 5, 7) = ∏(0, 2, 4, 6).

5- Simplify the following functions using K-maps, and then derive the corresponding simplified
Boolean expressions. Note that d stands for don’t-care cases. (12 points)
a) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0,2,8,10, 12, 13, 14)
b) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
c) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∏(1,3,6,9,11,12,14)
d) 𝐹(𝑥, 𝑦, 𝑧) = ∑(0,4,5,6) and 𝑑(𝑥, 𝑦, 𝑧) = ∑(2,3,7)

Answer 5:

a) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0,2,8,10, 12, 13, 14)

wx yz 00 01 11 10
00 1 1
01
11 1 1 1
10 1 1

F = wz’ + x’z’ + wxy’

b) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)

wx yz 00 01 11 10
00 1 1 1
01 1 1
11 1 1
10 1 1 1

F = yz + x’z’ + wy + w’xz
COEN 212 - Digital Systems Design I - Fall 2024

c) 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = ∏(1,3,6,9,11,12,14)

AB CD 00 01 11 10
00 1 0 0 1
01 1 1 1 0
11 0 1 1 0
10 1 0 0 1

F’ = B’D + ABD’ + BCD’

F = (B + D’)(A’ + B’ + D)(B’ + C’ + D)

d) 𝐹(𝑥, 𝑦, 𝑧) = ∑(0,4,5,6) and 𝑑(𝑥, 𝑦, 𝑧) = ∑(2,3,7)

x yz 00 01 11 10
0 1 d d
1 1 1 d 1

F = x + z’

6- Implement each of the simplified functions in Question 5 with the corresponding gates. Assume
the inputs and their complements are available. (4 points)

Answer 6:
COEN 212 - Digital Systems Design I - Fall 2024

7- Implement each of the simplified functions in Question 6 with NAND logic gates. (4 points)
COEN 212 - Digital Systems Design I - Fall 2024

8- Implement each of the simplified functions in Question 6 with NOR logic gates. (4 points)

Answer 8:
COEN 212 - Digital Systems Design I - Fall 2024

9- Using K-maps, simplify the following Boolean functions and express each of them in sum-of-
products (SOP) and product-of-sums (POS) forms. (12 points)
a) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 1, 2, 5, 8, 10, 13)
b) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(1, 3, 6, 7, 8, 9, 12, 13, 14, 15)
c) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(2, 4, 10, 12, 14) and 𝑑(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 1, 5, 8)
d) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 4, 8, 9, 10, 11, 12, 14)
Answer 9:
a) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 1, 2, 5, 8, 10, 13)

wx yz 00 01 11 10
00 1 1 1
01 1
11 1
10 1 1
F = x’z’ + w’y’z + xy’z → SOP

wx yz 00 01 11 10
00 1 1 0 1
01 0 1 0 0
11 0 1 0 0
10 1 0 0 1
F’ = yz + xz’ + wx’z
F = (y’ + z’)(x’ + z)(w’ + x + z’) → POS
COEN 212 - Digital Systems Design I - Fall 2024
b) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(1, 3, 6, 7, 8, 9, 12, 13, 14, 15)

wx yz 00 01 11 10
00 1 1
01 1 1
11 1 1 1 1
10 1 1

F = wy’ + xy + w’x’z → SOP

wx yz 00 01 11 10
00 0 1 1 0
01 0 0 1 1
11 1 1 1 1
10 1 1 0 0
F’ = w’x’z’ + w’xy’ + wx’y
F = (w + x + z)(w + x’ + y)(w’ + x + y’) → POS

c) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(2, 4, 10, 12, 14) and 𝑑(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 1, 5, 8)

wx yz 00 01 11 10
00 d d 1
01 1 d
11 1 1
10 d 1

F = y’z’ + wz’ + x’z’ → SOP

wx yz 00 01 11 10
00 d d 0 1
01 1 d 0 0
11 1 0 0 1
10 d 0 0 1

F’ = z + w’xy
F = z’(w + x’ + y’) → POS

d) 𝐹(𝑤, 𝑥, 𝑦, 𝑧) = ∑(0, 4, 8, 9, 10, 11, 12, 14)

wx yz 00 01 11 10
00 1
01 1
11 1 1
10 1 1 1 1
COEN 212 - Digital Systems Design I - Fall 2024

F = wx’ + y’z’ + wz’ → SOP

wx yz 00 01 11 10
00 1 0 0 0
01 1 0 0 0
11 1 0 0 1
10 1 1 1 1

F’ = w’z + w’y + xz
F = (w + z’)(w + y’)(x’ + z’) → POS

10- Design a combinational circuit with three inputs x, y, and z and three outputs F1, F2, and F3
with the minimum possible number of gates, based on the following specifications:
(30 points)
• The output F1 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a
decimal number that is less than decimal 4, otherwise the output is 0.
• The output F2 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a
decimal number that is either 4 or an odd decimal number, otherwise the output is 0.
• The output F3 is 1 when the binary value of the inputs (the 3 bits together) is equivalent to a
decimal number that is either 0 or greater than decimal 4, otherwise the output is 0.

a) Your design steps must include: A truth table, K-maps, simplified Boolean expressions in
canonical and standard SOP forms, and implementations with logic gates.
Combine the logic diagrams into a single logic circuit having 3 inputs and 3 outputs.
In your implementations, assume the inputs and their complements are available
b) Identify the minimum number of gates in your design. How many gate-delays from the
inputs to each of the three outputs? If the delays from the inputs to each output are not
equal, redraw the logic diagram of your circuit with equal delays from the inputs to each
output.

Answer 10:
a)

x y z F1 F2 F3
0 0 0 1 0 1
0 0 1 1 1 0
0 1 0 1 0 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 1 0 1 1
1 1 0 0 0 1
1 1 1 0 1 1

𝐹1(𝑥, 𝑦, 𝑧) = ∑(0, 1, 2, 3)
𝐹2(𝑥, 𝑦, 𝑧) = ∑(1, 3, 4, 5, 7)
𝐹3(𝑥, 𝑦, 𝑧) = ∑(0, 5, 6, 7)
COEN 212 - Digital Systems Design I - Fall 2024

K-map for F1:

x yz 00 01 11 10
0 1 1 1 1
1 0 0 0 0
F1 = x’

K-map for F2:

x yz 00 01 11 10
0 0 1 1 0
1 1 1 1 0
F2 = xy’ + z

K-map for F3:

x yz 00 01 11 10
0 1 0 0 0
1 0 1 1 1
F3 = x’y’z’ + xy + xz

b)

The design with a minimum number of gates has four AND gates and two OR gates, where
one of the AND gates is 3-input and one of the OR gates is 3-input. All other gates are 2-
input.
COEN 212 - Digital Systems Design I - Fall 2024
From input x’ to F1, there is a 0 gate-delay.
From each input to F3, there are 2 gate-delays.
From the input y’ to F2, there are 2 gate-delays.
From the input z to F2, there is 1 gate-delay.

For the circuit to have equal delays from the inputs to the outputs, two gates must be
included in the path from x’ to F1, and one gate must be included in the path from z to
F2.

11- Consider the design of the 7-segment display presented in class. (12 points)
a) Write down the canonical form of the segment ‘g’ as sum of minterms and product of
maxterms.
b) Using a K-map, derive an optimal simplified Boolean expression for the segment g in
both SOP and POS forms.
c) Implement both SOP and POS with the minimum number of gates, assuming the inputs
and their complements are available.

Answer 11:
a)
𝑔(𝑤, 𝑥, 𝑦, 𝑧) = ∑(2, 3, 4, 5. 6, 8, 9) with 𝑑(𝑤, 𝑥, 𝑦, 𝑧) = ∑(10, 11, 12, 13. 14, 15)
𝑔(𝑤, 𝑥, 𝑦, 𝑧) = ∏(0, 1, 7) with 𝑑(𝑤, 𝑥, 𝑦, 𝑧) = ∏(10, 11, 12, 13. 14, 15)
COEN 212 - Digital Systems Design I - Fall 2024

b)

wx yz 00 01 11 10
00 0 0 1 1
01 1 1 0 1
11 x x x x
10 1 1 x x

g = w + yz’ + xy’ + x’y as SOP

g = w + yz’ + x ⊕ y with XOR
g’ = w’x’y’ + xyz as SOP for g’
g = (w + x + y)(x’ + y’ + z’) as POS for g

c)