EMBEDDED IOT SOLUTIONS | SMART TRANSCEIVERS

FT 6050 Smart
Transceiver
Ethernet
Interface
FT 6050 Smart Transceiver
Application (up to 256Kbytes)

14908-1 L4-L6 BACnet UART

LON LON/IP BACnet FT Custom IP BACnet
MS/TP
14908-1 L2-L3 IPv4

14908-1 MAC 14908-1 MAC (modified)

14908-2 PHY Neuron I/O

Ethernet
Interface
FT-X3 RS-485 PHY

Figure 1. FT 6050 Firmware Protocol Stacks

Product Description Features
The FT 6050 Smart Transceiver is a system-on-chip for modernizing • Built-in LON, LON/IP, BACnet FT,
and consolidating smart control networks. It is a key product in and BACnet MS/TP stacks provide
Adesto’s IzoT® platform — the most comprehensive and open compatibility with millions of LON and
control networking platform for the Industrial Internet of Things BACnet devices and enabling IP access to
(IIoT). It offers compatibility with the large installed base of LON every FT 6050 based device
FT and BACnet MS/TP devices while adding support for LON/IP • Built-in Free Topology (FT) transceiver
and BACnet/IP communication over the reliable and proven Free provides the most cost-effective, easy-to-in-
Topology (FT) channel. It is designed to bring unprecedented stall, and easy-to-use interface for commu-
flexibility and openness while lowering development and device nication with twisted-pair cables supporting
costs. polarity-insensitive free topology star, daisy
chain, bus, loop, or mixed topology wiring
The FT 6050 Smart Transceiver integrates a high-performance
and very high noise immunity
Neuron® core with an FT twisted-pair transceiver. Combined with
• Low-cost and royalty-free IzoT FT 6000
the proven FT-X3 Communications Transformer and inexpensive
EVK available for rapid application
flash memory, the FT 6050 Smart Transceivers provide a very
development and testing
flexible, low-cost, feature-enhanced LON FT, BACnet MS/TP, LON/
• Free and royalty-free IzoT SDKs available
IP, and BACnet/IP solution all within the same device with a single
for simple integration with other processors
application.
• Integrated quad core processor supports
A rich set of LonMark and IoT standard profiles and data types is applications up to 256KB for a 5x increase
included that you can use to further reduce application development over previous generations
time. • Supports up to 254 network variables
The FT 6050 Smart Transceiver includes four independent (NVs), 127 aliases and 254 address table
8-bit logical processors to manage the physical MAC layer, the entries (16x increase)
communication protocol stacks, the user application, and interrupts • Neuron core supports easy migration of
(see Figure 3, on page 2). existing applications written for previous
generation Neuron chips and smart
transceivers
product description

12 GPIO and 5 FT-X3

I/O FT PHY
USART Transformer

Flash 3 Serial
Memory Media
Memory Interface Access CPU
SPI

Network
Stack CPU
RAM
(64K x 8)

Interrupt
CPU

ROM
Application
(16K x 8)
CPU

Control, Clocks, Unique

Figure 2. FT Free Topology Network Configurations and Timers
48-bit
MAC ID

2
The FT 6050 Smart Transceiver supports polarity-insensitive
Crystal Reset Service
cabling using a star, bus, daisy-chain, loop, or combination
topology (see Figure 2). Installers don’t have to follow a strict set Figure 3. FT 6050 Smart Transceiver
of wiring rules imposed by other networking technologies. Instead,
they can install wiring in the fastest and most cost- effective manner,
thereby saving time and money. FT wiring also simplifies network
Features, continued
expansion by eliminating restrictions on wire routing, splicing, and
device placement. The FT 6050 extends all the benefits of FT wiring
to IP devices, allowing an efficient multi-drop IP capability where • Up to 80MHz system clock provides up
multiple IP devices can be very simply connected in any topology to a 16x performance improvement over
previous generations
without the need for switches or hubs.
• On-chip 64KB RAM and 16KB ROM
Multi-Protocol Operation
• 3.3V operation
The FT 6050 simultaneously supports up to four different
communication protocols, as shown in Figure 1 (page 1), allowing • User-programmable interrupts, hardware
USART, and 12 GPIO pins with 35
device makers unprecedented flexibility in creating control devices
configurable I/O drivers
for a wide variety of applications using one application. Backward
compatibility and future proofing can both be met using a common • Compatible with low-cost surface mount
FT-X3 Communications Transformer
platform based on the FT 6050 Smart Transceiver.
• Supports a rich set of LonMark® and IoT
For LON FT communication, the FT 6050 implements the complete standard profiles and data types to reduce
LON stack as defined by ISO/IEC 14908-1 and is fully backward application development time
compatible with devices running the LON stack, including devices
• Flash file system for data logging and
based on the Neuron 3120, Neuron 3150, or the FT 3120, FT 3150, or other applications requiring persistent
FT 5000 Smart Transceiver. storage
For LON/IP communication, the FT 6050 implements layers 4 • Unique 48-bit IEEE MAC ID
through 7 of the ISO/ IEC 14908-1 LON stack running on top of • 7mm x 7mm 48-pin QFN package
layers 2 and 3 of a UDP/IP stack. This allows the implementation • -40°C to 85°C industrial temperature range
of devices that are fully compatible with classic LON applications
while supporting native IP addressing at the device level. This allows
LON compatible applications to run unmodified over FT wiring while
gaining IP addressing at the device level.

2
product description
For BACnet/IP communication, the instruction set and architecture as the events triggered by selected state
FT 6050 implements a BACnet/ previous-generation Neuron core, changes on any of the 12 GPIO
IP standard stack running on top of including instructions for hardware pins, by on-chip hardware timer-
layers 2 and 3 of a UDP/IP stack. multiplication and division. The FT counter units, or by an on-chip high-
This enables BACnet/ IP-compliant 6050 Neuron core is source code performance hardware system timer.
applications to run on the easy-to- compatible with applications written MAC Layer Enhancements
use and easy-to-install FT channel, for the Series 5000 and 3100 Neuron The FT 6050 has an enhanced
pushing BACnet/IP all the way down core. MAC layer that allows frame sizes
to the simplest of devices, while Enhanced Performance up to 1280 bytes. This allows large
leveraging the ease-of-installation Neuron Core Speed IP frames to be carried over the FT
provided by LON commissioning The internal system clock for the channel without fragmenting the
tools. Devices thus provisioned are FT 6050 Smart Transceiver can be packet to provide better bandwidth
fully compatible and discoverable user-configured to run from 5MHz to utilization of the FT channel.
using industry standard, BTL certified, 80MHz. The required external crystal The dedicated processor cores for the
BACnet management clients. provides a 10MHz clock frequency, MAC and network protocol support
For BACnet MS/TP communication, and an internal PLL boosts the allows the application to have the
the FT 6050 implements a BACnet frequency to a maximum of 80MHz as same performance independent of
MS/TP stack that uses one of the FT the internal system clock speed. The the network traffic. Traditional uni-
6050 USARTS to communicate with Neuron 3120/3150 core divided the processor designs running popular
an external RS-485 transceiver using external oscillator frequency by two to transceivers such as RS-485 must
the BACnet MS/TP protocol. This create the internal system clock. An be interrupted repeatedly to receive
enables BACnet MS/TP-compliant FT 6050 Smart Transceiver running every packet on the network, even
applications to be implemented with an 80MHz internal system clock when the packet turns out to not
in parallel with LON, LON/IP, and is thus 16 times faster than a 10MHz be addressed to the device. This
BACnet/ IP applications running on Neuron 3120 or Neuron 3150 core. increases the demands on the
the FT 6050. The Neuron core inside the FT 6050 application processor and makes the
For other IP applications, the FT 6050 Smart Transceiver includes a built- amount of processing available to
implements a UDP/IP stack that an in hardware multiplier and divider the application difficult to predict as
application can use to create any type to increase the performance of it becomes a function of the network
of IP interface that communicates with arithmetic operations. load.
the easy-to-use and easy-to-install FT Higher Protocol Limits JTAG Interface
channel. The FT 6050 Smart Transceiver The FT 6050 Smart Transceiver
Compatibility supports up to 254 network variables provides an interface for the Institute
The FT 6050 series Smart Transceiver per application, up to 127 aliases, of Electrical and Electronics Engineers
is fully compliant with LON devices and up to 254 address table entries. (IEEE) Standard Test Access Port and
implementing the ISO/IEC 14908- This is a significant increase over Boundary-Scan Architecture (IEEE
1 protocol on the FT channel type the previous limits of 62 network 1149.1-1990) of the Joint Test Action
defined by ISO/ IEC 14908-2 and variables, 62 aliases, and 15 address Group (JTAG) to allow an FT 6050
can communicate with devices that table entries which simplifies network chip to be included in the boundary-
use Echelon’s FTT-10 or FTT- 10A installation and supports more scan chain for device production
transceivers, FT 3120 or FT 3150 complex applications. tests.
Smart Transceivers, LPT-10 or LPT-11 Interrupts GPIO
Link Power Transceivers, or other ISO/ The FT 6050 Smart Transceiver The FT 6050 Smart Transceiver
IEC 14908-2 compliant transceivers. lets developers define application provides 12 bidirectional GPIO pins
The Neuron core in the FT 6050 interrupts to handle asynchronous that are 5V-tolerant and can be
Smart Transceiver uses the same

3
product description
configured to operate in one or increase in application size that can for use with the FT 6050 Smart
more of 35 predefined standard be hosted on the FT 6050 compared Transceiver: Macronix MX25L8035E,
input/ output modes. The chip also to previous generations. Micron M25PX80, ON Semiconductor
has two 16-bit timer/counters and The application code and LE25U40CM, Winbond W25X40CL,
a hardware USART that reduce the configuration data are stored in the Winbond W25Q80BV.
need for external logic and software external non-volatile memory (NVM) Noise Immunity
development. and copied into the internal RAM A LON device based on the FT 6050
Memory Architecture during device reset; the instructions Smart Transceiver is composed
The FT 6050 Smart Transceiver then execute from internal RAM. of two components: the FT 6050
eliminates the need for external Writes to NVM are shadowed in the Series Smart Transceiver and an
serial EEPROM that the previous internal RAM and pushed out to external communications transformer
generation FT 5000 required and external NVM by the Neuron firmware. such as the FT-X3 communications
instead relies only on inexpensive The FT 6050 Smart Transceiver transformer. The transformer enables
external flash memories for non- supports serial peripheral interface operation in the presence of high
volatile application and data storage, (SPI) for accessing off-chip, non- frequency common-mode noise on
and for Neuron firmware upgrades. volatile memory. unshielded twisted-pair networks.
It has 16KB of ROM and 64KB (44KB The FT 6050 Smart Transceiver Properly designed devices can meet
user-accessible) of RAM on the chip. supports a variety of flash devices; we the rigorous Level 3 requirements
Each chip, contains a unique identifier recommend: of EN 61000-4-6 without the need
(IEEE MAC ID) in an on-chip, non- for a network isolation choke. The
Adesto AT25SF041B or Adesto
volatile, read-only memory. Typical transformer also offers outstanding
AT25SF081B
external flash memory configuration immunity from magnetic noise,
is 1MB of which 256KB is available for Adesto has also qualified the eliminating the need for protective
application code. This is a five-fold following SPI flash memory devices magnetic shields in most applications.

6K chip design information

SDA_CS1~
VDD1V8

VDD3V3
VDD3V3

RXON
TXON
MOSI

MISO

CS0~
SCK

SCL

CP4

GND PAD
48
47
46
45
44
43
42
41
40
39
38
37

SVC~ 1 36 GND
IO0 2 35 NC
IO1 3 34 NETP
IO2 4 33 AGND
IO3 5 32 NETN
VDD1V8 6 31 AVDD3V3
IO4 7 30 VDD3V3
VDD3V3 8 Series 6000 29 VIN3V3
IO5 9 28 RST~
IO6 10 27 VOUT1V8
IO7 11 26 GNDPLL
IO8 12 25 VDDPLL
13
14
15
16
17
18
19
20
21
22
23
24
IO9
IO10
IO11
VDD1V8
TRST~
VDD3V3
TCK
TMS
TDI
TDO
XIN
XOUT

Dashed line represents Pad (pin 49)

Pad must be connected to GND

Figure 4. 6K IC Pin Configuration Figure 5. Recommended 6K Pad Layout

4
6K ic mechanical specification

Figure 6. 6K IC Dimensions
Notes:
1. Unlabled dimensions are in millimeters.
2. Dimensions and tolerances conform to ASME Y14.5M.-1994.
3. Package warpage max. 0.08 mm.
4. Package corners unless otherwise specified are R0.175±0.025 mm.

FT-X3 design information

Figure 7. FT-X3 Pin Configuration and Pin-out

Figure 9. FT-X3 Pad Layout

Note: Add vias to the ends of each pin pad connection (just outside
oftheSMTpadrectangles)toprovideadditionalmechanicalsupport
Figure 8. FT-X3 Transformer Pin Assignments
for the transformer
Note: There is no marking for Pin 1 on the FT-X3
because it is rotationally symmetrical
5
FT-X3 mechanical specifications

Figure 10. FT-X3 Dimensions

6K and FT-X3 tape and reel information

Note: 6K ICs are uniformly
loaded in the carrier tape such
that pin 1 is oriented in quadrant
1 toward the side of the tape
having round sprocket holes.

User Direction of Feed Notes:

Figure 11. 6K Tape and Reel Orientation 1. All dimensions in mm
2. Tolerances unless noted: 1PL +
Figure 12. 6K Carrier Tape Outline 0.2. 2PL + 0.1
3. 10 Sprocket hole pitch
cumulative tolerance +0.2
4.CambercompliantwithEIA481
5. Pocket position relative to
sprocket hole measured as true
position of pocket, not pocket
hole
For more information, refer to
EIA-481-B, “Taping of Surface
MountComponentsforAutomatic
Figure 14. FT-X3 Reel and Tape Device Placement Placement”

Figure 13. 6K 7″ Reel and Hub Dimensions

Notes:
1.Material:blackconductivepolystyrenePS
2. Inspect per EIA-481-3 standard.
3. Tape thickness: 0.5 ±0.05 mm
4. 10 Sprocket hole pitch cumulative
tolerance ±0.20
5. Carrier chamber is within 1 mm in 100 mm
6. Packing length per 22” reel: 10.2 meters
7. Packing length per 13” reel: 3.4 meters
8. Component load per 13” reel: 100 PCS
9. Compression strength: 1.5 kgf min.
Figure 15. FT-X3 Reel and Hub Dimensions in mm 10. Environment-related substance must
Note: Tolerances unless noted: 1PL + ; 2PL + 0.2; meet DELTA’s general spec no. 10000-0162
3PL + 0.1; ANG + 0.5”; FRACT + Figure 16. FT-X3 Carrier Tape Packing
6
application development

A typical FT 6050 Smart Transceiver-based device requires a

power source, crystal, external memory, and an I/O interface to Serial Flash
Memory
the device being controlled (see Figure 17). SPI

Sensors or Actuators:

Adesto provides all of the building blocks required to Motors, Valves,

Lights, Relays,
FT 6050
FT-X3
Switches, Temperature I/O External
successfully design and field cost-effective, robust products Sensors, Flow Sensors,
Light-Level Sensors,
SoC
Transformer

based on the FT 6050 Smart Transceiver. Adesto’s end-to-end Motion Sensors

solutions include a comprehensive set of development tools, 10MHz Power Source

Crystal
network interfaces, routers, and network tools. In addition, LON FT Channel

pre-production design review services, training, and worldwide

technical support (including onsite support) are available Figure 17. Typical FT 6050-based Device
through Adesto’s Support technical assistance program.
The following development tools are available for developing
applications for the FT 6050 Smart Transceiver:

IzoT FT 6000 EVK — a complete IzoT SDK Premium Edition — a IzoT ShortStack SDK — a free
hardware and software platform for software development kit that enables software development kit, available at
creating or evaluating LON, LON/ developers to build communicating github.com/izot/shortstack, that enables
IP, BACnet FT, and BACnet MS/TP devices using any processor that developers to build communicating
devices based on an Adesto smart runs Linux for the application and devices using any processor that can
transceiver or Neuron chip. Using the Layers 3 through 7 of the LON/IP and run the application plus a tiny IzoT
FT 6000 EVK, developers can create LON protocol stacks. The IzoT SDK ShortStack driver. The IzoT ShortStack
applications that run on the FT 6050 Premium Edition includes royalty- SDK includes royalty-free firmware for
Smart Transceiver using the highly free firmware for the FT 6050 Smart the FT 6050 Smart Transceiver that
productive Neuron C programming Transceiver that enables the FT 6050 enables the FT 6050 to be used as a
language. to be used as a PHY chip to interface Layer 2 to 6 LON and LON/IP protocol
to an FT channel. processor with integrated PHY interface
to an FT channel.

7
product specifications
Data Communications Type Network Wiring Operating Humidity
Differential Manchester encoding 24 to 16AWG twisted pair; see Series 25-90% RH @50°C, non-condensing
Network Polarity 6000 Chip Data Book or Junction Box (FT-X3 Communications Transformer)
Polarity insensitive and Wiring Guidelines engineering Non-operating Humidity
bulletin for qualified cable types 95% RH @ 50°C, non-condensing (FT-
Isolation between Network and FT 6050
0-60Hz, 60 seconds: 1000Vrms; Network Length in Free Topology X3 Communications Transformer)
0-60Hz, continuous: 277Vrms 500m (1640 feet) maximum total wire Vibration
with no repeaters; 500m (1640 feet) 1.5g peak-to-peak, 8Hz-2kHz (FT-X3
EMI maximum device-to-device distance
Compliant with FCC Part 15 Subpart B Communications Transformer)
and EN55022 Level B Network Length in Doubly-terminated Mechanical Shock
Bus Topology 100g (peak) (FT-X3 Communications
ESD 2700m (8,850 feet) with no repeaters
Compliant with EN 61000-4-2, Level 4 Transformer)
Maximum Stub Length in Doubly- Reflow Soldering Temperature Profile
Radiated Electromagnetic Susceptibility terminated Bus Topology
Compliant with EN 61000-4-3, Level 3 Refer to Joint Industry Standard IPC/
3m (9.8 feet) JEDEC J-STD-020D.1 (March 2008)
Fast Transient/Burst Immunity Network Termination
Compliant with EN 61000-4-4, Level 4 Peak Reflow Soldering Temperature
One terminator in free topology; two 260°C (FT 6050 Smart Transceiver)
Surge Immunity terminators in bus topology (more
Compliant with EN 61000-4-5, Level 3 245°C (FT-X3 Communications
details in Series 6000 Chip Data
Transformer)
Conducted RF Immunity Book).
Compliant with EN 61000-4-6, Level 3 Co-planarity
Power-down Network Protection
0.12mm (FT-X3 Communications
Transmission Speed High impedance when unpowered
Transformer)
78 kilobits per second Operating Temperature
Mass
Number of Transceivers per Segment -40° to 85°C
6g (FT-X3 Communications
Up to 64 Transformer)

Model # Product Name Product Description

14450R-500 FT 6050 Smart Transceiver Tape and reel package, quantity 500

14255R-100 FT-X3 Comunications Transformer Tape and reel package, quantity 100

10070R-43-54 IzoT FT 6000 EVK Hardware and software development kit

23360-10 IzoT SDK Premium Edition Software development kit

23400-FV IzoT Short Stack SDK Software development kit available at www.github.com/izot/shortstack

Copyright ©2022 Renesas Electronics Corp. All rights reserved.

003-0527-01A rev 5/2020

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