INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

A Low NF, High Gain Of 2.4ghz Differential LNA

Design For Wireless Applications
Mahesh Mudavath, K. Hari Kishore

Abstract: This article presents the differential Low Noise Amplifier (LNA) for wireless receiver at the frequency of 2.4GHz. This differential provides
less noise figure (NF), high gain and good reverse isolation as well as good stability. The designed LNA is simulated with a 180 nanometers CMOS
process in cadence virtuoso tool and simulate the results by using SpectreRF simulator. This LNA exhibits an input reflection coefficient (S 11) of -8.4dB
and output reflection coefficient (S22) of -10dB. It produces a noise figure (NF) of 0.54dB, a high voltage gain (S21) of 30dB, a good reverse isolation (S12)
of -48dB, and it maintains good stability of Rollet factor Kf > 1, and also alternate stability factor B1f < 1, respectively.

Index Terms: Cascode-stage; cascade differential; input matching; inductive source degeneration; low noise amplifier; noise figure.
——————————  ——————————

1. INTRODUCTION receivers [4]. However, this approach requires increases the

In modern years, an instantaneous improvement in technology complication of the receiver, and bulky chip area [3]. The
as well as market has raised better quality by means of substitute technique employs the switched inductors, or
telecommunications and portable electronic devices [1]. The switched capacitors, in the input and output matching
majority of the communication systems could be hand-held; networks. This switching technique can’t offer an appropriate
hence device with compressed size is a challenging task for IC match for both band of frequency and it also restrictions to
manufacturer. The key challenge for compact device size of receive one frequency band at a time. But the cascade
such systems, directly that it affects power usage and differential LNA design is able to offer an improved trade-off
portability. Conversely, the essential demands of high between power gain, & noise figure [3]. This paper is
frequency devices for huge data rate wireless systems such as prearranged as follows. Section-2 covers the importance of low
IoT (internet of things) [2], and wireless LAN. These are noise amplifier and different blocks. Section-3 explains the
broadly used in homes and offices to offer multi-standard different techniques of LNA topologies and fundamental
receivers [3]. By the number of portable devices will theoretical calculations for design parameters. Section-4 is the
go beyond billion and more and it will be used at extremely description about the circuit design and analysis. The
wide area such as an urban area, an indoor area, a mountain simulation plots are exposed in Section-5 and finally, Section-6
area and so forth [2]. CMOS technology for high frequency concludes this paper.
integrated circuits is an appropriate solution. In an advanced
CMOS process the challenging factors for design and 2. LOW-NOISE AMPLIFIER
development of the LNA building blocks are circuit linearity, Every signal is analog and we handle with the right device &
decreasing supply voltage, low noise figure (NF), and high flow. A low-noise amplifier is the foremost stage of the receiver
gain. The receivers are broadly utilized in RF radio frequency front-end and it is used to amplify the signal which is coming
systems. In reality, a receiver is capable to accept every signal from the antenna terminals whilst introducing a smaller amount
from low to high frequency, and the received signals are of noise by the same LNA [5]. Actually the LNA consist of five
typically very noisy and weak [1]. Consequently, the LNA is different parts, which are appropriate topologies, input
desired to amplify the received signals and transfer to the impedance matching network, inductive source degeneration
subsequent stages. Annually, there are many techniques have circuit, biasing circuit, and output impedance matching
been exploring for LNA design. Nonetheless, all design network. The universal topology of any LNA circuit can be
parameters simultaneously can’t be satisfied or achieved for a consists of three stages. It has the input matching block, core
Radio Frequency (RF) system. Hence, a trade-off between the amplifier and finally output matching block. To get better
issues of LNA is supposed to be done as to achieve an design performance the input/output matching network can try
adequate performance over the preferred bandwidth. For the to maintain similarity. It is measured from s-parameters of input
design of LNA, noise figure is one of the important key return loss co-efficient and output return loss co-
parameter, as it shows the entire system noise presentation in efficient . Generally, these values should be in the range of
a receiver, and also more power gain, low power consumption, less than or equal to -10dBm.
and good input matching are significant key parameters [1]. The stability of the two-port network is analyzed using s-
Here, the simple way to design a cascade-stage and parameters. The essential and sufficient condition for stability
differential LNA to amplify weak and noisy signals for wireless is to take Rollet factor and also alternate stability
factor , which are expressed in terms of s-parameters
————————————————
 Research Scholar, KLEF (Deemed to be University), [1].
Vaddeswaram, Guntur Dist. (AP), India. ( | | | | | | )
( | |)
(1)
 Asst. Professor, Vaagdevi College of Engineering.
Bollikunta, Warangal (TS), India. | | | | | | (2)
[email protected] Where
 KLEF (Deemed to be University), Vaddeswaram, ( )
Guntur (AP), India
 [email protected]
If > 1 & , the network would be unconditionally
stable.
109
IJSTR©2019
www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

3. SINGLE-ENDED, CASCODE STAGE, AND

CASCADE DIFFERENTIAL AMPLIFIER
The amplification block of the cascode circuit is revised during Where ( )
this analysis to attain an optimized performance in single-
ended and differential topologies. A single-ended signal
measured with relation to a preset potential-gnd. Further, as a
result of the differential signal measured between each node √
that have equivalent and opposite excursions in the order of a
fixed potential. To be precise each node should exhibit
equivalent impedances to its potential. The center potential √ √ (6)
within the differential signal is named the common-mode level.

3.1. Single transistor amplifier

An amplifier may be a device for increasing the ability of a
signal. This can be often accomplished by taking power from 3.2. Cascode transistor amplifier
and controlling the output to duplicate the form of the The signal flows through the gate of the first transistor , and
signal but with a bigger (current or voltage) amplitude. During the gate of the second transistor . The bias reference
this sense, an amplifier could be attention of as modulating the voltage is fixed at gate of the second transistor , such
voltage or current of the ability of a signal to provide its output. that both transistors operate in saturation mode. The lower
transistor acts as a common source amplifier, whereas the
upper transistor works in the common gate configuration and
also it act as isolating output nodes from input.
To analyze the cascade stage and its circuit performance, we
treat the two series connected transistors as a single
compound transistor with the gate and source of and drain
of acting as the corresponding terminals of the equivalent
transistor.

Fig. 1. Single transistor amplifier

To measure the drain current shown in Fig. 1 it is a function

of gate voltage which is applied at the gate terminal, and
drain voltage which is taken from the drain terminal.
( ) (3)
For multiple signals, by applying partial derivation to the
equation 3, then the change of current defined as.
(4)
Since

Fig. 2. cascode amplifier

and
To measure the drain current for cascode amplifier shown in
Fig. 2 is a function of gate voltage which is applied at the
Assumed and then gate terminal, and drain voltage which is taken from output
of drain terminal.
(Suppose is very small) ( )
Then the voltage gain can be defined as
(5)
|
Assuming transistor is in saturation region, and then the
current can be expressed as.
|
( )[ ] -------For saturation region
( ) *( ) + ---For linear region
For MOSFET should have varied to the signal applied at We then evaluate its equivalent and . Since the two
input. In saturation region, varies with respect to input transistors are in series, then the drain currents of both
voltage else varies both , and . transistors are equal i.e.
( ) Here, current for both and
Define

And

110
IJSTR©2019
www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

[ ]

[ ]
Fig. 3. The small- signal model analysis for cascode.

Generally values are very much higher than values. In Writing the KCL equation at the output we get
this case, we can see that

This leads to
| ( ) ( )
We should make and evaluate the change of drain
current according with change in the drain voltage of to
Since is quite large, is very small compare to , at
get .
the drain of the lower transistor is.
( )

(for ) ( )
( ) (for ) ( )
( ) ( )
( ) ( )
( )
( )( )
[ ]
But
( )
( )( )
[ ]
This gives
We can define the individual gains of the two transistors (in ( )
CS and CG configurations respectively) [6]. Then the voltage ( )( )
gain can be defined as.
( ) ( )
( )( )
( ) If is small we can simplify the above relation to get.
( ) (8)
( )
[ ]
------- For CS stage 3.3. Differential amplifier
The differential of is broadly used because of its
and
advantages of common-mode (CM) noise immunity [7]. Hence,
* + ---- For CG stage they offer differential output that is needed by the following
(7) stages of shown in Fig. 4. The selection of cascode
Here, the effective of cscode is same as the single topology within initial stage degrades the noise presentation of
transistor amplifier. the amplifier yet if it improves the gain. To occupied less chip
area by using single ended LNAs, but if the amplifier design is
3.2.1. AC behavior single ended, it’s a lot of vulnerable to noise and alternate
The small- signal model analysis for cascode transistor shown interferences [8].
in Fig. 3. The equivalent transconductance for the
cascode stage is regarding the similar to the single transistor
stage, the product of Gain Bandwidth ( ) also remains
unchanged. Because of high output impedance, the bandwidth
is reduced and the DC gain is increased for a cascade-stage.

111
IJSTR©2019
www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

3.4. INPUT MATCHING AND GAIN

The most important purpose of input matching n/w is to attain
the maximum power transfer rate from input to output
terminals, which is happens when impedance matches. The
received signals from the antenna terminals, assumed as
voltage source that is connected to a LNA. The source
impedance ( ), generally the resistance of the antenna’s, can
be specified as . For that reason, the LNA’s input
impedance ( ), be required to match the exact 50Ω in
regulate to transfer the maximum power to the subsequent
Fig. 4. Differential outputs. stage of the system [11].

Alternatively, by using the differential amplifier very less The input impedance of designing LNA can be expressed as
amount of liable to noise and intervention are presented [9]. beneath equation (9) [8] [12].
Also the differential amplifier has the advantage, of getting the ( ) (9)
( ) ( )
signal swing which will be a double that of the single-ended
Where, are the transconductance and gate-source
swing lying on the similar supply voltage, in that way
capacitor of the respectively. The input impedance
increasing signal-to-noise ratio (SNR) [8].
matching network consists of, , and resonate at the
3.3.1. Noisy supply voltages frequency of operation, the imaginary part of impedance is
For single ended operation, if changes by , then output neglected [13]. For this context, the pure real part will be
also changes by the same amount shown in Fig 5. considered for input impedance with only relevant to & ,
- Output is quite susceptible to supply noise. consequently by adjusting & can simply realize to a real
- Differential operation: if the circuit is symmetric, supply impedance at the input of the LNA can be expressed as
noise affects and but not [10] . below equation(10) [14].
(10)
( )
To calculate the required of LNA with the help of ,
, , and .
As a result, and can be obtained by equation 11 and 12
[15].
(11)
( )
(a) (12)
Hence, the voltage gain Av can be defined as.
( ) (13)
( )

4. CIRCUIT DESCRIPTION
A. Cascode Configuration.
The universal topology of LNA is consists of 3 stages: staring
with input matching set-up, the core amplifier design, and
finally the output matching set-up [16]. To begin with, input
(b) matching necessities are fulfilled by putting an inductor Lg at
Fig. 5. Noisy signals for (a) single-ended (b) differential paths gate of MOSFET transistor it allows resonating at the centre
freq. To realize low NF in given structure, an inductor Ls is
Max achievable voltage swings increase. located on source terminal; it acts as inductive source
Max output swing at or is ( ) degeneration [16]. The capacitance Cgd is worn for wide-band
Where as is [ ( )] matching. Therefore the Lg, Cgd and Ls provide the input
Simpler biasing and higher linearity matching network for wide-band matching. At the output side
Disadvantages: Ld and Cd is resonating to a particular frequency [16].
Double the area with respect to single ended counterpart
Advantages of differential signaling B. Cascade Differential Configuration
1. Employing differential paths for sensitive signals,
higher immunity to environmental noise
2. Noise cancelled.
3. Highest achievable voltage swings
4. Simpler biasing and better linearity
Conclusion: Because of symmetry, common mode signal
rejected.

112
IJSTR©2019
www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

Fig. 7 Simulated voltage gain S21=30dB @ 2.4GHz center

frequency

The plot of Noise Figure is shown in the Fig. 8, a noise figure

(NF) of 0.54dB @ 2.4GHz is obtained.

Fig. 6. Differential circuit design

The projected differential cascade LNA [17] [18] is illustrates in

Fig. 6. This differential design includes the each side inductive
degenerated CS and a CG stage of transistor M1 and M2. Also
it consists of input gate inductor Lg, source inductor Ls, gate-to-
source capacitors Cgs, respectively for both sides [17]. The
benefit of input output and noise matching simultaneously, with
the help of inductive source degenerated through inductor Ls.
For the purpose of input matching at the input ports, the DC
blocking capacitor CB and an off chip capacitor Cp are used. To
optimize the power gain & noise of the LNA, a very small value
of shunt capacitance Cs is connected at the input port.
Transistors M5 and M6 commonly called as cascade devices,
hence it formed as CG stage cascaded to the input stage [17]
[19]. The benefit of the cascade device using in LNA circuit is
essentially shields the output from the input stage; hence it
extremely improves the power gain and reverse isolation (S 12)
[20]. At the output ports, the LC resonance tank circuit consists Fig. 8 Simulated noise figure (NF) =0.54dB @ 2.4GHz center
of the MIM capacitors C1, C2, tuning inductor LT, and the total frequency
drain terminal to node capacitances are required to tuning the
desired frequency and also for output impedance matching. Fig. 9 gives the plot of the reverse isolation (S12) that is
provided by the circuit. The value of the isolation that was
5. SIMMULATED RESULTS obtained is -48dB @ 2.4GHz which are very good figure. This
The design parameters of the LNA circuit are analyzed with is attributed to the resonating circuit that is inserted between
respect to the frequency of 2.4GHz operation. A plot of the S- the two stages.
parameters and required parameters is shown from Fig. 7 to
Fig. 13. The S21 plot is of importance as it gives the gain of the
amplifier. As it can be seen from Fig. 7, a gain of 30dB is
obtained at 2.4GHz which falls right in our desired range.

113
IJSTR©2019
www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

Fig. 12 presents P1dB compression point which is -10.6dBm

and linearity performance of the proposed LNA.

Fig. 9 Simulated reverse isolation (S12) = -48dB @2.4GHz

center Frequency

Fig. 10 shows the plot of the input reflection coefficients (S 11),

and its obtained value is -8.4dB @ 2.4GHz
Fig. 12 The simulated 1dB Compression point (P1dB) =-
10.6dBm

IIP3 of the designed LNA is presented in Fig. 13, with respect

to this figure, its value is -14dBm.

Fig. 10 Simulated input return loss S11= -8.4dB @ 2.4GHz

center frequency

Fig. 11 shows the plot of the output reflection coefficients (S 22),

and its obtained value is -10dB @ 2.4GHz. Fig. 13 The simulated IIP3=-14dBm

The simulated results are summarized and compared to other

related works in the area of LNA design and also with some
designs employing the cascode and cascade strategy. The
results are tabulated in table 1.

Table 1: Performance summary and comparison of CMOS

LNAs
Parameters This [9] [2] [4 ]
work

Center Frequency 2.4 2.4 2.4 5.2 1.2 1.5

(GHz) 7
CMOS Tech. (nm) 180 180 180 180
Power Gain (dB) 30 12.68 16.5 11. 26.9 27.
1 5
Noise Figure (dB) 0.54 3.14 3.1 3.7 2.3 2.3
Fig. 11 Simulated output return loss S22= -10dB @ 2.4GHz S11 (dB) -8.4 -13.5 -14 -16 -11 -13
center frequency S12 (dB) -48 -33.8 --
S21 (dB) 30 12.68 16 11 26.9 27.
5

114
IJSTR©2019
www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

S22 -10 -10 -6 -8 Band Communication System," in IEEE MTT-S

1dB Compression -10.6 International Microwave and RF Conference (IMaRC),
point (P1dB)
IIP3(dB) -14
2017 , pp. 35-38.
Stability Factor [9] Nandini Shrivastava and Rajesh Khatri, "Design of a 2.4-
(Kf) 1.09 4.84 10 5 -- -- GHz Differential Low Noise Amplifier using 180nm
(B1f) 0.97 0.94 technology," in Proceeding International conference on
Power supply (V) 1.8 1.8 1.8 1.8
Recent Innovations is Signal Processing and Embedded
6. CONCLUSION: Systems (RISE-2017), 2017, pp. 494-497.
The field of wireless receiver communications has undergone [10] Dhananjaya Tripathy, Shasanka Sekhar Rout, and Kabiraj
enormous growth, moving quickly during a sequence of Sethi, "A Low Power Noise Cancelling LNA for UWB
generations in the present scenario. The receiver design with Receiver Front End," in 2015 IEEE Power, Communication
low noise is a foremost design constraint. For this context, the and Information Technology Conference (PCITC),
design of the LNA for better performance is of immense Bhubaneswar, India., 2015.
importance. The proposed LNA for Radiofrequency front-end is [11] Mahesh Mudavath and K. Hari Kishore, "Design and
designed with very little NF & high gain using 180nanometer in Analysis of Receiver Front-End of CMOS Cascode
cadence virtuoso tool and simulate the results by using Common Source Stage with Inductive Degeneration Low
SpectreRF simulator. This LNA exhibits an input reflection Noise Amplifier on 65 nm Technology Process," Journal of
coefficient (S11) of -8.4dB and output reflection coefficient (S22) Computational and Theoretical Nanoscience, vol. 16, no.
of -10dB. It produces a noise figure (NF) of 0.54dB, a high 5-6, pp. 2628-2634, May 2018.
voltage gain (S21) of 30dB, a good reverse isolation (S12) of - [12] Mahesh Mudavath and K.HariKishore, "Design of CMOS
48dB, and it maintains good stability of Rollet factor Kf > 1, and RF Front-End of Low Noise Amplifier for LTE System
also alternate stability factor B1f < 1, respectively. Applications," Asian Journal of Information Technology,
Medwell Journal, vol. 15, no. 20, pp. 4040-4047, 2016.
REFERENCES: [13] A. Surendar, K. H. Kishore, M. Kavitha, A. Z. Ibatova, V.
[1] Tayebe Mohammadi, Alireza Ghaneizadeh, and and Samavatian ―Effects of Thermo-Mechanical Fatigue and
Yasser Mafinejad, "A Narrow-Band CMOS LNA for Low Cycle Fatigue Interaction on Performance of Solder
Wireless Communications," in 26th Iranian Conference on Joints,‖ IEEE Transactions on Device and Materials
Electrical Engineering (ICEE2018), 2018, pp. 265-268. Reliability, P-ISSN: 1530-4388, E-ISSN: 1558-2574, Vol
[2] Atsuhiro Hamasawa and Haruichi Kanaya, "Dual-band No: 18, Issue No: 4, Page No: 606-612, December-2018.
differential outputs CMOS Low Noise Amplifier," in 2018 [14] Mahesh Mudavath and K Hari Kishore, "RF Front-End
IEEE 20th Electronics Packaging Technology Conference Design of Inductorless CMOS LNA Circuit with Noise
(EPTC), Singapore, pp. 661-664. Cancellation Method for IoT Applications," International
[3] Hossein Khosravi, Salman Zandian, Abolfazl Bijari, and Journal of Innovative Technology and Exploring
Nabeeh Kandalaft, "A Low Power, High Gain 2.4/5.2 GHz Engineering (IJITEE), vol. 8, no. 6S, pp. 176-183, April
Concurrent Dual-Band Low Noise Amplifier," in 2018 IEEE 2018.
9th Annual Computing and Communication Workshop and [15] Vaithianathan, J. Raja, R. Kavya, and N. Anuradha, "A 3.1
Conference (CCWC), Las Vegas, NV, USA, 2018, pp. to 4.85GHz differential CMOS low noise amplifier for lower
0788-0792. band of UWB applications," in 2010 International
[4] M. Safari, M. Eghtesadi, and M. R. Mosavi, "A Concurrent Conference on Wireless Communication and Sensor
Dual-Band Low Noise Amplifier for GNSS Receivers," Computing (ICWCSC), Chennai, India, 2010.
Iranian Journal of Electrical and Electronic Engineering, [16] J.Manjula, P.Sai Krishna, and and D.Rubeena, "Design
vol. 12, no. 2, pp. 119-125, June 2016. and Performance Analysis of Active Inductor Based
[5] M.Sumathi and S.Malarvizhi, "Study on Performance Reconfigurable Regulated Cascode LNA for Tunable RF
Analysis of CMOS RF front-end circuits for 2.4GHz Front End," in International Conference on Communication
Wireless Applications," Study on Performance Analysis of and Signal Processing, India, April 6-8, 2017, pp. 0222-
CMOS RF front-end circuits for 2.4GHz Wireless 0227.
Applications International Journal of Electrical and [17] Shaikh K. Alam and Joanne DeGroat, "A 1.5-V 2.4 GHz
Electronics Engineering (IJEEE), vol. I, no. II, pp. 18-23, Differential CMOS Low Noise Amplifier for Bluetooth and
2011. Wireless LAN Applications," in 2006 IEEE North-East
[6] Pratap Tumkur Renukaswamy, Vijaya Pasupureddi, and Workshop on Circuits and Systems, Gatineau, Que.,
and Johannes Sturm, "Analysis and Design of Differential Canada, 2006, pp. 13-16.
Feedback CG LNA Topologies for Low Voltage [18] Jinhua Liu, Guican Chen, and Ruizhi Zhang, "Design of a
Multistandard Wireless Receivers," in 2016 24th Austrian noise-canceling differential CMOS LNA for 3.1–10.6 GHz
Workshop on Microelectronics, 2016, pp. 24-29. UWB receivers," in 2009 IEEE 8th International
[7] Ratan Smrity et al., "Design of 2.4 GHz Differential Low Conference on ASIC, Changsha, Hunan, China, 2009, pp.
Noise Amplifier Using 0.18μm CMOS Technology," in 1169-1172.
International Conference on Computing, Communication, [19] Neeraja A R and Siva S Yellampalli, "Design of Cascaded
and Automation, 2016, pp. 1435-1439. Narrow Band Low NoiseAmplifier," in 2017 International
[8] Raghu S and Punithavathi Duraiswamy, "High Gain and Conference on Electrical, Electronics, Communication,
Low Noise Figure Single-to-Differential CMOS LNA for Ka- Computer and Optimization Techniques (ICEECCOT).

115
IJSTR©2019
www.ijstr.org
INTERNATIONAL JOURNAL OF SCIENTIFIC & TECHNOLOGY RESEARCH VOLUME 8, ISSUE 12, DECEMBER 2019 ISSN 2277-8616

[20] Shaikh K. Alam and and Joanne DeGroat, "A 1.5-V 2.4 Workshop on Circuits and Systems, 2006, pp. 13-16.
GHz Differential CMOS Low Noise Amplifier for Bluetooth
and Wireless LAN Applications," in 2006 IEEE North-East

116
IJSTR©2019
www.ijstr.org