St. Joseph’s Degree College, Kurnool. II BSc.

, III Sem(CO)
Unit-V
Computer Arithmetic and Parallel Processing
Data representation- fixed point, floating point, addition and subtraction, multiplication and division
algorithms. Parallel Processing-Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction
Pipeline.

In computers, the data are stored in memory registers with binary bits 1's and 0's as the computers only
understand binary language. When we enter data in the computer, it is converted into binary and then
processed and used by the CPU in different ways. The memory registers have a specific range and a format
to store data.
We have two major approaches for storing real numbers: Fixed and Floating-Point Representation.
Fixed Point Representation:
In computers, fixed-point representation is a real data type for numbers. Fixed point representation can
convert data into binary form, and then the data is processed, stored, and used by the computer. It has a
fixed number of bits for the integral and fractional parts. For example, if given fixed-point representation is
IIIII.FFF, we can store a minimum value of 00000.001 and a maximum value of 99999.999.
There are three parts of the fixed-point number representation: Sign bit, Integral part, and Fractional
part. The below figure depicts it.

Sign bit:- The fixed-point number representation in binary uses a sign bit. The negative number has a sign
bit 1, while a positive number has a bit 0.
Integral Part:- The integral part in fixed-point numbers is of different lengths at different places. It
depends on the register's size; for an 8-bit register, the integral part is 4 bits.
Fractional part:- The Fractional part is of different lengths at different places. It depends on the registers;
for an 8-bit register, the fractional part is 3 bits.

Example: The number considered is 4.5

Step 1: We will convert the number 4.5 to binary form. 4.5 = 100.1
Step 2: Represent the binary number in fixed-point notation with the following format.

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)
Floating Point Representation
Floating Point representation doesn't reserve any specific number of bits for the integer or fractional parts.
But instead, it reserves certain bits for the number (called the significand or mantissa ) and a fixed number
of bits to say where the decimal place lies(called the exponent).
The computer uses floating-point number representation to convert the input data into binary form.
This binary form number is converted into scientific notation, which is converted into floating-point
representation.

The floating-point representation has two types of notation:

1. Scientific notation: Scientific notation is the method of representing binary numbers into a x be form. It
is further converted into floating-point representation.
For example,
Number = 32625
Number in Scientific Notation = 32.625 x 103
Number in binary form = 1101.101*2101
Here, Mantissa is 1101.101 and Base part is 2101.

2. Normalization notation: It is a special case of scientific notation. Normalized means that we have at
least one non-zero digit after the decimal point.
A floating-point representation has three parts: Sign bit, Exponent Part, and Mantissa. We can see the
below diagram to understand these parts.

Sign bit: The floating-point numbers in binary uses a sign bit. A negative number has a sign bit 1, while a
positive number has a sign bit 0. The sign of any number depends on mantissa, not on exponent.
Mantissa Part: The mantissa part is of different lengths at different places. It depends on registers like for
a 16-bit register, and mantissa part is of 8 bits.
Exponent Part: It is the power of the number. It depends on the size of the register. For example, in the
16-bit register, the exponent part is of 7 bits.
Example: The number considered is 53.5
Step 1: We will convert the number 53.5 to binary form. 53.5 = 110101.1
Step 2: Normalize the number ( base is 2) = (1.101011) * 25.
Step 2: Represent the binary number in floating-point notation with the following format.

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)
Fixed Point Addition and Subtraction
An arithmetic instruction may specify binary or decimal data, and in each case the data may be in fixed-
point or floating-point form. Fixed-point numbers may represent integers or fractions. Arithmetic
operations for binary and decimal data in fixed-point and floating-point representation.
There are three ways of representing negative fixed-point binary numbers:
 signed-magnitude,
 signed-1's complement, or
 signed-2's complement.
Most computers use the signed-2's
complement representation when
performing arithmetic operations with
integers.
We designate the magnitude of the two
numbers by A and B. When the signed
numbers are added or subtracted, we find
that there are eight different conditions to
consider, depending on the sign of the numbers and the operation performed.
 Addition (subtraction) algorithm: when the signs of A and B are Identical (different), add the two
magnitudes and attach the sign of A to the result. When the signs of A and B are different (identical),
compare the magnitudes and subtract the smaller number from the larger. Choose the sign of the result
to be the same as A if A > B or the complement of the sign of A if A < B. If the two magnitudes are
equal, subtract B from A and make the sign of the result positive.
Example 1: Let's add two values, +3 and +2, using the signed magnitude representation.
We represent the given operands as shown below:
+3 = 0 0112
+2 = 0 0102
So we do the addition of the magnitude of both operands.
Mag(+3) + Mag(+2) = 0112 + 0102 = 1012 = Mag(5)
Now the sign of the result will be that of As, Therefore, +3 + (+2) = 0 1012 = +5

Example 2: Let's subtract two values, +3 and +2, using the signed magnitude representation.
We represent the given operands as shown below:
+3 = 0 0112
+2 = 0 0102
Since the magnitude of P > Q,
We get results by +(P-Q).
Mag(Result) = 011 - 010 = 001, Therefore, +3 - (+2) = +(3-2) = +1

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)

 Addition and Subtraction with Signed 2’s Complement Data

Here, the signed-2's complement form of integers is examined, as well as arithmetic techniques for addition
and subtraction. The sign bit is represented by the leftmost bit of a binary number: 0 for positive and 1 for
negative. If the sign bit is 1, the entire number is represented in 2' s complement form.As a result, +33 is
represented as 00100001, and -33 is represented as 11011111. The 2's complement of 00100001 is
11011111, and vice versa.
Example 1: Let's use the 2's complement approach to add two decimal integers of +7 and +4.
The 2's complement representations of +4 and +7 with 5 bits each are shown below.

+710 = 001112
+410 = 001002
The addition of these two numbers is
(+710) + (+410) = 001112+ 001002
(+710) + (+410) = 010112
The final total is positive, as shown by the sign bit
'0'. In the decimal number system, the magnitude of
the sum is 11.
Example 2: Let's use the 2's complement approach
to subtract two decimal integers of +7 and +4.
The subtraction of these two numbers is
(+410) − (+710) = (+410 ) + (−710)
The 2’s complement representations of +4 and -7
with 5 bits each are shown below.
+410 = 001002
−710 = 110012
(+410) + (−710) = 001002 + 110012 = 111012
The final total is negative, as shown by the sign bit '1'. As a result, we may determine the magnitude of the
resultant sum as 3.

 Multiplication Algorithm in Signed Magnitude Representation

Multiplication of two fixed point binary number in signed magnitude representation is done with process
of successive shift and add operation.
 In the multiplication process we are considering
successive bits of the multiplier, least significant bit first.
 If the multiplier bit is 1, the multiplicand is copied down
else 0’s are copied down.
 The numbers copied down in successive lines are shifted
one position to the left from the previous number.

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)
 Finally, numbers are added and their sum form the product.
 The sign of the product is determined from the sign of the multiplicand and multiplier. If they are
alike, sign of the product is positive else negative.

Hardware Implementation
Following components are required for the Hardware Implementation of multiplication algorithm :
1. Registers:
Two Registers B and Q are used to store multiplicand
and multiplier respectively.
Register A is used to store partial product during
multiplication.
Sequence Counter register (SC) is used to store number
of bits in the multiplier.
2. Flip Flop:
To store sign bit of registers we require three flip flops
(A sign, B sign and Q sign).
Flip flop E is used to store carry bit generated during
partial product addition.
3. Complement and Parallel adder:
This hardware unit is used in calculating partial product i.e, perform addition required.
Flowchart of Multiplication:
1. Initially multiplicand is stored in B register and multiplier is stored in Q register.
2. Sign of registers B (Bs) and Q (Qs) are compared using XOR functionality (i.e., if both the signs
are alike, output of XOR operation is 0 unless 1) and
output stored in as (sign of A register).
Note: Initially 0 is assigned to register A and E flip flop.
Sequence counter is initialized with value n, n is the
number of bits in the Multiplier.
3. Now least significant bit of multiplier is checked. If it
is 1 add the content of register A with Multiplicand
(register B) and result is assigned in A register with
carry bit in flip flop E. Content of E A Q is shifted to
right by one position, i.e., content of E is shifted to
most significant bit (MSB) of A and least significant
bit of A is shifted to most significant bit of Q.
4. If Qn = 0, only shift right operation on content of E A
Q is performed in a similar fashion.
5. Content of Sequence counter is decremented by 1.
6. Check the content of Sequence counter (SC), if it is 0,
end the process and the final product is present in register A and Q, else repeat the process.

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)

 Division Algorithm in Signed Magnitude Representation

The Division of two fixed-point binary numbers in the signed-magnitude representation is done by the
cycle of successive compare, shift, and subtract operations.
The binary division is easier than the decimal division because the quotient digit is either 0 or 1. Also, there
is no need to estimate how many times the dividend or partial remainders adjust to the divisor.

Hardware Implementation:
The hardware implementation in the division operation is identical to that required for multiplication and
consists of the following components –
 Here, Registers B is used to store divisor, and the double-length dividend is stored in registers A and
Q
 The information for the relative magnitude is given in E.
 A sequence Counter register (SC) is used to store the number of bits in the dividend.

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)
Parallel Processing
Parallel processing is a term used to denote a large class of techniques that are used to provide
simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer
system. For example, while an instruction is being executed in ALU, the next instruction can be read from
memory. The system may have two or more ALUs and be able to execute multiple instructions at the
same time. The purpose of parallel processing is to speed up computer processing capacity and increases
with parallel processing. But, technological development has reduced hardware costs to the point where
parallel processing methods are economically possible.

Parallel processing is established by distributing the data among the multiple functional units. For example,
the arithmetic, logic, and shift operations can be separated into three units and the operands diverted to
each unit under the supervision of a control unit.

The operation performed in each functional unit is indicated in each block of the diagram.

o The adder and integer multiplier performs the

arithmetic operation with integer numbers.
o The floating-point operations are separated
into three circuits operating in parallel.
o The logic, shift, and increment operations can
be performed concurrently on different data.
All units are independent of each other, so
one number can be shifted while another
number is being incremented.
One classification introduced by M. J. Flynn
considers the organization of a computer system by
the number of instructions and data items that are
manipulated simultaneously. Flynn's classification
divides computers into four major groups as follows:

1. Single Instruction, Single Data (SISD): a single computer containing a control unit, a processor unit,
and a memory unit. Instructions are executed sequentially and may have more than one functional unit, but
these units function under the administration of one control unit.
2. Single Instruction, Multiple Data (SIMD): It represents an organization that includes many processing
units under the supervision of a common control unit. All processors receive the same instruction from the
control unit but operate on different items of data.
3. Multiple Instruction, Single Data (MISD): This organization method includes several processing units
receiving different instructions and operating over a similar data flow. In this structure, the output of one
processor becomes the input of another processor.
4. Multiple Instruction, Multiple Data (MIMD): This computer organization involves the processors in
the parallel system executing different instructions and operating on various data simultaneously. In MIMD

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)
computer organization, each processor operates on a separate program, and you can generate a unique
instruction stream for each program.

Pipelining
The term Pipelining refers to a technique of decomposing a sequential process into sub-operations,
with each sub-operation being executed in a dedicated segment that operates concurrently with all other
segments.

Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows
storing and executing instructions in an orderly process. It is also known as pipeline processing. Pipelining
is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages
and these stages are connected with one another to form a pipe like structure. Instructions enter from one
end and exit from another end. Pipelining increases the overall instruction throughput.

In pipeline system, each segment consists of an input register followed by a combinational circuit. The
register is used to hold data and combinational circuit performs operations on it. The output of
combinational circuit is applied to the input register of the next segment

Finally, it can consider the basic pipeline operates clocked, in other words synchronously. This defines
that each stage gets a new input at the beginning of the clock cycle, each stage has a single clock cycle
available for implementing the needed operations, and each stage produces the result to the next stage by
the starting of the subsequent clock cycle.

Types of Pipelines: There are two types of pipelines. They are:

1. Arithmetic Pipeline
2. Instruction Pipeline

1. Arithmetic Pipeline: Arithmetic Pipelines are mostly used in high-speed computers. They are used to
implement floating-point operations, multiplication of fixed-point numbers, and similar computations
encountered in scientific problems.

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)
To understand the concepts of arithmetic pipeline in a more convenient way, let us consider an example of
a pipeline unit for floating-point addition and subtraction.
The inputs to the floating-point adder pipeline are two normalized floating-point binary numbers defined
as:
X = A * 2a
Y = B * 2b
Where A and B are two fractions that represent the mantissas and a and b are the exponents.
The combined operation of floating-point addition and subtraction can be performed in four segments.
Each segment contains the corresponding sub operation to be performed in the given pipeline. The sub
operations that are shown in the four segments are:
1. Compare the exponents by subtraction.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.
1. Compare exponents by subtraction: The
exponents are compared by subtracting them to
determine their difference. The larger exponent is
chosen as the exponent of the result.
The difference of the exponents, i.e., 3 -
2 = 1 determines how many times the mantissa
associated with the smaller exponent must be
shifted to the right.
2. Align the mantissas: The mantissa associated
with the smaller exponent is shifted according to the
difference of exponents determined in segment one.
X = 0.9504 * 103
Y = 0.8200 * 102
3. Add mantissas: The two mantissas are added in
segment three.
Z = X + Y = 1.0324 * 103
4. Normalize the result: After normalization, the
result is written as:
Z = 0.10324 * 104

2. Instruction Pipeline: Pipeline processing can occur not only in the data stream but in the instruction
stream as well. Most of the digital computers with complex instructions require instruction pipeline to carry
out operations like fetch, decode and execute instructions.

In general, the computer needs to process each instruction with the following sequence of steps.

1. Fetch instruction from memory.

2. Decode the instruction.

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St. Joseph’s Degree College, Kurnool. II BSc., III Sem(CO)
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.

Each step is executed in a particular segment, and there are times when different segments may take
different times to operate on the incoming information. Moreover, there are times when two or more
segments may require memory access at the same time, causing one segment to wait until another is
finished with the memory.

The organization of an instruction pipeline will be more efficient if the instruction cycle is divided into
segments of equal duration. One of the most common examples of this type of organization is a Four-
segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments and makes it as a single
one. For instance, the decoding of the instruction can be combined with the calculation of the effective
address into one segment.

Segment 1: The instruction fetch segment can be implemented using first in, first out (FIFO) buffer.

Segment 2: The instruction fetched from memory is decoded in the second segment, and eventually, the
effective address is calculated in a separate arithmetic circuit.
Segment 3: An operand from memory is fetched in the third segment.
Segment 4: The instructions are finally executed in the last segment of the pipeline organization.

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