Chapter 4 – Input/Output Organization

4.1. After reading the input data, it is necessary to clear the input status flag before
the program begins a new read operation. Otherwise, the same input data would
be read a second time.
4.2. The ASCII code for the numbers 0 to 9 can be obtained by adding $30 to the number.
The values 10 to 15 are represented by the letters A to F, whose ASCII codes can be
obtained by adding $37 to the corresponding binary number.

Assume the output status bit is __in register Status, and the output data register is Output.
Move #10,R0 Use R0 as counter
Move #LOC,R1 Use R1 as pointer
Next Move (R1),R2 Get next byte
Move R2,R3
Shift-right #4,R3 Prepare bits __- __
Call Convert
Move R2,R3 Prepare bits __- __
Call Convert
Move $20,R3 Print space
Call Print
Increment R1
Decrement R0
Branch 0 _ Next Repeat if more bytes left
End

Convert And #0F,R3 Keep only low-order 4 bits

Compare #9,R3
Branch 0 _ Letters Branch if [R3] _9
Or #$30,R3 Convert to ASCII, for values 0 to 9
Branch Print
Letters Add #$37,R3 Convert to ASCII, for values 10 to 15
Print BitTest #4,Status Test output status bit
Branch _0 Print Loop back if equal to 0
Move R3,Output Send character to output register
Return

4.3. 7CA4, 7DA4, 7EA4, 7FA4.

4.4. A subroutine is called by a program instruction to perform a function needed by the

calling program. An interrupt-service routine is initiated by an event such as an input
operation or a hardware error. The function it performs may not be at

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 all related to the program being executed at the time of interruption. Hence, it
must not affect any of the data or status information relating to that program.
4.5. If execution of the interrupted instruction is to be completed after return from
interrupt, a large amount of information needs to be saved. This includes the
contents of any temporary registers, intermediate results, etc. An alternative is
to abort the interrupted instruction and start its execution from the beginning
after return from interrupt. In this case, the results of an instruction must not be
stored in registers or memory locations until it is guaranteed that execution of
the instruction will be completed without interruption.
4.6. (a) Interrupts should be enabled, except when C is being serviced. The nesting
rules can be enforced by manipulating the interrupt-enable flags in the
interfaces of A and B.
(b) A and B should be connected to INTR , and C to INTR. When an interrupt
request is received from either A or B, interrupts from the other device will be
automatically disabled until the request has been serviced. However, interrupt
requests from C will always be accepted.
4.7. Interrupts are disabled before the interrupt-service routine is entered. Once de-vice _turns
off its interrupt request, interrupts may be safely enabled in the pro-
_turns off its interrupt request when it receives the interrupt acknowledge signal,
cessor. If the interface circuit of device
interrupts may be enabled at the be- _ ginning of the interrupt-service routine of device _.
Otherwise, interrupts may be enabled only after the instruction that causes device _to turn off its interrupt
_
request has been executed.
4.8. Yes, because other devices may keep the interrupt request line asserted.
4.9. The control program includes an interrupt-service routine, INPUT, which reads
the input characters. Transfer of control among various programs takes place as
shown in the diagram below.

CONTROL

CALL INTERRUPT
RET
RTI
INT
PROG INPUT

RTI

A number of status variables are required to coordinate the functions of PROG

and INPUT, as follows.

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 BLK-FULL: A binary variable, indicating whether a block is full and ready
for processing.
IN-COUNT: Number of characters read.
IN-POINTER: Points at the location where the next input character is to be
stored.
PROG-BLK: Points at the location of the block to be processed by PROG.

Two memory buffers are needed, each capable of storing a block of data. Let
BLK(0) and BLK(1) be the addresses of the two memory buffers. The structure
of CONTROL and INPUT can be described as follows.

CONTROL BLK-FULL := false

IN-POINTER := BLK( )_
IN-COUNT := 0
Enable interrupts
:= 0
_Loop
Wait for BLK-FULL
If not last block then
BLK-FULL := false Prepare to read the next block
IN-POINTER := BLK( _____)
IN-COUNT := 0
Enable interrupts _
_
PROG-BLK := BLK( ) Process the block just read
Call PROG
If last block then exit

End Loop ___________

Interrupt-service routine
INPUT: Store input character and increment IN-COUNT and IN-POINTER If IN-
COUNT = N Then
disable interrupts from device
BLK-FULL := true _
Return from interrupt

4.10. Correction: In the last paragraph, change “equivalent value” to “equivalent

condition”.
Assume that the interface registers for each video terminal are the same as in
Figure 4.3. A list of device addresses is stored in the memory, starting at DE-
VICES, where the address given in the list, DEVADRS, is that of DATAIN.
_
The pointers to data areas, PNTR , are also stored in a list, starting at
PNTRS.
Note that depending on the processor, several instructions may be needed to
perform the function of one of the instructions used below.

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 POLL Move #20,R1 Use R1 as device counter, _
LOOP Move DEVICES(R1),R2 Get address of device _
BitTest #0,2(R2) Test input status of a device
Branch __0 NXTDV Skip read operation if not ready
Move PNTRS(R1),R3 Get pointer to data for device _
MoveByte (R2),(R3)+ Get and store input character
Move R3,PNTRS(R1) Update pointer in memory
NXTDV Decrement R1
Branch 0 _ LOOP
Return

INTERRUPT Same as POLL, except that it returns once a character

is read. If several devices are ready at the same time,
the routine will be entered several times in succession.

In case a, POLL must be executed at least 100 times per second. Thus _______
_!_"_ ms.
The equivalent condition for case b can be obtained by considering the case when
all 20 terminals become ready at the same time. The time required for interrupt
servicing must be less than the inter-character delay. That is, #$_&%'#(_(_)%*___,+.-0/
, or 34/5#(6$char/s_879._$_(_
The _21(3time spent servicing the terminals in each second is given by:
Case a: Time _:___(_;%*<$_ns(__;%=?<(s__A@"_,+>-
Case b: Time _B#$_C%EDC%*#$_(_;%=_"_ns,+>-F%G___(_F__H(_$_ID
Case b is a better strategy for D*/5._
The reader may repeat this problem using a slightly more complete model in which the
L
polling time, , for caseM is a function of the number of terminals. For example, assume
that L increases by 0.5 @s for each terminal that is ready,
that is, LN_O#$_)P_#.$_IDQ%Q_
4.11. (a) Read the interrupt vector number from the device (1 transfer).
Save PC and SR (3 transfers on a 16-bit bus).
Read the interrupt vector (2 transfers) and load it in the PC.
(b) The 68000 instruction requiring the maximum number of memory
transfers is:
MOVEM.L D0-D7/A0-A7,LOC.L
where LOC.L is a 32-bit absolute address. Four memory transfers are
needed to read the instruction, followed by 2 transfers for each register,
for a total of 36.
(c) 36 for completion of current instruction plus 6 for interrupt handling, for a
total of 42.
4.12. (a) RTSVUXWE_&__RTSVUAYE_
RTSVUXWV#;__RTSVUAYV#)ZRTSVUAYE_

RTSVUXWV[;__RTSVUAYV[)ZRTSVUAYE_BRTS0UAY
\#

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 (b) See logic equations in part a.
(c) Yes.
(d) In the circuit below, DECIDE is used to lock interrupt requests. The pro-
cessor should set the interrupt acknowledge signal, INTA, after DECIDE
returns to zero. This will cause the highest priority request to be acknowl-
_ edged. Note that latches are placed at the inputs of the priority circuit. _
They could be placed at the outputs, but the circuit would be less reliable
when interrupts change at about the same time as arbitration is taking place
(races may occur).

INTR1

f
a INTA1

INTR2

_ h
b INTA2

INTR3

] ge
DECIDE `

c INTA3

Reset ^ INTA d

4.13. In the circuit given below, register A records which device was given a grant most
recently. Only one of its outputs is equal to 1 at any given time, identifying the highest-
priority line. The falling edge of DECIDE records the results of the current arbitration
cycle in A and at the same time records new requests in register B. This prevents
requests that arrive later from changing the grant.
The circuit requires careful initialization, because one and only one output of
register A must be equal to 1. This output determines the highest-priority line
during a given arbitration cycle. For example, if the LSB of A is equal to 1, point
E2 will be equal to 0, giving REQ2 the highest priority.
5
_ _

DECIDE A
E1
GR1
REQ1

E2
GR2
REQ2

E3
GR3
REQ3

E4
GR4
REQ4

DECIDE

4.14. The truth table for a priority encoder is given below.

1 2 3 4 5 6 7 IPL IPL IPL _

0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1
x 1 0 0 0 0 0 0 1 0
x x 1 0 0 0 0 0 1 1
x x x 1 0 0 0 1 0 0
x x x x 1 0 0 1 0 1
x x x x x 1 0 1 1 0
x x x x x x 1 1 1 1

A possible implementation for this priority circuit is as follows:

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 _ _
RTikjl mP___ npo0PGnpqVPn_n

_ _ut
t
RTikj__qnP_nP RTirjpsn PGn

_ _ _
4.15. Assume
RTikjthatthe__interfacenP_onZ"nregistersqPRTirjareusnthePGnsameZ"nas in
Figure 4.3 and that the characters to be printed are stored in the memory.

* Program A (MAIN) points to the character string and calls DSPLY twice
MAIN MOVE.L #ISR,VECTOR Initialize interrupt vector
ORI.B #$80,STATUS Enable interrupts from device
MOVE #$2300,SR Set interrupt mask to 3
MOVEA.L #CHARS,A0 Set pointer to character list
BSR DSPLY
MOVEA.L #CHARS,A0
BSR DSPLY
END MAIN
*Subroutine DSPLY prints the character string pointed to by A0
*The last character in the string must be the NULL character
DSPLY ...
RTS
* Program B, the interrupt-service routine, points at the number string and calls DSPLY
ISR MOVEM.L A0,_(A7) Save registers used
MOVE.L NEWLINE,A0 Start a new line
BSR DSPLY
MOVEA.L #NMBRS,A0 Point to the number string
BSR DSPLY
MOVEM.L (A7)+,A0 Restore registers
RTE
* Characters and numbers to be displayed
CHARS CC /AB . . . Z/
NEWLINE CB $0D, $0A, 0 Codes for CR, LF and Null
NMBRS CB $0D, $0A
CC /01 . . . 901 . . . 901 . . . 9/
CB $0D, $0A, 0

When ISR is entered, the interrupt mask in SR is automatically set to 4 by the

hardware. To allow interrupt nesting, the mask must be set to 3 at the
beginning of ISR.

4.16. Modify subroutine DSPLY in Problem 4.15 to keep count of the number of char-
acters printed in register D1. Before ISR returns, it should call RESTORE, which
sends a number of space characters (ASCII code 20 vq
)equal to the count in D1.

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 DSPLY ...
MOVE #$2400,SR Disable keyboard interrupts
MOVEB D0,DATAOUT Print character
ADDQ #1,D1
MOVE #$2300,SR Enable keyboard interrupts
...
RESTORE MOVE.L D1,D2
BR TEST
LOOP BTST #1,STATUS
BEQ LOOP
MOVEB #$20,DATAOUT
TEST DBRA D2,LOOP
RTS

Note that interrupts are disabled in DSPLY before printing a character to

ensure that no further interrupts are accepted until the count is updated.
4.17. The debugger can use the trace interrupt to execute the saved instruction then
regain control. The debugger puts the saved instruction at the correct address,
enables trace interrupts and returns. The instruction will be executed. Then, a
second interruption will occur, and the debugger begins execution again. The
de-bugger can now remove the program instruction, reinstall the breakpoint,
disable trace interrupts, then return to resume program execution.
4.18. (a) The return address, which is in register R14 svc, is PC+4, where PC is the
address of the SWI instruction.
LDR R2,[R14,#-4] Get SWI instruction
BIC R2,R2,#&FFFFFF00 Clear high-order bits
(b) Assume that the low-order 8 bits in SWI have the values 1, 2, 3, ... to
request services number 1, 2, 3, etc. Use register R3 to point to a table of
addresses of the corresponding routines, at addresses [R3]+4, [R3]+8,
respectively.
ADR R3,EntryTable Get the table's address
LDR R15,[R3,R2,LSL #2] Load starting address of routine

4.19. Each device pulls the line down (closes a switch to ground) when it is not
ready. It opens the switch when it is ready. Thus, the line will be high when all
devices are ready.
4.20. The request from one device may be masked by the other, because the
processor may see only one edge.

INTR

REQ1

REQ2

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4.21. Assume that when BR becomes active, the processor asserts BG1 and keeps it
asserted until BR is negated.

Dev. 3 asserts BR
BR1

BG1

BG3

BBSY
Processor Dev. 1 Dev. 3

4.22. (a) Device 2 requests the bus and receives a grant. Before it releases the bus,
device 1 also asserts BR. When device 2 is finished nothing will happen. BR
and BG1 remain active, but since device 1 does not see a transition on BG1 it
cannot become the bus master.
(b) No device may assert BR if its BG input is active.
4.23. For better clarity, change BR to w_Yand use an inverter with delay

xptogenerate
BG1.

BR3
d1
BG1
2d
BG3
d
BG4
d2

Assuming device 3 asserts BG4 shortly after it drops the bus request (delay xy), a spurious pulse of
width z{_|xp}PG[8x~willappear__xyon BG4.
4.24. Refer to the timing diagram in Problem 4.23. Assume that both BR1 and BR5
are activated during the delay period xy
. Input BG1 will become active and
at the same time the pulse on BG4 will travel to BG5. Thus, both devices will
receive a bus grant at the same time.
9
 4.25. A state machine for the required circuit is given in the figure below. An output
called ACK has been added, indicating when the device may use the bus. Note
that the restriction in Solution 4.22b above is observed (state B).
BUSREQ, BGi, BBSY/BR, BG(i+1), BBSY, ACK
00x/0000 10x/1000

x0x/0000 10x/0000

B A C
x1x/0100 x1x/0100

110/1000
0xx/0000

1xx/0011
_ _

4.26. The priority register in the circuit below contains 1111 for the highest priority
device and 0000 for the lowest.

Priority StartArbitration
register
o.c.
ARB3*

o.c.
ARB2*

o.c.
ARB1*

o.c.
ARB0*

Winner

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 4.27. A larger distance means longer delay for the signals traveling between the pro-
€_,_y_E9and
cessor and the input device. Primarily, this means that 9 9oX__E
_and __G_may
_ _
will increase. Since longer distances may also mean larger skew, the intervals
have to be increased to cover worst-case differences in

propagation_= delay.
In the case of Figure 4.24, the clock period must be increased to accommodate
the maximum propagation delay.
4.28. A possible circuit is given below.

Address Decoder
A
15

A
9 ƒ
A8
Device Selected
A5

A4

A3
A
0

†
9 9
Read/Write
Enable V
cc
Clock Sensors
D
7

D0 „ ‚
Tri-state
Drivers
11
_ _

4.29. Assume that the display has the bus address FE40. The circuit below sets the Load signal
to 0 during the second half of the write cycle. The rising edge at the end of the clock
period will load the data into the display register.

D
3
Š

D
0 ˆ
A
15
7-segment

‰ 4-bit Display
A Register
9
A
6

A
8,7,5,4
Load

A3
A0

Read/Write ‡T‡T‡T‡
Clock

4.30. Generate SIN ‹ŒŽ_’‘ inthesame way as Load in Problem P4.29. This signal
should load the data on D6 into an Interrupt-Enable flip-flop, IntEn. The interrupt re-
quest can now be generated as RTSVUAY“_”8RTS:Z_RT•p–9—k•.
4.31. Hardware organization and a state diagram for the memory interface circuit are given
below.

Tri-state
Memory Drivers
MyAddress

MyAddress
Read Data
A C

Read Enable

Read Address
D Enable Control
Slave-ready Clock
Slave-ready

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4.32. (a) Once the memory receives the address and data, the bus is no longer
needed. Operations involving other devices can proceed.
(b) The bus protocol may be designed such that no response is needed for write
operations, provided that arrival of the address and data in the first clock cycle is
guaranteed. The main precaution that must be taken is that the memory interface
cannot respond to other requests until it has completed the write operation. Thus, a
subsequent read or write operation may encounter additional delay.
Note that without a response signal the processor is not informed if the
memory does not receive the data for any reason. Also, we have assumed a
simple uni-processor environment. For a discussion of the constraints in
parallel-processing systems, see Chapter 12.

4.33. In the case of Figure 4.24, the lack of response will not be detected and pro-
cessing will continue, leading to erroneous results. For this reason, a response
signal from the device should be provided, even though it is not essential for
bus operation. The schemes of both Figures 4.25 and 4.26 provide a response
signal, Slave-ready. No response would cause the bus to hang up. Thus, after
some time-out period the processor should abort the transaction and begin
executing an appropriate bus error exception routine.

4.34. The device may contain a buffer to hold the address value if it requires
additional time to decode it or to access the requested data. In this case, the
address may be removed from the bus after the first cycle.

4.35. Minimum clock period = 4+5+6+10+3 = 28

ns Maximum clock speed = 35.7 MHz
These calculations assume no clock skew between the sender and the receiver.
4.36. y}____bus skew = 4 ns
= propagation delay + address decoding + access time 9

0__=1yto5 + 6 + 5 to 10 = 12 to 21 ns
_ = propagation delay + skew + setup time  __9= 1
to 5 + 4 + 3 = 8 to 12 ns
_= propagation delay = 1 to 5 ns
9o0Minimum__cycle = 4 + 12 + 8 + 1 = 25 ns
Maximum cycle = 4 + 21 + 12 + 5 = 42 ns

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