Shri VaishnavSM Institute of Technology & Science, Indore

Discipline Department of Electrical & Electronics Engineering Pages: 1/6

Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

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EXPERIMENT NO. – 05

1.0 Aim: -
To construct Adders and Subtractors.

2.0 Objectives: -
2.1 To construct the circuit of half adder.
2.2 To construct the circuit of half subtractor.
2.3 To construct the circuit of full adder.
2.4 To construct the circuit of full subtractor.

3.0 Pre – Requisites: -

3.1 Knowledge of Binary Number System.
3.2 Knowledge of pin diagrams of all logic gates.
3.3 Knowledge of truth table of all logic gates

4.0 Apparatus Requirements: -

4.1 DC Power Supply (5 Volt)
4.2 IC’s of logic gates (AND, OR, X-OR, and NOT)
4.3 Breadboard
4.4 SPDT Switches
4.5 LED’s
4.6 Resistors
4.7 Connecting Wires
5.0 Theory: -
The circuit which is capable to adds or subtracts binary numbers or data is called
digital (or binary) Adder or Subtractor. These circuits made with the help of logic gates.
5.1 Adder:
In digital electronics an adder is a logic circuit which implement for addition of binary
numbers. In many computers and other types of processors, adders are used to calculate
addresses, similar operations and table indices in the arithmetic logic unit (ALU).
There are two types of adders:
1) Half Adder
2) Full Adder

Study Group. Digital Electronics Modified by: Nitin Saravagi

Created by: Nitin Saravagi Date of Creation: 10/11/2022 Date of Modification:
Rev. No. EC/DE/01/2022 Approved by: HOD
 Shri VaishnavSM Institute of Technology & Science, Indore
Discipline Department of Electrical & Electronics Engineering Pages: 2/6
Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

5.1.1 Half Adder:

The half adder adds two binary digits called as augend and addend (Input A and Input
B) and produces two outputs as sum and carry (S and CO). It means half adder circuits can
add only two digits and give the results according the inputs. The block diagram of a half
adder is given below:

Input A Sum (S)

Half Adder
Input B Carry (CO)

Figure 5.1 Block Diagram of Half Adder

Consider the operation of adding two binary numbers, which is one of the
fundamental tasks performed by a digital computer. The four basic addition operations two
single bit binary numbers are:

Figure 5.2 Additions of two single bits

Figure 5.3 Circuit diagram of Half Adder

In the first three operations, each binary addition gives sum as one bit, i.e., either 0 or 1.
But for the fourth addition operation (where the inputs are 1 and 1), the result consists of
two binary digits. Here, the lower significant bit is called as the ‘Sum Bit’, while the higher
significant bit is called as the ‘Carry Bit’.
 Shri VaishnavSM Institute of Technology & Science, Indore
Discipline Department of Electrical & Electronics Engineering Pages: 3/6
Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

B A Carry (CO) Sum (S)

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Table 5.1 Truth Table of Half Adder

If we observe the ‘Sum’ values in the above truth table, it resembles an Ex-OR Gate.
Similarly, the values for ‘Carry’ in the above truth table resembles an AND Gate.
So, to properly implement a Half Adder, we need two Logic Gates: an XOR gate for
‘Sum’ Output and an AND gate for ‘Carry’ output. The following figure shows the Logic
Diagram of a Half Adder.

Half adder is mainly used for addition of augend and addend of first order binary
numbers i.e., 1-bit binary numbers. We cannot add binary numbers with more than one bit
as the Half Adder cannot include the ‘Carry’ information from the previous sum.
Due to this limitation, Half Adder is practically not used in many applications,
especially in multi-digit addition. In such applications, carry of the previous digit addition
must be added along with two bits; hence it is a three bit addition.
5.1.2 Full Adder:
A Full Adder is a combinational logic circuit which performs addition on three bits and
produces two outputs: a Sum and a Carry. As we have seen that the Half Adder cannot
respond to three inputs and hence the full adder is used to add three digits at a time. The
block diagram of a Full Adder is as below:

Input A Sum (S)

Input B Full Adder

Input C Carry (CO)

Figure 5.4 Block Diagram of Full Adder

Figure 5.5 Circuit Diagram of Full Adder

 Shri VaishnavSM Institute of Technology & Science, Indore
Discipline Department of Electrical & Electronics Engineering Pages: 4/6
Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

C B A Carry (CO) Sum (S)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Table 5.2 Truth Table of Full Adder

From the above truth table, we can obtain the Boolean Expressions for both the Sum
and Carry Outputs. Using those expressions, we can build the logic circuits for Full Adder.
But by simplifying the equations further, we can derive at a point that a Full Adder can be
easily implemented using two Half Adders and an OR Gate.

Input C Sum (S)

Half Adder
Carry (CO2)
Input B CO

Half Adder
Carry (CO1)
Input A

Figure 5.5 Block Diagram of Full Adder using Two Half Adder
5.2 Subtractor:
Another basic arithmetic operation to be performed by Digital Computers is the
Subtraction. Subtraction is a mathematical operation in which one integer number is
deducted from another to obtain the equivalent quantity. The number from which other
number is to be deducted is called as ‘Minuend’ and the number subtracted from the
minuend is called ‘Subtrahend’.
A subtractor can be designed using the same approach as that of an adder with a
negative input on AND gate. So, like adder, subtractor also has two types:
1) Half Subtractor
2) Full Subtractor
5.2.1 Half Subtractor:
The half subtractor is a combinational circuit which is used to perform subtraction of
two bits. It has two inputs, the minuend (A) and subtrahend (B) and two outputs the
difference D and borrows out B out. Borrows out signal is set when the subtractor needs to
 Shri VaishnavSM Institute of Technology & Science, Indore
Discipline Department of Electrical & Electronics Engineering Pages: 5/6
Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

borrow from the next digit in a multi digit subtraction. That is, B out = 1 when A < B. Since A
and B are bits, Bout = 1 if and only if A = 0 and B = 1. An important point worth mentioning is
that the half subtractor diagram aside implements A - B and not B - A since Bout on the
diagram is given by Bout = NOT A . B.

Figure 5.6 Circuit Diagram of Half Subtractor

A B Borrow Difference (D)

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

Table 5.3 Truth Table of Half Subtractor

5.2.2 Full Subtractor:

A full subtractor is a combinational circuit that performs subtraction of two bits, one is
minuend and other is subtrahend, taking into account borrow of the previous adjacent lower
minuend bit. This circuit has three inputs and two outputs. The three inputs A, B and C,
denote the minuend, subtrahend, and previous borrow, respectively. The two outputs, D
and Bout represent the difference and output borrows, respectively. Generally, the full
subtractor is one of the most used and essential combinational logic circuits

Figure 5.7 Circuit Diagram of Full Subtractor

 Shri VaishnavSM Institute of Technology & Science, Indore
Discipline Department of Electrical & Electronics Engineering Pages: 6/6
Subject Name: Digital Logic and Circuit Design Sub. Code: BTEC104 Experiment No.: 04

A B C Borrow Difference (D)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Table 5.4 Truth Table of Full Subtractor

6.0 Questions to Be Answered: -

6.1. Explain the following terms:
a) Combinational logic circuit
b) Sequential logic circuit
c) Parallel Adder
d) Serial Adder
6.2. What is the disadvantage of realizing a full adder using two half adders? Explain in brief.

7.0 Investigations Expected:

7.1. Answers to the questions asked.
7.2. Exploring inferences and conclusion.

8.0 Students should submit in their own handwriting: -

8.1. Truth table.
8.2. Answer of the given questions.

References: -
 M. Morris Mano; "Digital Logic & Computer Design"; PHI.