ALP to Check if a Number is Even or Odd

MOV AL, [NUM] ; Load the number into AL

TEST AL, 01H ; Test the LSB (Least Significant Bit)
JZ EVEN ; If ZF=1, the number is even
MOV DX, "ODD" ; Load "ODD" to print/display
JMP EXIT
EVEN:
MOV DX, "EVEN" ; Load "EVEN" to print/display
EXIT:

ALP to Find 1’s Complement of a Number

MOV AL, [NUM] ; Load the number into AL
NOT AL ; Perform 1’s complement operation
MOV [RESULT], AL ; Store the result

ALP to Perform 2 8-bit BCD Addition

MOV AL, [NUM1] ; Load first BCD number
ADD AL, [NUM2] ; Add second BCD number
DAA ; Decimal Adjust after Addition
MOV [RESULT], AL ; Store the result

ALP to Find Smallest Value in an Array

LEA SI, ARRAY ; Load starting address of array
MOV AL, [SI] ; Assume first element is smallest
MOV CX, LENGTH ; Load number of elements
DEC CX
NEXT:
INC SI ; Move to the next element
CMP AL, [SI] ; Compare with current smallest
JBE SKIP ; If AL <= [SI], skip
MOV AL, [SI] ; Update AL with new smallest
SKIP:
LOOP NEXT ; Repeat for remaining elements
MOV [RESULT], AL ; Store smallest value

ALP to Find the Length of a String

LEA SI, STRING ; Load address of the string
MOV CX, 0 ; Initialize counter to 0
NEXT:
MOV AL, [SI] ; Load a character
CMP AL, 0 ; Check for null terminator
JE END ; If null, end
INC CX ; Increment counter
INC SI ; Move to the next character
JMP NEXT
END:
MOV [RESULT], CX ; Store the length
ALP to Find Sum of Digits
MOV AL, [NUM] ; Load the number
MOV AH, 00H ; Clear AH for division
MOV CX, 00H ; Initialize sum
NEXT:
MOV DL, 10
DIV DL ; Divide by 10 (AL = Quotient, AH = Remainder)
ADD CX, AH ; Add remainder to sum
CMP AL, 0 ; Check if quotient is zero
JNE NEXT ; Repeat if not zero
MOV [RESULT], CX ; Store the sum

ALP to Find Factorial of a Number

MOV CX, [NUM] ; Load the number as a counter
MOV AX, 01 ; Initialize AX to 1 (result)
FACT_LOOP:
MUL CX ; Multiply AX by CX
DEC CX ; Decrement counter
JNZ FACT_LOOP ; Repeat until CX = 0
MOV [RESULT], AX ; Store the factorial result

ALP to Transfer a Block to Another Array

LEA SI, SRC ; Load source array address
LEA DI, DEST ; Load destination array address
MOV CX, LENGTH ; Load number of elements
REP MOVSB ; Repeat moving bytes from SI to DI

Write an assembly language program to find the largest number from an array of a 10
numbers. Assume suitable data.
DATA SEGMENT
ARR DB 1,4,2,3,9,8,6,7,5,10
LN DW 10
L DB ?
DATA ENDS
CODE SEGMENT
ASSUME DS:DATA, CS:CODE
START:
MOV AX,DATA
MOV DS,AX
LEA SI,ARR
MOV AL,ARR[SI]
MOV L,AL
MOV CX,LN
REPEAT: MOV AL,ARR[SI]
CMP L,AL
JG NOCHANGE (or JNC NOCHANGE) MOV L,AL
NOCHANGE: INC SI LOOP REPEAT MOV AH,4CH INT 21H CODE ENDS
END START
Pipelining allows the CPU to fetch the next instruction while executing the current
one. In the 8086 microprocessor, the Bus Interface Unit (BIU) fetches up to 6
instruction bytes in advance and stores them in a FIFO queue for the Execution Unit
(EU). The EU decodes and executes instructions from this queue, speeding up
operations by reducing memory access delays. For branch instructions, the queue is
cleared, and new instructions are fetched from the branch target address.

Physical Address Generation:

The 8086 uses segmented memory with 20-bit physical addresses. The physical
address is formed by shifting the 16-bit segment address left by 4 bits (adding a
nibble of 0) and adding the 16-bit offset

Draw minimum mode configuration of 8086 and explain the function of any four
control signals
INTA: Indicates the processor has accepted a non-vectored INTR interrupt.
ALE: Address Latch Enable signal used to demultiplex address and data:

● ALE = 1: AD0-AD15 → A0-A15

● ALE = 0: AD0-AD15 → D0-D15

DEN: Data Enable signal for output enable of 8286 in minimum mode, active LOW during
memory, I/O, and INTA cycles.
DT/R: Controls data flow direction: 1: Data transmitted from 8086, 0: Data received by 8086.
M/IO: Distinguishes memory (M/IO=1) and I/O (M/IO=0) transfers.
WR: Indicates a write operation (memory or I/O) based on M/IO signal.
HOLD: Request by peripheral to control address/data lines.
HLDA: Acknowledge from the microprocessor to grant control of address/data lines.

List the addressing modes of 8086 and describe them with an example.
Immediate Addressing: Data is part of the instruction, used as the source operand. Ex: MOV
CL, 03H; ADD AX, 1234H.
Register Addressing: Operands are registers (8-bit: AL, AH, etc.; 16-bit: AX, BX, etc.). Ex:
MOV AL, BL; ADD CL, DL; MOV DS, AX.
Memory Addressing:

● Direct: Offset address in the instruction. Ex: MOV AL, [2000H]; MOV [1020],
5050H.
● Indirect: EA is calculated.
○ Register Indirect: EA = [BX, SI, DI]. Ex: MOV [DI], 1234H; MOV AX,
[BX].
○ Based + Displacement: EA = BX/BP + displacement. Ex: MOV AX,
[BX+300H].
○ Indexed: EA = SI/DI + displacement. Ex: MOV [DI+2345H], 1234H.
○ Based Indexed: EA = BX/BP + SI/DI. Ex: MOV [BX+DI], 1234H.
○ Based Indexed + Displacement: EA = BX/BP + SI/DI + displacement. Ex: MOV
[DI+BX+37H], AX.

I/O Port Addressing:

● Direct: Fixed port address in instruction. Ex: OUT 06H, AL.

● Indirect: Port address in DX. Ex: IN AL, DX.

Implied Addressing: Operand implied by the instruction. Ex: CLC; DAA.

Draw architectural block diagram of 8086 microprocessor and describe the function of
each block.

Intel 8086 Architecture

Intel 8086 is a 16-bit processor with a 16-bit data bus and a 20-bit address bus. It has two
units:

1. BIU (Bus Interface Unit):

○ Memory Interface: Generates 20-bit physical addresses for ROM/RAM.
○ Instruction Queue: Stores 6 pre-fetched instruction bytes for faster
execution.
○ Segment Registers: Four 16-bit registers: CS (Code), SS (Stack), DS
(Data), and ES (Extra). CS is used with IP (Instruction Pointer).
○ Adder: Combines 16-bit segment and offset addresses for 20-bit addressing.
2. EU (Execution Unit):
○ Control Unit: Decodes instructions from the queue.
○ ALU: Performs 16-bit arithmetic and logic operations.
○ General Purpose Registers: AX, BX, CX, DX, SP, BP, SI, DI. AX splits into
AL (8-bit) and AH (8-bit).
○ Flags: 16-bit register with 9 flags: OF, DF, IF, TF, SF, ZF, AF, PF, CF.

Describe the working principal of successive approximation ADC.

The converter compares analog voltage (Va) with reference voltage (Vi) using a comparator.
 ● Operation:
1. If Va = Vi, no conversion is needed, and digital output matches Vi.
2. If Va ≠ Vi, Vi is adjusted:
■ Va > Vi: Vi increases by 50%.
■ Va < Vi: Vi decreases by 50%.
3. The updated Vi is converted to analog using a DAC, and the process repeats
until Va = Vi.
● Conversion Process:
1. SAR is cleared, and DAC output starts at 0V.
2. MSB is set, and VDAC is compared with Vin:
■ If VDAC < Vin, the bit stays set.
■ If VDAC > Vin, the bit resets.
3. Steps repeat for all bits (D6 to D0).
4. Final SAR output matches the analog input, and an end of conversion signal
is sent.

Compare the following (Any three points) i) Volatile with Non-volatile memory
Definition: Volatile Memory requires electrical power to retain information. Non-Volatile
Memory retains information without power.

Classification: Volatile Memory includes all RAMs. Non-Volatile Memory includes ROMs,
EPROM, and magnetic memories.

Effect of Power: Volatile Memory loses information when power is off. Non-Volatile Memory
retains information regardless of power.

Applications: Volatile Memory is used for temporary storage. Non-Volatile Memory is used
for permanent storage.

ii) SRAM with DRAM memory

Circuit Configuration: SRAM uses flip-flops; DRAM uses one MOSFET and a capacitor per
cell.

Bits Stored: SRAM stores bits as voltage; DRAM stores bits as charges.

Components per Cell: SRAM requires more; DRAM requires less.

Storage Capacity: SRAM has less; DRAM has more.

Refreshing: SRAM doesn’t require refreshing; DRAM does.

Cost: SRAM is expensive; DRAM is cheaper.

State and explain De-Morgan’s theorems.

First Theorem (A⋅B‾=A‾+B‾\overline{A \cdot B} = \overline{A} + \

overline{B}A⋅B=A+B):

● If AAA and BBB are both 1, then A⋅B=1A \cdot B = 1A⋅B=1, and its
complement is 0. The sum of the complements of AAA and BBB is also 0.
● If either AAA or BBB is 0, then A⋅B=0A \cdot B = 0A⋅B=0, and its
complement is 1. The sum of the complements of AAA and BBB is also 1.
Second Theorem (A+B‾=A‾⋅B‾\overline{A + B} = \overline{A} \cdot \
overline{B}A+B=A⋅B):

● If AAA or BBB is 1, then A+B=1A + B = 1A+B=1, and its complement is 0. The

product of the complements of AAA and BBB is also 0.
● If both AAA and BBB are 0, then A+B=0A + B = 0A+B=0, and its complement is 1.
The product of the complements of AAA and BBB is also 1.

working of JK flip-flop

The JK flip-flop is an improved version of the SR flip-flop, resolving the invalid condition
when both inputs are high (S = R = 1) by introducing two inputs, J and K, along with a clock
input. It uses cross-coupling between Q and Q' to interlock the inputs, allowing the flip-flop to
toggle its state when J = K = 1. The operation is synchronized with the clock, enabling four
states: no change (J = 0, K = 0), reset (J = 0, K = 1), set (J = 1, K = 0), and toggle (J = 1, K =
1). This design ensures stable and valid output for all input combinations.