ISAs & RISC-V

CIS 5710
Computer Organization & Design
ISAs & RISC-V
App App App • ISA recap
System software
• RISC-V ISA overview
Mem CPU I/O • RISC-V assembly

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Review: Execution Model
App App App • A computer is a finite state machine
System software • Registers (few of them, but fast)
• Memory (lots of it, but slower)
Mem CPU I/O
• Program Counter (next insn to execute)
• A computer executes instructions
Fetch
• Fetches next instruction from memory
Decode • Decodes it (figure out what it does)
Read Inputs • Reads its inputs (registers & memory)
Execute
• Executes it (adds, multiply, etc.)
Write Output
Next Insn • Write its outputs (registers & memory)
• Next insn (adjust the PC)
Instruction ® Insn • Program is just data in memory
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Review: ISA
App App App • HW/SW interface is ISA
System software (instruction set architecture)
• A “contract” between HW and SW
Mem CPU I/O
• Encourages compatibility, allows
HW/SW to evolve independently
• Functional definition of HW storage
locations & operations
• Storage locations: registers, memory
• Operations: add, multiply, branch,
load, store, etc.
• Precise description of how to invoke &
access them
• what bits the hardware understands
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Review: Assembly vs machine code
• Assembly language
• human-readable(-ish) version of machine code
• Machine code
• the binary format the processor understands
• assembler translates assembly language to machine code

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RISC-V

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RISC-V History
• Started in 2010 at UC Berkeley
• led by Krste Asanović & David Patterson
• an open source ISA
• ground-breaking model
• all other ISAs are commercial and require licensing
• anyone can build an RV chip without a license
• interesting open-source designs exist
• SiFive fabless chip designer founded in 2015
• privately held, valued >$2B
• Vibrant ecosystem
• significant traction in embedded market segments

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What is a 64-bit ISA?
• an ISA with 64-bit pointers
• often registers are also 64b in size (to hold pointers)
• address space is 64 bits (later)
• does not describe:
• the number of registers
• insn size
• amount of memory
• all of the data widths insns may process

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RV Extensibility
• RV has two base ISAs
• RV32I and RV64I
• There are many (optional) extensions
• RV32I
• 32-bit with only the 47 base integer instructions
• RV64IMA
• 64-bit with base + multiply/divide + atomics
• RV64G
• 64-bit with enough support to run a full OS
• We will build a RV32IM core
• 32-bit base + multiply/divide insns
• ignore a few insns for cycle/time/insn counting
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RV32IM, your new BFF
• program counter, 32b
• 32 registers, 32b each
• called x0-x31
• x0 always has the value zero
• each register has an alias, e.g., zero, sp, a0
• insns are fixed 32b in size
• RV also has compressed 16b insns with the C extension
• you’ll need to refer to the RV ISA spec
• Volume 1: Unprivileged Specification
• includes nice commentary on design decisions
• our ISA reference sheet has the basics

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RV has no NOT insn!
• How can we perform NOT?
addi rd,rs1,imm12 rd = rs1 + se(imm12)
slti rd,rs1,imm12 rd = rs1 <signed se(imm12) ? 1 : 0
sltiu rd,rs1,imm12 rd = rs1 <unsign se(imm12) ? 1 : 0
xori rd,rs1,imm12 rd = rs1 ^ se(imm12)
ori rd,rs1,imm12 rd = rs1 | se(imm12)
andi rd,rs1,imm12 rd = rs1 & se(imm12)
slli rd,rs1,imm12 rd = rs1 << imm12[4:0]
srli rd,rs1,imm12 rd = rs1 >> imm12[4:0]
srai rd,rs1,imm12 rd = rs1 >>> imm12[4:0]

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CIS 5710 | Dr. Joe Devietti | ISAs & Single Cycle
Signed vs unsigned
• slti x1,x0,0x876
• x1 = x0 < signextend(0x876) ? 1 : 0
• sltiu x1,x0,0x876
• x1 = x0 <unsigned signextend(0x876) ? 1 : 0

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CIS 5710 | Dr. Joe Devietti | ISAs & Single Cycle
CIS 5710 | Dr. Joe Devietti | ISAs & Single Cycle
Memory Insns
• 5 load insns
• lb, lh, lw for loading byte (8b), half (16b), word (32b)
• lb/lh perform sign extension to 32b
• lbu, lhu perform zero extension instead
• 3 store insns
• sb, sh, sw to write 8b, 16b or 32b to memory

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Memory Access Granularity
• RV is byte addressable
• each address points to a byte (8b) of data
• cannot directly manipulate smaller units (bits, nibbles)

Address Value
0 A
lb x1,0(x0)
1 B
opcode 2 C
destination register
3 D
immediate
source register 4 E
load address = source + immediate 5 F
6 G
7 H

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CIS 5710 | Dr. Joe Devietti | ISAs & Single Cycle
CIS 5710 | Dr. Joe Devietti | ISAs & Single Cycle
Memory Access Alignment
• All storage devices have some internal structure
• let’s assume our memory is built of 4B chunks
• what happens with lh x1,3(x0)?
• If address % size == 0, the access is aligned
• what if an access is misaligned? Address Value
0 A
1 B
2 C
3 D
4 E
5 F
6 G
7 H
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Misaligned/Unaligned Accesses
• if address % size != 0, access is misaligned
• misaligned may require multiple physical memory accesses
• How to handle misaligned accesses?
• Disallow and crash the program
• MIPS, ARMv5
• Handle it transparently
• x86, ARMv6+, RV
👍easier to program
👎slower, adds significant hardware complexity
• Trap to software routine
• simple hardware, but high penalty when it occurs
• Compilers try to avoid misaligned accesses
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How big is this struct in C?

struct foo {
char c;
int i;
}

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CIS 5710 | Dr. Joe Devietti | ISAs & Single Cycle
Memory Endian-ness
• the arrangement of bytes in a multi-byte number
• within a byte, LS bit is always position 0
• Big-endian: MS byte first in memory
• the sensible order, used by MIPS, PowerPC
• Little-endian: LS byte first in memory
• x86, ARM, RV
• ARM & RV are runtime-configurable, but usually run in LE

address 0 1 2 3
big-endian 00000000 00000000 00000001 00000011 256 + 3 = 259
little-endian 00000011 00000001 00000000 00000000 3 + 256 = 259

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Why do we have little-endian?
• driven by popularity of x86
• integer casts are free on LE
address 0 1 2 3
little-endian 00000011 00000001 00000000 00000000

int* points here

short* and char* also point here!

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Jumps
• used for function calls, returns, and plain jumps
• jal x1,0x123
• jump and link
• jump to PC+0x123, write PC+4 to x1
• jalr x1,0x10(x2)
• jal but destination in a register instead
• jump to x2+0x10, write PC+4 to x1
• regular jump is jal x0,offset

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Branches
• branch based on comparing two registers
• beq x1,x2,0x456
• branch to PC+0x456 if x1 == x2
• also bltu and bgeu for unsigned comparisons

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RV Assembly

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 RV array sum program
// C code
int array[5];
# c/o ChatGPT
int sum;
# the array
void array_sum() {
.data
array: .word 1, 2, 3, 4, 5 for (int i=0; i<5;i++) {
sum += array[i];
array_sum: }
la a1, array # load base address }
li a2, 5 # array length
li a3, 0 # initialize sum

loop:
lw a4, 0(a1) # load element
add a3, a3, a4 # add to sum
addi a1, a1, 4 # increment pointer
addi a2, a2, -1 # decrement index
bnez a2, loop # all done?

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At least it’s not x86
• variable-length insns from 1-15B
• only 16 registers
• and many registers that are prefixes of others
• most insns have only two operands
• source and source+destination
• registers are frequently overwritten
• over 300 insns

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My favorite x86 insn

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