Introduction to X-86 Family
4M
Block Diagram of 8086
Programming model of X-86 Family of 16 bit
Programming model of X-86 Family of 32 bit
Flag register of 8086,X-86 family
Comparison of features of X-86 family
Explain with Block Diagram of 8086-4M
BIU
Memory
Interface
control Bus
6 Instruction
cs 5 stream
SS 4 byte
DS 3 queue
ES 2
IP 1
EU Control
system
AH AL ALU
BH BL
CH CL
DH DL Operand
SP flag
BP
SI
DI
8086 consists of 2 parts
1)BIU 2)EU
1)BIU(Bus Interface Unit) : It sends address, fetches
instruction from memory, reads data from memory and writes
data to memory. It consists of following parts.
a)Segment registers: BIU consists of 4 segment registers
which are all of 16 bit.
1)Code Segment(CS)
2)Data segment(DS)
3)Extra segment(ES)
4)Stack segment(SS)
b) Instruction Pointer(IP): The IP holds 16 bit address of next
instruction to be executed. It is similar to program counter.
c) Queue: To speed up execution of program BIU fetches 6
instruction bytes ahead of time from memory and stores them
for EU in FIFO register called queue.
2)Execution Unit(EU):EU tells BIU where to fetch instructions
or data , decodes instruction and executes them. It consists of
a) General Purpose Registers :There are 8 general purpose
registers AH-AL(AX), BH-BL(BX), CH-CL(CX), DH-DL(DX),SP,
BP,DI,SI, which are all of 16 bit.
Flag Register: 8086 flag register is of 16 bit in which 9 flags
are active and 7 flags are inactive.
Draw a neat labelled diagram and explain Programming
model of X-86 Family of 16 bit-4M
The 16 bit version of programming model of X-86 family is
shown in the following figure
As shown in above figure the programming model of 16 bit
version of X-86 family consists of 3 register groups.
1)The first group contain 8 general purpose registers
AX,BX,CX,DX,SP,BP,SI,DI.These general purpose registers are
all of 16 bit. These are pointer registers because they are
used to point locations within a segment.
2) The second group of registers is the segment group of
registers. There are 4 segment registers code
segment(CS),stack segment(SS),Data segment(DS) and Extra
segment(ES). There are 2 Data segment Data segment(DS)
and Extra segment(ES).These are all of 16 bit.
3)The third group of registers consists of Instruction
Pointer(IP) and flag register which are of 16 bit.
Draw a neat labelled diagram and explain Programming
model of X-86 Family of 32 bit-4M
The 32 bit version of programming model of X-86 family is
shown in the following figure
As shown in above figure the programming model of 32 bit
version of X-86 family consists of 3 register groups.
1)The first group contain 8 general purpose registers
EAX,EBX,ECX,EDX,ESP,EBP,ESI,EDI. These general purpose
registers are all of 32 bit. These registers are used to store data
during computations .
2) The second group of registers is the segment group of
registers. There are 4 segment registers code segment(CS),stack
Segment(SS),Data segment(DS) and Extra segment(ES). There are
4 Data segment Data segment(DS), Extra segment(ES),FS and GS.
These are all of 16 bit.
3) The third group of registers consists of Instruction Pointer(IP)
and flag register.These are all of 32 bit.
Flag register of 8086
8086 Flag register is of 16 bit in which 9 flags are active and 7
flags are inactive
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-- -- -- -- OF DF IF TF S Z -- Ac -- P -- Cy
The 9 flags which are active are
1)Cy-Carry Flag
2)P-Parity Flag
3)Ac-Auxiliary Carry Flag
4)Z-Zero Flag
5) S-Sign Flag
6)TF-Trap Flag used for single stepping instructions.
7)IF-Interrupt Flag used to enable or disable external maskable
interrupts requests.
8) DF-Direction Flag-Used to control the direction
(increment/decrement) of the string operation.
9) OF-Overflow Flag- used in signed numbers, when the result
of signed number is too large, causing MSB to overflow into
sign bit ,this flag is set.
Flag register of X-86
The Flag register of X-86 family is of 32 bit
31------- 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Ac VM RF O NT IO PL O D I T S Z -- A -- P -- Cy
Where
1)Cy-Carry Flag
2)P-Parity Flag
3)A-Auxiliary Carry Flag
4)Z-Zero Flag
5) S-Sign Flag
6)T-Trap Flag used for single stepping instructions.
7)I-Interrupt Flag used to enable or disable external maskable
interrupts requests.
8) D-Direction Flag-Used to control the direction
(increment/decrement) of the string operation.
9) O-Overflow Flag- used in signed numbers, when the result
of signed number is too large, causing MSB to overflow into
sign bit ,this flag is set.
10)PL-Privilege Level
11)IO-Input / Output
12)NT- Nested Task Flag
13)RF-Resume Flag
14)VM-Virtual Mode Flag
15)Ac- Alignment Check Flag
Comparison of features of X-86 family-3/4 M
Microprocessor 8086 80286 80386 80486 Pentium
1)Introduction 1978 1982 1985 1989 1993
2)Data Bus(bits) 16 16 32 32 64
3)Address 20 24 32 32 32
Bus((bits)
4)Operating 5-10 6-20 16-33 25-50 50-100
Speed(MHz)
5)Memory 1MB 16MB 4GB 4GB 4GB
capacity
6)Memory External External External Internal Internal
management
7)PC Type(IBM) PC-XT PC-AT PC-AT PC-AT PC-AT
8)Math External External External Internal Internal
Co-Processor
Advanced Design Features of Pentium-4M
1)Dual Pipelining Architecture –It has 2 execution units with dual
pipelined architecture ,able to execute 2 instructions
simultaneously per clock cycle and achieve a high level of
performance.
2) On chip cache memory for instructions and data-
It is found that the speed of CPU and main memory is
mismatching , main memory speed is very low as compared to
CPU speed. To compensate this mismatch a high speed memory is
used to store current programs and data and to make it available
to CPU with faster rate. The cache holds those segments of
program and data which are frequently required by CPU and for
remaining program and data CPU access main memory.
Using a cache by CPU results in best performance of a
computer system. All latest CPU make use of cache. Pentium
has 2,8 KB on cache, memory on chip, one for code and other
for data ,which eliminates the need of processor to go off the
chip and access the main memory during the loop execution,
thus improving performance of microprocessor.
3)The Branch Prediction : Using branch prediction it makes an
intelligent guess of the next conditional instruction, it prevents
the instruction cache from running dry during conditional
instruction.
4)High performance floating point unit: This microprocessor
has an on-chip floating point unit that incorporates highly
sophisticated 7 stage pipelining and hardwired code.
5) Performance monitoring : Processor design enables the
user to monitor the performance of the processor.
6) 64 –bit data bus : Pentium has a wide 64-bit data bus which
results in high speed data transfer.
