Digital IC Design

Lec 3: MOS/Wire RC for Transient Time

黃柏蒼 Po-Tsang (Bug) Huang

[email protected]

International College of Semiconductor Technology

National Chiao Tung Yang Ming University
Delay Definitions

Vin Vout

Vin
Propagation delay
input 50% tp = (tpHL + tpLH)/2
waveform

t
tpHL tpLH
Vout
90%
output
50% signal slopes
waveform
10%
t
tf tr

2
CMOS Inverter : Dynamic
 Transient, or dynamic, response determines
the maximum speed at which a device can be
operated.
VDD

Vout = 0

Rn
CL tpHL = f(Rn, CL)

Vin = V DD
3
Transient Response

4
Inverter Propagation Delay (Designer)
 To see how a designer can optimize the delay
of a gate have to expand the Req in the delay
equation

tpHL = 0.69 Reqn CL

= 0.69 (3/4 (CL VDD)/IDSATn )

≈ 0.52 CL / (W/Ln k’n VDSATn )

5
Impacts of NMOS/PMOS Ratio
5
β = (W/Lp)/(W/Ln)
tpLH tpHL
4.5
β of 2.4 (= 31 kΩ/13 kΩ)
gives symmetrical
4 tp response

3.5 β of 1.6 to 1.9 gives

optimal performance
3
1 2 3 4 5
β = (W/Lp)/(W/Ln)

6
 Calibrating Delays
 Step RC delay model is a good first-order
approximation
 Accuracy can be improved by including:
 Slope effects
 Non-linear capacitive loading
 Signal arrival times
 Wire models

7
Sources of Capacitance
 intrinsic MOS transistor capacitances
 extrinsic MOS transistor (fanout) capacitances
 wiring (interconnect) capacitance

Vout
Vin Vout2
CL

CG4
M2
M4
CDB2
pdrain Vout Vout2
Vin
CGD12 ndrain Cw
CDB1 M3
M1
CG3

8
MOS Capacitances
 Gate capacitance
 Non-linear channel capacitance
 Linear overlap, fringing capacitances
 Miller effect on overlap capacitance
 Non-linear drain diffusion capacitance
 PN junction
 Wiring capacitances
 Linear

9
 Intrinsic MOS Capacitances
 Structure capacitances

 Channel capacitances

 Diffusion capacitances from the depletion

regions of the reverse-biased pn-junctions
G
CGS = CGCS + CGSO CGD = CGCD + CGDO
CGS CGD

S D
CSB CGB CDB
CSB = CSdiff CDB = CDdiff
B CGB = CGCB 10
 Gate-Drain Capacitance: The Miller Effect
 M1 and M2 are either in cut-off or in saturation.
 The floating gate-drain capacitor is replaced by a
capacitance-to-ground (gate-bulk capacitor).
 Miller Effect: A capacitor experiencing identical but
opposite voltage swings at both its terminals can be
replaced by a capacitor to ground whose value is two
times the original value.

∆V CGD1 Vout
Vout ∆V
Vin 2CGB1
∆V
∆V
M1 M1
Vin

11
 Fan-Out of a Cell (gate)
 Typically, the output of a logic gate is connected to
the input(s) of one or more logic gates
 The fan-out is the number of gates that are connected
to the output of the driving gate

 Fanout leads to increased capacitive load on the

driving gate, and therefore longer propagation delay
 The input capacitances of the driven gates sum, and must be
charged through the equivalent resistance of the driver

12
 Extrinsic (Fan-Out) Capacitance
 The extrinsic, or fan-out, capacitance is the total gate
capacitance of the loading gates M3 and M4.
Cfan-out = Cgate (NMOS) + Cgate (PMOS)
= (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox)

 Simplification of the actual situation

Assumes all the components of Cgate are between Vout and
GND (or VDD)
Assumes the channel capacitances of the loading gates are
constant

13
FO4 Inverter Delay

14
 Wiring Capacitance
 The wiring capacitance depends upon the
length and width of the connecting wires and is
a function of the fan-out from the driving gate
and the number of fan-out gates.
 Wiring capacitance is growing in importance
with the scaling of technology.

15
Parallel Plate Wiring Capacitance

current flow

electrical field lines

W
H
tdi dielectric (SiO2)

substrate

permittivity
constant Cpp = (εdi/tdi) WL
(SiO2= 3.9)

16
Sources of Interwire Capacitance
Cwire = Cpp + Cfringe + Cinterwire
= (εdi/tdi)WL
+ (2πεdi)/log(tdi/H)
+ (εdi/tdi)HL

fringe

interwire

pp

17
Impact of Fringe Capacitance

H/tdi = 1

H/tdi = 0.5

Cpp

W/tdi

18
Impact of Interwire Capacitance

19
 Wiring Insights
 For W/H < 1.5, the fringe component dominates the parallel-
plate component. Fringing capacitance can increase the overall
capacitance by a factor of 10 or more.
 When W/H < 1.75 interwire capacitance starts to dominate
 Interwire capacitance is more pronounced for wires in the
higher interconnect layers (further from the substrate)
 Rules of thumb
 Never run wires in diffusion
 Use poly only for short runs
 Shorter wires – lower R and C
 Thinner wires – lower C but higher R
 Wire delay nearly proportional to L2

20
CMOS Inverter : Dynamic
 Transient, or dynamic, response determines
the maximum speed at which a device can be
operated.
VDD

Vout = 0

Rn
CL tpHL = f(Rn, CL)

Vin = V DD
21
 Sources of Resistance
 MOS structure resistance - Ron
 Source and drain resistance
 Contact (via) resistance
 Wiring resistance

Poly Gate

Drain n+ Source n+
W

22
MOS Transistor as a Switch

23
Equivalent MOS Resistance

24
Equivalent MOS Resistance

25
Approximate MOS Resistance

26
CMOS Performance

27
MOS Structure Resistance
 The simplest model assumes the transistor is a switch
with an infinite “off” resistance and a finite “on”
resistance Ron
VGS ≥ VT
Ron
S D

 However Ron is nonlinear, so use instead the average

value of the resistances, Req, at the end-points of the
transition (VDD and VDD/2)

Req = ½ (Ron(t1) + Ron(t2))

Req = ¾ VDD/IDSAT (1 – 5/6 λ VDD)

28
Source and Drain Resistance

D
S
RS RD
RS,D = (LS,D/W)R

where LS,D is the length of the source or drain diffusion

R is the sheet resistance of the source or drain
diffusion (20 to 100 Ω/)
 More pronounced with scaling since junctions
are shallower
 With silicidation R is reduced to the range 1
to 4 Ω/
29
 Contact Resistance
 Transitions between routing layers (contacts through via’s) add
extra resistance to a wire
keep signals wires on a single layer whenever possible
avoid excess contacts
reduce contact resistance by making vias larger (beware of
current crowding that puts a practical limit on the size of
vias) or by using multiple minimum-size vias to make the
contact
 Typical contact resistances, RC, (minimum-size)
5 to 20 Ω for metal or poly to n+, p+ diffusion and metal to
poly
1 to 5 Ω for metal to metal contacts
 More pronounced with scaling since contact openings are
smaller

30
Contacts Resistance
 Use many contacts for lower R
 Many small contacts for current crowding around
periphery

31
Wire Resistance
ρL ρ L
R= =
A HW
Sheet Resistance R
L R1 = R2
H
=
W
Material Sheet Res. (Ω/)
Material ρ(Ω-m) n, p well diffusion 1000 to 1500
Silver (Ag) 1.6 x 10-8 n+, p+ diffusion 50 to 150

Copper (Cu) 1.7 x 10-8 n+, p+ diffusion with 3 to 5

silicide
Gold (Au) 2.2 x 10-8
polysilicon 150 to 200
Aluminum (Al) 2.7 x 10-8 polysilicon with 4 to 5
Tungsten (W) 5.5 x 10-8 silicide
Aluminum 0.05 to 0.1
32
 Skin Effect
 At high frequency, currents tend to flow primarily on
the surface of a conductor with the current density
falling off exponentially with depth into the wire
W
δ= √(ρ/(πfµ)) δ= 2.6 µm
where f is frequency for Al at 1 GHz
H µ = 4π x 10-7 H/m

so the overall cross section is ~ 2(W+H)δ

 The onset of skin effect is at fs - where the skin depth is
equal to half the largest dimension of the wire.
fs = 4 ρ / (π µ (max(W,H))2)
 An issue for high frequency, wide (tall) wires (i.e., clocks!)

33
Skin Effect for Different W’s
for H = .70 um
1000
% Increase in Resistance

100

10

1 W = 1 um
W = 10 um
W = 20 um
0.1
1E8 1E9 1E10
Frequency (Hz)

 A 30% increase in resistance is observe for 20 µm Al wires

at 1 GHz (versus only a 1% increase for 1 µm wires)
34
The Wire

transmitters receivers

schematic physical

35
Wire Models
Interconnect parasitics (capacitance, resistance, and
inductance)
 reduce reliability
 affect performance and power consumption

All-inclusive (C,R,l) model Capacitance-only 36

 Parasitic Simplifications
 Inductive effects can be ignored
if the resistance of the wire is substantial enough (as is the
case for long metal wires with small cross section)
if the rise and fall times of the applied signals are slow
enough

 When the wire is short, or the cross-section is large, or the

interconnect material has low resistivity, a capacitance only
model can be used

 When the separation between neighboring wires is large, or

when the wires run together for only a short distance, interwire
capacitance can be ignored and all the parasitic capacitance can
be modeled as capacitance to ground

37
 Wire Delay Models
 Ideal wire
 same voltage is present at every segment of the wire at every point in
time - at equi-potential
 only holds for very short wires, i.e., interconnects between very nearest
neighbor gates
 Lumped C model
 when only a single parasitic component (C, R, or L) is dominant the different
fractions are lumped into a single circuit element
When the resistive component is small and the switching frequency is low
to medium, can consider only C; the wire itself does not introduce any
delay; the only impact on performance comes from wire capacitance
Driver
Vout RDriver Vout

cwire Clumped

capacitance per unit length

 good for short wires; pessimistic and inaccurate for long wires 38
 Lumped/Distributed Delay Models
 Lumped RC model
 total wire resistance is lumped into a single R and total capacitance into
a single C
 good for short wires; pessimistic and inaccurate for long wires
 Distributed RC model
 circuit parasitics are distributed along the length, L, of the wire
 c and r are the capacitance and resistance per unit length

r∆L r∆L r∆L r∆L r∆L (r,c,L)

Vin VN Vin VN
c∆L c∆L c∆L c∆L c∆L

 Delay is determined using the Elmore delay equation

N
τDi = ∑ ckrik
k=1

39
 RC Tree Definitions
 RC tree characteristics 2
 A unique resistive path exists between r2
r c2
the source node and any node of the s 1 1
network r3 r 4

Single input (source) node, s c

4 c4
1
All capacitors are between a node 3 ri
and GND c3
No resistive loops i
 Path resistance (sum of the resistances on the path from the ci
input node to node i)
i
rii = ∑ rj ⇒ (rj ∈ [path(s → i)]
j=1

 Shared path resistance (resistance shared along the paths from

the input node N
to nodes i and k)
rik = ∑ rj ⇒ (rj ∈ [path(s → i) ∩ path(s → k)])
j=1
 A typical wire is a chain network with (simplified) Elmore
delay of N
τ = ∑ crDN i ii
40
i=1
Chain Network Elmore Delay
τD1=c1r1 τD2=c1r1 + c2(r1+r2)
r1 r2 ri-1 ri rN
1 2 i-1 i N
Vin VN
c1 c2 ci-1 ci cN

τDi=c1r1+ c2(r1+r2)+…+ci(r1+r2+…+ri)

N i
Elmore delay equation τDN = ∑ cirii = ∑ ci ∑ rj

τDi=c1req+ 2c2req+ 3c3req+…+ icireq

41
Distributed RC Model for Simple Wires
 A length L RC wire can be modeled by N
segments of length L/N
The resistance and capacitance of each segment
are given by r L/N and c L/N

τDN = (L/N)2(cr+2cr+…+Ncr) = (crL2) (N(N+1))/(2N2) = CR((N+1)/(2N))

where R (= rL) and C (= cL) are the total lumped resistance and
capacitance of the wire

 For large N τDN = RC/2 = rcL2/2

 Delay of a wire is a quadratic function of its length, L
 The delay is 1/2 of that predicted (by the lumped model)

42
Step Response Points
Voltage Range Lumped RC Distributed RC
0 → 50% (tp) 0.69 RC 0.38 RC
0 → 63% (τ) RC 0.5 RC
10% → 90% (tr) 2.2 RC 0.9 RC
0 → 90% 2.3 RC 1.0 RC

Time to reach the 50% point is t = ln(2)τ = 0.69τ

Time to reach the 90% point is t = ln(9)τ = 2.2τ

43
 Nature of Interconnect

Pentium Pro (R)

Pentium(R) II
Pentium (MMX)
Pentium (R)
Pentium (R) II
(Log Scale)
No of nets

10 100 1,000 10,000 100,000

Length (u)

44
Wire Spacing
Intel P858
Intel P856.5 Al, 0.18µm IBM CMOS-8S
Al, 0.25µm CU, 0.18µm
Ω - 0.07 M6

Ω - 0.05 M5
Ω - 0.10 M7
Ω - 0.08 M5

Ω - 0.10 M6
Ω - 0.12 M4
Ω - 0.17 M4
Ω - 0.50 M5
Ω - 0.33 M3
Ω - 0.49 M3 Ω - 0.50 M4

Ω - 0.50 M3
Ω - 0.33 M2 Ω - 0.49 M2
Ω - 0.70 M2
Ω - 1.11 M1 Ω - 1.00 M1 Ω - 0.97 M1
Scale: 2,160 nm

45
Inductance of Wires
 When the rise and fall times of the signal become comparable
to the time of flight of the signal waveform across the line,
then the inductance of the wire starts to dominate the delay
behavior
l l l l
r r r r
Vin Vout
g c g c g c g c

 Must consider wire transmission line effects

Signal propagates over the wire as a wave (rather than
diffusing as in rc only models)
 Signal propagates by alternately transferring energy
from
capacitive to inductive modes
46
 Delay of MOS + Wire
RDriver rw,cw,L
Vout
Vin

 Total propagation delay consider driver and wire

τD = RDriverCw + (RwCw)/2 = RDriverCw + 0.5rwcwL2
and tp = 0.69 RDriverCw + 0.38 RwCw
where Rw = rwL and Cw = cwL
 The delay introduced by wire resistance becomes dominant
when
(RwCw)/2 ≥ RDriver CW (when L ≥ 2RDriver/Rw)
 For an RDriver = 1 kΩ driving an 1 µm wide Al1 wire, Lcrit is
2.67 cm

47
 Crosstalk
 A capacitor does not like to change its voltage
instantaneously.
 A wire has high capacitance to its neighbor.
 When the neighbor switches from 1-> 0 or 0->1, the
wire tends to switch too.
 Called capacitive coupling or crosstalk.
 Crosstalk effects
 Noise on nonswitching wires
 Increased delay on switching wires

48
Crosstalk Delay
 Assume layers above and below on average are
quiet
 Second terminal of capacitor can be ignored
 Model as Cgnd = Ctop + Cbot
 Effective Cadj depends on behavior of neighbors
 Miller effect
A B
Cadj
Cgnd Cgnd

B ∆V Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A 0 Cgnd 0
Switching opposite A 2VDD Cgnd + 2 Cadj 2

49
 Crosstalk Noise
 Crosstalk causes noise on nonswitching wires
 If victim is floating:
 model as capacitive voltage divider

Cadj
Vvictim
∆= ∆Vaggressor
C gnd −v + Cadj
Aggressor

∆Vaggressor
Cadj
Victim
Cgnd-v ∆Vvictim

50
Coupling Waveforms
 Simulated coupling for Cadj = Cvictim

Aggressor
1.8

1.5

1.2

Victim (undriven): 50%

0.9

0.6
Victim (half size driver): 16%

Victim (equal size driver): 8%

0.3 Victim (double size driver): 4%

0
0 200 400 600 800 1000 1200 1400 1800 2000

t(ps)

51
 Noise Implications
 So what if we have noise?
 If the noise is less than the noise margin,
nothing happens
 Static CMOS logic will eventually settle to
correct output even if disturbed by large noise
spikes
 But glitches cause extra delay
 Also cause extra power from false transitions
 Dynamic logic never recovers from glitches
 Memories and other sensitive circuits also can
produce the wrong answer
52
 Wire Engineering
 Goal: achieve delay, area, power goals with
acceptable noise
 Degrees of freedom:
 Width
 Spacing
 Layer
 Shielding

vdd a0 a1 gnd a2 a3 vdd vdd a0 gnd a1 vdd a2 gnd a0 b0 a1 b1 a2 b2

53
 Repeaters
 R and C are proportional to l
 RC delay is proportional to l2
 Unacceptably great for long wires
 Break long wires into N shorter segments
 Drive each one with an inverter or buffer

Wire Length: l

Driver Receiver

N Segments
Segment

l/N l/N l/N

Driver Repeater Repeater Repeater Receiver

54