Interviewer 1 :
1. Tell about the work you have done in DFT domain.
Scan insertion, ATPG, simulations
2. If you have faced any clock DRC, what was the scenario and how you resolved it.
Uncontrollable clock: when clocks are not controllable from top(use mux to solve)
Clock driving data
3. How to check the coverage for the enable pin of clock gaters.
By setting enable pin to 0.
4. How reset pin coverage checked for stuck-at and transition fault
By defining reset pin as clock, we can toggle
5. EDT architecture. EDT update signal working.
EDT architecture consists of decompressor, compactor and bypass module
Decompressor will be having ring generator and phase shifter.
Ring generator generates random patterns and phase shifter consists of xor logic which provides
more randomness and drives more number of scan chains.
Compressor consists of masking register and masking logic with xor tree logic and pipeline flops.
To block the x propagation, and gates are used as masking gates
If any scan chain output is x, that particular and gate output is zero, in this way propagation of x is
blocked
Xor tree is used to compress several scan chains data and gives less data volume to scan channel
outputs, pipeline flops to increase data transfer rate.
Edt control signals:
Edt clock and edt update
Edt clock should not pulse in capture phase, bcoz if edt clock is pulsing, the new data will be pumped
into scan chains which will replace previous data, so if any faults in the previous data will not be
detected.
Edt update signal is used to reset the ring generator and mask hold register.
During load/unload edt update is activated, which makes ring generator register 0 and mask hold
register is loaded with the value in the mask shift register
Edt bypass : to bypass the test compression logic, it is used to disable the compression logic, test data
flow directly to scan chains without going to compression and decompression stages.
Edt bypass signal is used to enable or disable the bypass functionality.
In normal mode , edt compression is enabled(normal edt mode)
In bypass mode, compression logic is bypassed and test data is applied and retrieved from scan chains
directly.
If something goes wrong during testing in compressed mode, bypass signal is having direct access to
scan chains.
6. OCC architecture.
Occ is onchip clock controller is also known as scan clock controller.
Occ is the logic inserted in soc for controlling clocks
Occ uses pll to generate clock pulses , during stuck at testing it generates one clock pulse in the capture
phase and 2 clock pulses during atspeed testing
When tm=0, occ bypasses the functional clock
When during shift phase when se=1 , scan clock is propagated to occ,
when se=0, shift register starts shifting 1,and enables the clock gate, to allow single pulse or double pulse
depending upon the type of testing.
7. How to check the 0 – 1 transition fault for one of the input a AND gate where the 2 inputs of
AND gate is from 2 different flops (FF1 and FF2) and the output of AND gate is connected to
another flop (FF3).
8. Explain about LOC, LOS and LOES.
ATSPEED TESTING TECHNIQUES
LOC: LAUNCH ON CAPTURE: After shifting in the test pattern, the scan enable (SE) signal is de-
asserted, placing the design in functional mode. The first clock pulse launches the transition, and
the second clock pulse captures the result at-speed.
LOS: During LOS, the scan enable (SE) remains active, meaning the scan chain is still in shift
mode. A fast clock pulse creates a launch transition on the outputs, and a subsequent capture
pulse captures the response.
LOES: Launch on Extra Shift uses an extra shift clock compared to LOS. It's as efficient as LOS in
terms of coverage and test patterns.
9. Pipeline Structure of SE signal in LOS and LOES.
transition of scan enable signal between two function frequency clocks would increase the cost
of testing and also it is very difficult with low speed ATEs. So, pipelined scan enable signal is a
solution for that
10. Coverage analysis.
11. What is LEC. What are the steps involved in doing LEC.(conformal tool)
Logical Equivalence Check (LEC) is a crucial step in the chip design process that verifies the functionality
of a circuit. It compares two representations of a digital circuit to ensure they are functionally
equivalent. The steps involved in LEC are:
Setup mode: Read the two designs, designate their types, and require three types of files.
Mapping mode: Automatically map key points and compare them.
Compare mode: Examine key points to determine if they are equivalent or non-equivalent.
Debug: If the tool returns a non-equivalent result, improve the logics and check again until they are
logically equivalent to the reference design.
12. Parallel and serial pattern simulation. In which pattern EDT logics are covered.
In serial patterns, all the patterns are applied through ScanIn and ScanOut. The operations are
similar to the Tester environment. But the parallel patterns are applied directly to the internal
registers, therefore no Shift-in, shift-out. So reduces the test time.
Serial patterns cover edt logic.
13. What is MBIST. Explain on MBIST sim debug. If write and read work on different clock
frequencies which clock is to be used by controller.
