IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 70, NO.

12, DECEMBER 2023 6329

An Accurate Drain Current Model of

Multichannel Cylindrical High-K
HfO2-/Si3N4-Based GAA-MOSFET
for SRAM Application
Krutideepa Bhol, Biswajit Jena , Member, IEEE, and Umakanta Nanda , Senior Member, IEEE

Abstract— This research proposes an innovative ana- led to a constant process of scaling down transistor devices
lytical approach for studying the electrostatic potential [2]. The advancement to the 7-nm technology node and beyond
distribution in multichannel gate-all-around metal–oxide– has become feasible due to the utilization of multigate devices,
semiconductor field-effect transistors (GAA MOSFETs).
The model focuses specifically on the effect of multiple particularly gate-all-around (GAA) MOSFETs. These devices
nanowires on the electrostatic potential distribution and feature a gate that completely surrounds the transistor’s small
the subsequent impact on device performance in lower conduction channel, known as the nanowire. This configu-
technology nodes. To validate the analytical model for small ration enables improved control over short-channel effects
gate lengths, simulations are performed using the quantum (SCE), which is essential for achieving different technology
potential model. The results obtained from the analytical
model were further validated using the TCAD simulation. nodes [3], [4], [5]. The technique also offers more density
In addition, the noise margin parameters are extracted to scaling, which is becoming increasingly difficult due to gate
evaluate the feasibility of advanced static random access pitch scaling issues. Currently, it is extremely difficult to scale
memory (SRAM) cells. The noise margin in hold (336, 349, down the dielectric thickness to match the demand for lower
342), read (100, 93, 93), and write (243, 245, 249) for different technology nodes without high-K dielectric such as Si3 N4 and
channel separation (4, 8, 10 nm) are extensively investi-
gated. These findings provide a valuable contribution to HfO2 [6].
the understanding of the electrostatic potential distribution From one perception, device scaling causes developments
in multichannel GAA MOSFETs and application toward the in terms of functionality, speed, power consumption, cost per
development of more advanced SRAM cells. device, and device density per chip area [7]. However, when
Index Terms— Gate-all-around metal–oxide– transistors are made smaller, reaching lengths of about 10 nm,
semiconductor field-effect transistor (GAA-MOSFET), several undesirable effects start to occur. These effects include
high-K dielectric, nanowire, quantum, TCAD. drain-induced barrier lowering (DIBL), where the barrier sep-
arating the source and drain regions is reduced. Another effect
I. I NTRODUCTION is an increase in leakage current, which leads to energy loss
NCREASED demand for portable gadgets is revolutioniz- and impacts the performance. Threshold voltage roll-off is also
I ing the semiconductor device industry by allowing a single
processor to encompass about two billion transistors [1]. Over
observed, which means the voltage required to activate the
transistor decreases. In addition, there is a phenomenon called
the past few decades, there has been a growing need for subthreshold slope, which affects the efficiency of switching
integrated circuits that consume less power. This demand has between ON and OFF states. As devices continue to shrink,
these effects become more prominent and pose challenges
Manuscript received 30 June 2023; revised 28 August 2023 and in maintaining optimal device performance and power effi-
10 October 2023; accepted 17 October 2023. Date of publication
31 October 2023; date of current version 28 November 2023. The review
ciency [8]. Researchers are actively exploring the potential of
of this article was arranged by Editor B. Iñiguez. (Corresponding author: using HfO2 instead of SiO2 in nanoscale GAA-MOSFETs.
Umakanta Nanda.) This switch offers benefits such as reduced leakage current
Krutideepa Bhol is with the Department of Electronics and Commu-
nication Engineering, Sathyabama Institute of Science and Technology,
and improved device performance. HfO2 minimizes leakage
Chennai 600119, India. current, leading to increased energy efficiency and lower power
Biswajit Jena is with the School of Electronics Engineering, Vellore consumption [9], [10], [11]. High-K dielectric material has the
Institute of Technology, Chennai 600127, India.
Umakanta Nanda is with the School of Electronics Engineering,
capacity of better gate controllability, which further makes it
VIT-AP University, Amaravati, Andhra Pradesh 522237, India (e-mail: a better choice for low-power applications [12], [13], [14],
[email protected]). [15]. The introduction of multiple channels to the GAA metal–
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TED.2023.3326792. oxide–semiconductor field-effect transistor (GAA MOSFET)
Digital Object Identifier 10.1109/TED.2023.3326792 has been found to significantly increase the drain current

0018-9383 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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 6330 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 70, NO. 12, DECEMBER 2023

the silicon channel, a high-K dielectric material (HfO2 ) and

Si3 N4 were used as interfacial oxide layers. Each silicon pillar
(channel) was assigned an individual oxide layer to ensure
uniform controllability of the gate metal over the channel from
all directions.
Fig. 1 represents a bird’s eye view of the proposed structure
highlighting all the device components and its architec-
tural view. The schematic view of the cylindrical nanowire
device is shown in Fig. 1(a)–(f), which depicts the gate
oxide consisting of two layers: Si3 N4 and HfO2 . In this
structure, Si3 N4 is the thinner layer that is located closer
to the Si channel, while HfO2 is the thicker layer that is
deposited on top of Si3 N4 . The utilization of HfO2 material
is vital in minimizing the leakage current and SCE, includ-
Fig. 1. Three Dimensional view of (a) channel, (b) interfacial layer,
ing DIBL. This is due to the high gate dielectric constant
(c) high-K dielectric, (d) spacer, (e) transparent structure, and (f) solid value of 25 attributed to HfO2 . Table I represents the device
structure. dimensions for the proposed structure. The use of HfO2 as
the gate dielectric material, along with the specific device
TABLE I dimensions selected for this research, is very crucial in achiev-
D EVICE D IMENSIONS OF THEP ROPOSED S TRUCTURE ing the desired performance characteristics of the nanowire
GAA-MOSFET.

III. A NALYTICAL M ODELING

The 2-D Poisson’s equation along the z-axis for cylindrical
coordinate is represented as [12]
1 ∂ r ∂ψ(r, z) ∂ 2 ψ(r, z)
 
q Na
+ = . (1)
r ∂r ∂r ∂z 2 ϵsi
The distribution of electrostatic potential in the channel regions
of the device. By incorporating multiple channels, the GAA can be expressed as a parabolic function as follows:
MOSFET is able to provide additional pathways for the flow ψ(r, z) = A0 (z) + A1 (z)r + A2 (z)r 2 . (2)
of current, resulting in a higher overall drain current. This
increased current facilitates improved device performance, as it Different boundary conditions associated with a cylinder will
enhances the transistor’s ability to deliver and handle electrical determine the arbitrary coefficients A0 (z), A1 (z), and A2 (z).
signals. However, the distance or separation between the two The center potential is a function of “z” only
channels in the GAA-MOSFETs is a significant factor that
ψc (r, z) = ψc (r = 0, z) = ψc (z) = A0 (z). (3)
can impact the device’s performance. To address this concern,
this device is extensively investigated to evaluate how varying The radial electric field in the center of silicon pillar is zero
the channel separation affects the performance of the device,
dψ(r, z)
both at the transistor level and in static random access memory = 0 = A1 (z). (4)
(SRAM) applications. dr r =0
The electric field at the Si/Si3 N4 interface
II. M ODEL S IMULATION S TRUCTURE εox Vgs − Vfb − ψ(z)


AND dψ(r, z)
= = A2 (z) (5)
The 3-D structure of the device and its corresponding dr r =tsi εsi ′
tox
dimensions are given in Fig. 1 and Table I, respectively. The
device dimensions and parameters are according to the IRDS-
′
where tox = (tsi /2) ln(1 + (2tox /tsi )).
2020 requirements [17]. The use of Sentaurus TCAD [18] Potential at source end
was employed to simulate the work described in this study. ψ(0) = Vbi . (6)
This advanced simulator is equipped with a range of models
for various semiconductor devices in both higher and lower Potential at drain end
technology nodes. In addition to the drift-diffusion model, the ψ(L) = Vbi + Vds . (7)
simulator also includes a quantum-based model that enables
the simulation of devices at the lower technology nodes. These The oxide capacitance Cox for the GAA MOSFET can be
models are equipped with comprehensive physics to ensure expressed as follows:
greater simulation accuracy and minimize errors. The device 2ϵ1
being simulated was scaled down from 60 to 17 nm to observe Cox =  . (8)
2t
changes in its characteristics. To facilitate fabrication with tsi ln 1 + ox(effective)
tsi

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 BHOL et al.: ACCURATE DRAIN CURRENT MODEL OF MULTICHANNEL CYLINDRICAL HIGH-K HfO2 /Si3 N4 6331

In (8), tox(effective) is the effective oxide thickness and can be

written as follows:
ϵ1
 
tox(effective) = t1 + t2 (9)
ϵ2
where t1 and t2 are the thicknesses of Si3 N4 and HfO2 ,
respectively, and ϵ1 and ϵ2 are the permittivities of Si3 N4 and
HfO2 , respectively.
Solving the boundary conditions and putting the values of
all the parameters, the solution for the auxiliary equation that
will determine the surface potential of the device is expressed Fig. 2. Transfer characteristics comparison of dual-channel (stack) GAA
MOSFET simulation data with fabricated data.
as
 
z −z q Na 2
ψ(z) = X e λcyl + Y e λcyl − λcyl − (VGS − VFB ) (10)
ϵsi
where λcyl = (ϵsi tsi /4Cox )1/2 is called the natural length of
cylinder.
The minima point along the z-axis represented by z m can
be obtained as
 
1 Y
z min = λcyl ln . (11)
2 X
Thus, the surface potential at the minimum point will be
 
zm −z m q Na 2
ψ S (z min ) = X e + Y e
λcyl λcyl
− λ − (VGS − VFB ) .
ϵsi cyl
(12)
From the equation, the threshold voltage can be obtained as
 zm −z m  q Na 2
Vth = VFB + 2ψ f − X e λcyl + Y e λcyl + λ . (13) Fig. 3. Electrostatic potential distribution (a) through the channel
ϵsi cyl at lower (50 mV) and higher (0.5 V) drain bias and (b) comparison
Using the above equation, the drain current in a single channel between the surface potential curve at lower and higher drain bias (8-nm
separation).
can be formulated as
πtsi µn C ox
 
1 2
I D (z) =   Vgs − Vth Vds − Vds .


(14)
L 1 + Vds 2
LEsat potential distribution through the channel from source–channel
interface to drain–channel interface, legends are introduced
The proposed structure has multiple nanowires as channel with
along with the 3-D channel. From Fig. 3(b), it can be observed
uniform channel thickness, i.e., tsi (a) = tsi (2) = · · · = tsi (n)
that the potential developed near source is Vbi , which is the
(k = 1, 2, 3, . . . , n)
built-in potential and the potential near drain is the built-in
n
πtsi(k) µn C ox potential along with the drain voltage applied (Vbi + Vds ).
 
X 1 2
I D (z)total =  Vgs − Vth Vds − Vds . (15)



Vds 2 This article depicts the distribution of electric field across
k=1 L 1 + LEsat
the channel, with a particular focus on the value near
source/channel interface and drain/channel interface. The total
IV. R ESULTS AND D ISCUSSION electric field distribution through the channel through lower
The benefits of employing multichannel or stack GAA drain bias and higher drain bias is shown in Fig. 4(a), which
MOSFETs can be well described by comparing simulation indicates a gradual increase in the electric field from the
results to previously published experimental results [10]. The source side to the drain side. High drain bias can increase the
simulation results align well with the published experimental electric field strength and current flow through the channel
findings, showing a close convergence between them, as shown in a MOSFET, leading to improved performance, as shown
in Fig. 2. in Fig. 4(b). However, it can also cause device performance
The electrostatic potential distribution of the proposed struc- degradation, reliability issues, hot carrier injection, and DIBL.
ture having a channel separation of 8 nm is shown in Fig. 3(a) It is important to operate the device within its specified range
for higher (0.5 V) and lower (50 mV) drain bias. As the of drain bias to ensure optimal performance and reliability.
interfacial layer (Si3 N4 ) and high-K dielectric (HfO2 ) are used When the drain bias in a MOSFET is decreased, the electric
for downscaling of the device into lower technology nodes, field strength at the drain end of the channel is weakened
so the distribution of electrostatic potential on the surface compared to the electric field at the source end, as shown
beneath the high-k dielectric (interface) can be realized easily in Fig. 4(b). This reduction in the electric field is due to
through Fig. 3(a). In order to get a clear insight into the the decrease in the potential difference between the source

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 6332 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 70, NO. 12, DECEMBER 2023

Fig. 6. (a) Comparison of transfer functions for analytical model and

Fig. 4. Electric field distribution (a) through the channel at lower (50 mV) TCAD simulation. (b) Transfer characteristics of the proposed structure
and higher (0.5 V) drain bias and (b) comparison between the electric in log scale at different technology nodes.
field at lower and higher drain bias (8-nm separation).

Fig. 7. Transconductance of the proposed structure at different gate

Fig. 5. Transfer characteristics of cylindrical GAA MOSFET with lengths.
different dielectrics.

and drain terminals. As a result, the current flowing through Fig. 7. The transconductance was calculated by taking the
the channel is decreased, which adversely affects the device’s first derivative of the transfer characteristics for all gate
performance. To study the effect of downscaling on device per- lengths. Transconductance is an important figure of merit for
formance, the device gate length is reduced from 60 to 17 nm, evaluating the electrical performance of a device. A high value
and the corresponding drain current is analyzed. The transfer of transconductance indicates that a small change in gate
characteristics for different dielectric and its effect on drain voltage results in maximum drain current, leading to enhanced
current are shown in Fig. 5. From the figure, the superiority of amplification. Moreover, a higher value of transconductance
HfO2 over another dielectric can be observed easily. Fig. 6(a) results in improved voltage gain and facilitates the realization
shows the comparison between the transfer characteristics of of analog circuits operating at low supply voltage. Based
the proposed structure in the analytical model and TCAD on the data presented in Fig. 7, it can be observed that the
simulation for a gate length of 60 nm. Fig. 6(b) shows the transconductance of the devices increases as the gate length
transfer function in lower technology nodes in order to study becomes shorter. This suggests that devices with longer gate
the SCE. The graph is represented in a logarithmic form to lengths are more efficient at amplifying small signals.
calculate ON current and OFF current correctly. The simulation In order to obtain the threshold voltage of the proposed
is carried out for a gate voltage of 1 V and a drain voltage of structure in the lower technology node, the transconductance
0.05 V. The drain current versus gate voltage graph is plotted first-order derivative is taken (peak-transconductance method)
for a gate length of 17, 22, 32, and 60 nm. It is observed from and shown in Fig. 8. The transconductance change method
the figure that the ON current is almost the same for all the defines the threshold voltage as the gate voltage where
cases in the order of 10−4 on a logarithmic scale, while the OFF the derivative of the transconductance with respect to the
current is changing by ten folds for lowering down the gate gate–source voltage (dgm /d VGS ) reaches its maximum value
length. This indicates a higher switching ratio in long-channel [15], [16].
devices compared to short-channel devices. The threshold voltage for different gate lengths is shown in
Furthermore, the transconductance of the proposed device the figure for a gate voltage of 1.0 V and a drain voltage of
was investigated for different gate lengths, as shown in 0.05 V.

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 BHOL et al.: ACCURATE DRAIN CURRENT MODEL OF MULTICHANNEL CYLINDRICAL HIGH-K HfO2 /Si3 N4 6333

Fig. 10. Transfer characteristics of the proposed model in (a) linear

Fig. 8. Threshold voltage calculation from transconductance.
scale and (b) log scale with multiple channels.

TABLE II
D EVICE P ERFORMANCE A NALYSIS BY C HANGING THE
S EPARATION B ETWEEN C HANNELS

Fig. 9. Output conductance of the proposed structure at different

technology nodes.

The study indicates that the threshold voltage for the TABLE III
proposed structure varies between 0.4 and 0.5 V, depending SNM VALUES F ROM THE B UTTERFLY C URVES FOR (a) H OLD,
on the gate length. The threshold voltage is approximately (b) R EAD, AND (c) W RITE O PERATIONS OF THE
P ROPOSED S TRUCTURE
0.4 V for a gate length of 17 nm, while for a gate length
of 60 nm, it is around 0.5 V. The output characteristics of
the proposed structure were also analyzed for different gate
lengths, as shown in Fig. 9. The results indicate that, when the
gate length of a transistor is increased, the effective channel
length also increases. This is because the longer channel offers
more resistance to the movement of charge carriers (electrons
or holes), making it more difficult for them to flow from
the source to the drain. As a result, the transistor becomes arises from the complementary operation of n-type and p-type
less efficient at conducting current, and the leakage current transistors, allowing for a balanced pull-up and pull-down
between the drain and source terminals is reduced. Hence, path, thereby reducing output conductance. From the figure,
the output conductance decreases with an increase in the gate it can be observed that the proposed structure exhibits lower
length. This effect is attributed to the influence of the drain on output conductance in higher gate length compared to the
the channel, even with the use of a high-K dielectric. As the lower gate length structures and hence provides high gain,
device size is scaled down to smaller technology nodes, the as shown in Fig. 9.
drain has more control over the channel. Fig. 9 further shows The transfer characteristics of the proposed model were
the influence of the drain on the channel, indicating that this studied with multiple channels, and the results demonstrated
effect becomes more significant as the device enters minia- the superior performance of the structure for multiple channels
turization. The findings of this study suggest that designers in terms of ON current and OFF current, as shown in Fig. 10.
must consider the influence of the drain and other factors The figure clearly depicts the enhancement in dual and quad
when developing models for predicting device behavior and channels in comparison to a single channel.
optimizing performance. Higher values of output conductance The study has been extended to consider the impact of
result in lower values of output resistance, and hence, drain the placement and spacing of nanowire channels on device
current improves. There are several advantages to having a performance. It has been found that even when the number
higher output conductance. For instance, it can increase the of nanowire channels is held constant, varying the distance
stability of a circuit by minimizing the impact of parasitic between the nanowires can have a significant effect on
elements, such as capacitance and inductance. the device’s performance, as indicated by the results pre-
It is well known that the CMOS analog circuits always sented in Table II. The analysis is further extended to the
require lesser value of output conductance to attain high gain. implementation of CMOS-based 6-T SRAM cell to see the
CMOS analog circuits are favored for their ability to achieve behavior of the device in memory applications, as shown
high gain with minimal output conductance. This advantage in Fig. 11. GAA MOSFET-based SRAM offers significant

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 6334 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 70, NO. 12, DECEMBER 2023

Fig. 11. Six-transistor CMOS SRAM cell using the proposed structure.

Fig. 13. Butterfly curves for (a) hold, (b) read, and (c) write operations of
the proposed structure with a separation of 8 nm between the channels.

Fig. 12. Butterfly curves for (a) hold, (b) read, and (c) write operations of
the proposed structure with a separation of 4 nm between the channels.

advantages over traditional planar MOSFET-based SRAM

technologies. It delivers improved performance, reduced power
consumption, enhanced scalability, better leakage control,
higher memory density, improved noise immunity, and greater
reliability. The stability of an SRAM cell is commonly evalu-
ated through its static noise margin (SNM), which measures its
Fig. 14. Butterfly curves for (a) hold, (b) read, and (c) write operations
resilience to noise. The SRAM cell typically operates in three of the proposed structure with a separation of 10 nm between the
modes: write, hold, and read. During the write mode, data are channels.
written into the cell using bit lines (BLs), followed by the
hold mode, during which the cell maintains the written data.
Finally, in the read mode, the SRAM cell reads the data. The hold mode is observed for three different channel separations,
SRAM cell’s capacity to maintain data during the hold mode i.e., 4, 8, and 10 nm, respectively.
is assessed through the hold SNM (HSNM), whereas the read
SNM (RSNM) and write SNM (WSNM) are used to evaluate V. C ONCLUSION
the cell’s stability during read and write modes, respectively. This research is centered on investigating how the per-
Figs. 12–14 show the butterfly curve achieved in hold mode, formance of multichannel GAA MOSFETs is affected by
read mode, and write mode, respectively. The corresponding the incorporation of a high-K dielectric material, particularly
values are given in Table III. The hold mode is one of the hafnium oxide (HfO2 ), in both lower and higher technology
key operational modes of SRAM, alongside the write and read nodes. Extensive investigations were conducted to assess the
modes. It plays a critical role in preserving the previously writ- impact of substituting silicon dioxide with hafnium oxide on
ten data by keeping the BLs and word line at a fixed voltage. diverse performance criteria while maintaining the integrity
This ensures that the stored information remains unchanged of other device parameters. The researchers observed notable
until it is either read or overwritten, thus promoting data improvements in the drain current and other electrostatic
stability and reliability. From Figs. 12(a), 13(a), and 14(a), the characteristics when compared to conventional structures.

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 BHOL et al.: ACCURATE DRAIN CURRENT MODEL OF MULTICHANNEL CYLINDRICAL HIGH-K HfO2 /Si3 N4 6335

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