SEMESTER: Winter, SESSION: 2023-24

Examination & Semester: B. Tech., 4th Sem., Mid Semester (ECE)

Subject: Microprocessors and Microcontrollers
Time : 3 Hours Max Marks: 100

Answer all questions. (The right side numbers indicate marks.)

**Important Instructions:[Throughout the question the pins/ bits that are not in use must be considered as ‘0’s]

1. Write the content of Accumulator after executing the following instruction 2

a) SHL AX, CL
Given [AX] – B6 H (10110110)
[CX] - 0003 H
Left shift bits in AX for 3 times (assume CL = 03H); puts 0's in 3 LSB's and last MSB in 2
CF
[AX] = B0 H (considering only 8 bit)
[AX] = 05B6 H(considering 16 bit data bit)
b) SAR CX, 01
Given [CX] – B7 H (10110110)
shift bits in CX 1-bit right; puts copy of old MSB in MSB and LSB in CF;
[CX] = DB (considering only 8-bit)
[CX] = 005B H(considering 16 bit data bit)

** For both the answer, marks will be given

c) Write an assembly language program in 8086 to transfer a block of fifty 8-bit data using 6
‘LOOP’ instruction from a source with a starting memory location of 3401 H to a destination
with a starting location of 4400 H. The number of data to be transferred is to be loaded in
register CX. The 16-bit addresses mentioned here are all offset addresses.
MOV CX, 0032 H
MOV SI, 3401 H
MOV DI, 4400H
BACK: MOVSB
LOOP : BACK
INT 3

2. a) For the following program write the content of the HL register pair as well as the content of 4
4000 H and 4001 H memory locations after the execution of the program.
[Show all the steps]
LXI H 4500 H [ HL] = 4500 H
SPHL SP = 4500 H
LXI B 32FF H [BC] = 32FF H
PUSH B [SP] = 32 ; [SP+1] = 32
LXI H 1111 H [HL] = 1111 H
POP D [DE] = 32FF H
DAD D [HL] = [HL] + [DE] = 4410 H
SHLD 4000 H [4000] = 10 H; 4001 = 44 H
HLT

b) Draw the timing diagram of the following instruction showing the lower order address & 6
data bus, higher order address bus, ALE, RD, WR, and status signal]

4500H: ADD M

[The opcode of ADD M is 86 H; the content of the HL register pair is 2500 H and the content of
2500 H is 55 H]
3. a) Schematically explain the operation of any Timer/counter of 8051 Microcontroller in mode 2. 4
(2+2)

This is also same for both timer/counter. In this mode the timer/counter register TL0 or TL1 is
made an 8 bit counter with automatic reload. The timer/ counter value is loaded in the higher
bit of the timer register. The overflow of TL0/1 sets TF0/1 and it also auto reloads TL0/1 with
the content of TH0/1 which is preset by software.

b) Write a program to generate a pulse of 25% ON time and 75% OFF time using mode 3 of 6
Timer/Counter 0. Write the value of the TMOD register. The frequency of the processor and
that of the generated pulse are 2MHz and 1 KHz respectively.

T = 2MHz / 1 KHz = 200

ON delay = 50 = 32 H; OFF delay = 150 = 96 H
In mode 3 timer 0 acts as two 8 bit timer; TH0 and TL0 are loaded with two 8 bit values;
one
 Corresponding to ON delay and other for OFF delay.
If TLO is for ON and THO for OFF delay; then
TL0=FF- 32= CD H, TH0= FF – 96 = 69 H

TMOD = 0011 0011 = 33H

MOV TMOD,#33 ;Timer 0, mode 1(16-bit mode)

HERE: MOV TL0,#CD H ;TL0=CDH, the low byte
MOV TH0,#69 FH ;TH0=69H, the high byte
SET B P1.1 ; set p1.1 high
ACALL DELAY1
CLR P1.1 ; set p1.1 LOW
ACALL DELAY 2
SJMP HERE

DELAY1 : SETB TR0 ;start the lower timer 0

AGAIN : JNB TF0,AGAIN ;monitor timer flag 0 until it rolls over
CLR TR0 ;stop lower timer 0
CLR TF0 ;clear lower timer 0 flag
RET

DELAY2 : SETB TR1 ;start the higher timer 0

AGAIN1 : JNB TF1,AGAIN1 ;monitor timer flag 1 until it rolls over
CLR TR1 ;stop higher timer 0
CLR TF1 ;clear higher timer flag 1
RET

4. a) Draw an interfacing circuit for an eight-phase Stepper motor with an 8051 microcontroller. Use 4
transistor circuits as the drive circuit of the stepper motor.
 b) Write a program to rotate the motor in an anticlockwise direction with a full-step sequence 6
(excitation of two phases at a time) technique to increase the torque/ thrust.

A B C D A* B* C* D*
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Step1 1 0 0 0 0 0 0 1 81H

Step2 0 0 0 0 0 0 1 1 03 H

Step3 0 0 0 0 0 1 1 0

Step4 0 0 0 0 1 1 0 0

Step5 0 0 0 1 1 0 0 0

Step6 0 0 1 1 0 0 0 0

Step7 0 1 1 0 0 0 0 0

Step8 1 1 0 0 0 0 0 0

ORG 0000 H
MOV A, #81H
BACK: MOV P1 , A
RLA
LCALL DELAY
SJMP BACK

DELAY: MOV R1, #FF

GO DJNZ GO
RET
5. a) Write the opcode formation process of ACALL instruction. If the lower 5 digits of the opcode 5
of ACALL is (1 0001), then write all the opcodes of ACALL instruction available in 8051.

Absolute Addressing: this is only used with AJMP and ACALL instructions. The 11 least
significant bits of the destination address come from the op-code and the upper five bits are
the current upper five bits of the PC. In this addressing mode, the destination address will be
within 2K memory

Thus the eight opcodes are:

Codes from bits(A10, A9, A8) Common codes for ACALL opcode
000 10001 11 H
001 10001 31 H
010 10001 51 H
011 10001 71 H
100 10001 91 H
101 10001 B1 H
110 10001 D1 H
111 10001 F1 H

b) Write the memory location of the program counter, in which it will jump after the execution of
the following instruction. 5
6000 H: AJMP F5 H (the op-code of the AJUMP is E1 H)

Show all the address bits of the address bus and also show how they are getting the values.

PC = 6000H= 0110 0000 0000 0000

Op code= E1 = 111 0 0001> higher three bits of opcode represents A10, A9, A8

5 higher Address bits A10, A9, A8 come Lower 8

A15, A14, A13, A12, A11 from opcode bit address
0110 0 111 F5 H
Full 16 bit address = 67F5 H
6. a) Why are pull-up registers connected to the pins of Port 0 of 8051 microcontrollers for the input- 4
output operations? Draw the structure of Port 0 with the pull-up register for I/O operation.

b) How does pipelining in ARM Cortex M3 process enhance the performance of the processor? 4
Schematically discuss its pipelining technique.

Arm Cortex-M3 processor has a three-stage pipeline. There are three steps in an instruction;
instruction fetch, instruction decode, and instruction execution. In this processor, all these
functions are done in parallel. Thus it is called three-stage pipeline. When the first opcode is
fetched only fetching is done. In the 2nd instruction, fetching of the 2nd instruction and decoding
of the 1st instruction are done. When the 3rd instruction is fetched, decoding of the 2nd and
execution of the 1st instruction are done. Further, all these three steps are done in parallel. The
pipeline process of ARM cortex processor can represented schematically as shown below:

The Three-Stage Pipeline in the Cortex-M3

The three-stage pipeline allows the Cortex-M3 to overlap the execution of different instructions,
resulting in increased throughput. The three-stage pipeline is relatively simple compared to other
processors, it strikes a good balance between performance and complexity. It allows the core to
execute an instruction every cycle, leading to improved throughput. Overall the system
performance is enhanced
2
c) How does the pipelining technique in ARM Cortex M3 processor differ from that of 8086
processor?

8086 microprocessor also possesses pipelining feature. 8086 processor fetches the next instruction
while executing the current instruction12345. This technique allows multiple instructions to be
 overlapped during execution, increasing the overall instruction throughput. The process of
pipelining is done in a queue, which is filled by the Bus Interfacing Unit (BIU) until the entire
queue is full. It has two separate units; the Bus interface unit and the Execution unit. With the
help of these, a two-stage pipeline is done. Whereas in the case of the Arm cortex M3 processor 3-
stage pipeline is done as discussed above

7. (a) What value should be loaded into the TH1 register of an 8051 microcontroller with a clock 5
frequency of 12 MHz to get a baud rate of 5208 bps for serial communication? [given SMOD
=0]

TH1 = FA H

(b) Write the function of each bit of the SCON and TMOD register.
4

SCON
 (c) A message “BYE BYE” is to be displayed/transferred serially, continuously at a 5208 bps rate.
Find the value of SCON and TMOD register to implement the same. Also, write an assembly
language program.

Value of the register: TMOD = 20 H SCON = 40 H 4+

7-prog
8. An 8255 is interfaced with an 8085 microprocessor. The pins of Port B and Port C lower are connected
with digital switches, whereas the pins of Port C upper and Port A are connected with LEDs. The chip
selection of 8255 is done by a NAND gate as shown below.

a) Draw the complete interfacing circuit 4

b) Write the address of all ports and control register 4

Port A: 11110001 11111100 = F1FC H
Port B: 11110001 11111101 = F1FD H
Port C: 11110001 11111110 = F1FE H
CR: 11110001 11111111 = F1FF H
4
c) Write the function of different bits of the Control register and find the value of the control word (2+2)

CW= 10000011 = 83 H

d) Write a program to read the content of Port B and Port C lower; Add them; display the sum 8
through Port A; Display the content of Port C lower through Port C upper.

MVI A, 83H ; (PA = output, PC upper = Output, PB = Input, PC lower = Input)

STA FAFF H ; load control register port address
LDA F1FD H ; get data from Port B into acc
MOV B, A ; Save the data in B register
LDA F1FE H ; get data from Port C into acc
AND 0F H : omit upper nibble
MOV C, A ; Save the data in C register
RLC
RLC
RLC
RLC : Four RLC for nibble exchange
STA F1FE H : Display the content of port C lower through Port C upper
MOV A, C ; move the data from C to A
ADD B ; add data content of A and B
STA F1FC H : Display the sum through Port A
HLT