DESIGN OF DIFFERENT LOW POWER, HIGH PERFORMANCE CAM

CELL FOR 4 WORD 3 BITS CAM ARCHITECTURE

Project work report submitted in partial fulfillment of the requirements
for the degree of
Bachelor of Technology
in
Electronics and Communication Engineering
Submitted by

P. Harsha Vardhan (19B81A0476)

P. Naveen (19B81A0486)

K. Venkateswarlu (19B81A04B4)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CVR COLLEGE OF ENGINEERING

(An Autonomous Institution & Affiliated to JNTUH)
Ibrahimpatnam (M), Ranga Reddy (D), Telangana

2022-23
DESIGN OF DIFFERENT LOW POWER, HIGH PERFORMANCE CAM
CELL FOR 4 WORD 3 BITS CAM ARCHITECTURE
Project work report submitted in partial fulfillment of the requirements
for the degree of
Bachelor of Technology
in
Electronics and Communication Engineering
Submitted by
P. Harsha Vardhan (19B81A0476)

P. Naveen (19B81A0486)

K. Venkateswarlu (19B81A04B4)

Under the Supervision of

K. A Jysotna
Associate Professor

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CVR COLLEGE OF ENGINEERING

(An Autonomous Institution & Affiliated to JNTUH)
Ibrahimpatnam (M), Ranga Reddy (D), Telangana

2022-23
 Cherabuddi Education Society’s

CVR COLLEGE OF ENGINEERING

(An UGC Autonomous Institution with NAAC ‘A’ Grade)
(Approved by AICTE & Government of Telangana and Affiliated to JNTU, Hyderabad)
Vastunagar, Mangalpalli (V), Ibrahimpatan (M), R.R. District, Telangana – 501510
Web: http://cvr.ac.in, email: [email protected]
Ph. No:91-8414 – 661601, 661674, 661675

CERTIFICATE

This is to certify that the project work titled “DESIGN OF DIFFERENT LOW
POWER, HIGH PERFORMANCE CAM CELL FOR 4 WORD 3 BITS CAM
ARCHITECTURE” submitted to the CVR College of Engineering, affiliated to JNTUH, by P.
Harshavardhan(19B81A0476), P. Naveen (19B81A0486), K.Venkateswarlu(19B81A04B4), is
a bonafide record of the work done by the students towards partial fulfillment of requirements for
the award of the degree of Bachelor of Technology in Electronics & Communication
Engineering during the academic year 2022-2023.

Supervisor Head of the Department

K. A Jysotna Dr. K. Lalithendra

Associate Professor Head of Department
Dept. of ECE
Dept. of ECE

Project co-ordinator External Examiner

Dr.P.Hema Sree
Associate Professor
Dept. of ECE

Place:
Date:
 Cherabuddi Education Society’s

CVR COLLEGE OF ENGINEERING

(An UGC Autonomous Institution with NAAC ‘A’ Grade)
(Approved by AICTE & Government of Telangana and Affiliated to JNTU, Hyderabad)
Vastunagar, Mangalpalli (V), Ibrahimpatan (M), R.R. District, Telangana – 501510
Web: http://cvr.ac.in, email: [email protected]
Ph. No:91-8414 – 661601, 661674, 661675

DECLARATION

I hereby declare that this project report titled “DESIGN OF DIFFERENT LOW POWER, HIGH
PERFORMANCE CAM CELL FOR 4 WORD 3 BITS CAM ARCHITECTURE” submitted to the
Department of Electronics and Communication Engineering, CVR College of Engineering is a
record of original work done by me under the guidance of K.A.Jyotsna,Associate Professor. The
information and data given in the report is authentic to the best of my knowledge. This project
report is not submitted to any other university or institution for the award of any degree or diploma
or published any time before.

P. Harshavardhan (19B81A0476)
P. Naveen (19B81A0486)
K. Venkateswarlu (19B81A04B4)

Date:

Place:
 Acknowledgement

The satisfaction that accompanies the successful completion of any task would be
incomplete without the mention of the people who made it possible and whose encouragement and
guidance has been a source of inspiration throughout the course of the project.

It is great pleasure to convey our profound sense of gratitude to our principal Dr. K.
Ramamohan Reddy, Dr. K. Lalithendra, Head of the ECE Department, CVR college of
Engineering for having been kind enough for arranging the necessary facilities for executing the
project in the college.

We would like to express our sincere gratitude to our supervisor, K.A.Jyostna, Associate
Professor, ECE Dept, CVR College of Engineering, whose guidance and valuable suggestions
have been indispensable to bring about the successful completion of our project.

We wish to acknowledge special thanks to the Project Coordinator Dr.P.Hema Sree,

Associate Professor, of ECE Dept. for assessing seminars, inspiration, moral support and giving
us valuable suggestions in our project.

We would also like to express our gratitude to all the staff members and lab faculty,
department of Electronics and Communication Engineering, CVR College of Engineering for the
constant help and support.

We wish a deep sense of gratitude and heartfelt thanks to management for providing
excellent lab facilities and tools. Finally, we thank all those whose guidance helped us in this
regard.
 Abstract

The survey recent developments in the design of large-capacity content-

addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a
single clock cycle using dedicated comparison circuitry. CAM’s are especially popular in network
routers for packet forwarding and packet classification, but they are also beneficial in a variety of
other applications that require high-speed table lookup. The main CAM-design challenge is to
reduce power consumption associated with the large amount of parallel active circuitry, without
sacrificing speed or memory density. In this paper, the CAM-design techniques at the circuit level
and at the architectural level. At the circuit level, observing the low-power match-line sensing
techniques and search-line driving approaches. At the architectural level they are three methods
for reducing power consumption.

The new hardware enhances the power consumption since each

comparison of the circuitry is dynamic on each clock cycle accordingly. To achieve low power
design, some new implementations emulate the operation of CAM by utilizing different CAM cell
designs in the CAM architecture. Therefore designing novel CAM cells for low power application
in CAM architecture is a challenging task for the designer. This paper compares various CAM cell
design at 90nm for power, delay and analysis is performed in cadence virtuoso tool. Content-
addressable memory (CAM) is frequently used in applications, such as lookup tables, databases,
associative computing, and networking, that require high-speed searches due to its ability to
improve application performance by using parallel comparison to reduce search time. Although
the use of parallel comparison results in reduced search time, it also significantly increases power
consumption.
 Table of Contents

Acknowledgement 4
Abstract 5
Contents 6

Chapter 1 Overview 9

1.1 Introduction

1.2 Aim of the system

1.3 Methodology

1.4 Significance of work

1.5 Organization of work

Chapter 2 Literature Survey 11

Chapter 3 Types of Memory 16

3.1 Introduction
3.2 Volatile Memory
3.2.1 DRAM
3.2.2 SRAM
3.3 Non-Volatile Memory
3.3.1 READ ONLY MEMORY (ROM)

3.3.2 PROGRAMMABLE READ ONLY MEMORY (PROM)

 3.3.3 ERASABLE PROGRAMMABLE ROM (EPROM)

3.3.4 ELECTRICALLY ERASABLE PROM (EEPROM)

3.4 CONTENT ADDRESSABLE MEMORT (CAM)

3.5 NOR AND NAND TYPE BCAM CELLS

3.6 NOR AND NAND TYPE TCAM CELLS

3.7 XOR TYPE CAM CELL

Chapter 4 Priority Encoder 24

4.1 Implementation of Priority Encoder

4.2 Implementation of OR Gate

4.3 Implementation of Inverter

4.4 Implementation OF 3 INPUT NAND GATE

4.5 Implementation of 4 INPUT NOR GATE

Chapter 5 6-Bit Register 28

5.1 Implementation of 6-Bit Register

5.2 Implementation of 2-Input NAND GATE
5.3 implementation of D - Flip Flop

Chapter 6 Implementation of CAM Cell 31

6.1 Implementation of BCAM Cell

6.1.1 Implementation of NOR TYPE Cell

6.1.2 Implementation of NAND Type Cell

6.2 Implementation of TCAM Cell

 6.2.1 Implementation of NOR Type TCAM Cell

6.2.2 Implementation of NAND Type TCAM Cell

6.3 Implementation of XOR Type CAM Cell

6.4 Implementation of Sense Amplifier

6.5 Implementation of CAM Architecture

Chapter 7 Results 38

7.1 Simulation Result For Inverter

7.2 Simulation Result For 2 Input NAND Gate

7.3 Simulation Result For 3 Input NAND Gate

7.4 Simulation Result For 4 Input NOR Gate

7.5 Simulation Result For 2 input OR Gate

7.6 Simulation Result For Nor Type BCAM

7.7 Simulation Result For NAND Type BCAM

7.8 Simulation Result For NOR Type TCAM

7.9 Simulation Result For NAND Type TCAM

7.10 Simulation Result For XOR Type CAM

7.11 Simulation Result For Priority Encoder

7.12 Simulation Result For Sense Amplifier

7.13 Simulation Result For D – Flip Flop

 7.14 Simulation Result For 6-Bit Register

Chapter 8 Conclusion and Future Scope 44

8.1 Conclusion

8.2 Future Scope

REFERNECES 46
 LIST OF FIGURES

▪ Fig 1. DRAM circuit design 9

▪ Fig. 2. SRAM Circuit Design 15

▪ Fig. 3. NOR BCAM Cell Design 17

▪ Fig. 4. NAND BCAM Cell Design 18

▪ Fig. 5. NOR TCAM Cell Design 19

▪ Fig. 6. NAND TCAM Cell Design 20

▪ Fig. 7. XOR Type CAM Cell 21

▪ Fig. 8. Schematic of PRIORITY ENCODER 21

▪ Fig. 9. Schematic of OR Gate Circuit 22

▪ Fig. 10. Schematic of Inverter Circuit 23

▪ Fig. 11. Schematic of 3-Input NAND Gate 24

▪ Fig. 12. Schematic of 4-Input NOR Gate 25

▪ Fig. 13. Basic Schematic Design of 6-Bit Register 26

▪ Fig. 14. Schematic Design of 2-Input NAND Gate 27

▪ Fig. 15. Schematic Design of D – Flip Flop 28

▪ Fig. 16. Schematic Design of NOR TYPE BCAM Cell 29

▪ Fig. 17. Schematic Design of NAND TYPE BCAM Cell 30

▪ Fig. 18. Schematic Design of NOR TYPE TCAM Cell 31

▪ Fig. 19. Schematic Design of NAND TYPE TCAM Cell 32

▪ Fig. 20. Schematic Design of XOR TYPE CAM Cell 33

▪ Fig. 21. Schematic Design of Sense Amplifier 34

▪ Fig. 22. Schematic Design of CAM Architecture 35

▪ Fig. 23. Simulation Plot for INVERTER 36

▪ Fig. 24. Simulation Plot for 2-Input NAND Gate 37

▪ Fig. 25. Simulation Plot for 3-Input NAND Gate 38

▪ Fig. 26. Simulation Plot for 4-Input NOR Gate 39

▪ Fig. 27. Simulation Plot for 2-Input OR Gate 40

▪ Fig. 28. Simulation Plot for NOR type BCAM 41

▪ Fig. 29. Simulation Plot for NAND type BCAM 42

▪ Fig. 30. Simulation Plot for NOR type TCAM 43

▪ Fig. 31. Simulation Plot for NAND type TCAM 44

▪ Fig. 32. Simulation Plot for XOR Type CAM 45

▪ Fig. 33. Simulation Plot for Priority Encoder 46

▪ Fig. 34. Simulation Plot for Sense Amplifier 47

▪ Fig. 35. Simulation Plot for D – Flip Flop 48

▪ Fig. 36. Simulation plot for 6 – Bit Register 49

 Chapter One
Overview

1.1 Introduction
It has become the requirements of storage devices, because the computer era
drawing. In particular, this memory should be associative in nature. For practical purposes, this
memory also needs to be fast and cheap in cost. Most storage device stores and by addressing
specific memory location to retrieve the data. As a result, this path has become dependent on access
to the system flash memory constraints. To find that time is stored in a memory in the project
needed can be significantly decreased if the project can access its content by replacing its address
is recognized. Can be accessed in this way is called content-addressable memory (CAM). Thus,
content addressable memory (CAM) is one such memory is fast and intuitive.
1.2 Aim of the system

Our study focuses on minimizing power consumption of a CAM array, without

sacrificing the speed performance. For a CAM cell, there are three main parts that consume power
,Conventional CAM designs typically take up significantly more area, power, and sometimes delay
compared to location addressed memories of the same capacity.

1.3 Methodology
Content-addressable memory (CAM) is one in which it can use its contents, instead
of using the accessed memory cell storage memory. When the CAM receives input data word to
search it for the table stored in the CAM memory data word, it returns the data in which the search
word is stored in the address. The entire operation is done using active parallel circuit in a single
clock cycle. Therefore, it is very fast, only in need of high-speed applications. However, this will
consume a lot of power.
1.4 Significance of the work

Content-addressable memory (CAM) is a special type of computer memory used

in certain very high-speed searching applications. It is also known as associative memory or
associative storage and compares input search data against a table of stored data and returns the
address of the matching data.

1.5 Organization of the work

In this report,

Chapter 1 deals with a brief introduction and aim of the project.

Chapter 2 covers the Literature Survey about CAM.

Chapter 3 covers the Types of Memory.

Chapter 4 covers the Priority Encoder.

Chapter 5 covers the 6-Bit Register.

Chapter 6 covers the Implementation of CAM Cell.

Chapter 7 covers the Results.

Chapter 8 deals with the Conclusion and Future Scope.

Chapter 9 deals with References

Conclusion

This chapter dealt with the overview of the project

 Chapter Two
Literature Survey

In a new method is called block XOR-CAM way to improve the low-power precalculated
based CAM proposed efficiency. In this project, we propose an XOR block parameter extractor
for low power CAM. The project presents the theory and practice of proof to verify that the
proposed block XOR CAM can effectively reduce the number of comparison operations compare
the second part of the process to achieve greater power reduction. This means that this method is
more flexible and adaptive to the general design. In addition, the proposed block XOR-CAM bit
parallel parameter may be calculated only three XOR gate delay of any input bit length (constant
delay search operation).

In an investigation is the latest development in a large-capacity content addressable memory

(CAM) design is completed. In this article, CAM and CAM first basics of traditional architecture
review. Then the network router packet forwarding CAM applications also examined. In this
article, we have discussed CAM design technology, construction at the circuit level and reduce the
level of power of the traditional CAM. In the circuit, we have reviewed to reduce match-line
power, including selective pre-charge and pipeline technology matching line segmentation. At the
architectural level, we have examined the reduction CAM architecture bank that is counting
method includes a selection of pre-computed CAM structure and power consumption.

We propose a technique to reduce the content addressable memory (CAM) technique called
pipelining match line power consumption. In this technique, the search operation is performed by
matching lines into paragraphs pipeline sabotage. Since most of the stored word do not match on
their first portion, then the subsequent search operation is aborted segment. Accordingly, the power
will be reduced. Saving pipeline ML is the result of the activation of only a small segment matching
portion.
 In the architecture with low power consumption, low cost, low voltage, previously called
complete parallel computing-based content addressable memory (PBCAM) and high reliability.
This design is based on a pre-computed skill, to save power consumption of the CAM reduction
in the second part of the comparison process of comparing the number of passed. In this design, a
person counting method used to calculate in advance. For this, one count parameter extractor is to
use a chain full adder design, but it increases the data bit length increases the delay.The method to
reduce the power consumption of the technology available in the content-addressable memory
(cam) match line, called the selective pre-charge technique.

Since CAM compares all of its stored words concurrently, its search speed is high. However,
this comes at a cost of high energy consumption, mainly due to the high switching activity of the
ML’s. Therefore, a lot of works have been proposed to reduce the energy consumption of CAM
by reducing either the switching activity or voltage swing of the MLs. Among those designs, the
charge-injection and the pre-charge low MLSAs are the most attractive designs because of their
single-clock, high-speed and low energy characteristics. However, all of these designs have their
limitations. The charge-injection design is robust but a capacitor is associated for every ML, so
the area of the MLSA increases a lot; the pre-charge low MLSAs including the current-race, the
stability and the positive-feedback designs are very sensitive to external environment variations
including temperature and process corners. In view of that, we propose an improved MLSA design
offering a better performance in terms of energy, area, and robustness.

With strict literature investigation, it was decided to modify the architecture and design CAM
to achieve low power consumption and high-speed operation by reducing the comparison of the
number of the conventional CAM. To achieve this goal, we use an extra bit in each data word
stored in the data store. This extra bit is used as parity bits corresponding to the stored data word.
In the existing architecture of CAM, parallel to compare the contents of functions in a single clock
cycle for each CAM word (cell). Therefore, this design has to run fast, but there are a lot of power
consumption. To reduce this power consumption, there are two techniques in one word for
modifying the structure of the level comparison circuit. Although these techniques to save power,
but will increase its latency and area. Therefore, in the preconstruction level calculation method it
is proposed to reduce the number of comparators to save electricity. A method is a method of
extracting a person's number of parameters, and the other is a block XOR method.
 However, these methods take a lot of area for storing bits of these parameters and their
extraction. They must also extract and search operation parameters via the parameter memory,
although it reduces the power consumption data comparison of power loss. Thus, based on this
approach, we have decided to adopt a parity bit as arguments than previous PB-CAM it just a bit-
storage parameters, and reduce the number of comparison operations to reduce power consumption
and improve the ratio of performance to achieve PB-CAM Traditional CAM.
 Chapter Three

Types Of Memory

2.1 INTRODUCTION

In computing, memory refers to the computer hardware devices used to store information for
immediate use use in a computer, it is synonymous with the term "primary storage". Computer
memory operates at a high speed, for example Random-Acess memory (RAM), as a distinction
from storage that provides slow to access program and data storage but offers higher capacities. If
needed, contents of the computer memory can be transsferred to secondory storage, through a
memory management technique called "virtual memory". An archaic synonym for memory is
store.

The term "memory". meaning "primary storage" or "main memory", is often associated with
addressable semiconductor memory, i.e. integrated ciecuits consisting of silicon based transistors,
used for exampleas primary storage but also other purpose in comuters and other digital electronic
devices, there are two main kinds of semiconductor type memory, volatile and non-volatile. Some
examples of non-volatile memory are ROM,PROM,EPROM and EEPROM memory(which is
used for storing firmware such as BIOS). Examples of volatile memory are primary storage, which
is typically Dynamic Random-access memory (DRAM), and fast CPU cache memory, which is
typically static Random-access memory(SRAM) that is fast but energy-consuming, offering lower
memory areal density than DRAM.

Flash memory organisation include both one bit per memory cell and multiples bits per cell
(called MLC, Multiple Level Cell). The memory cells are grouped into words of fixed word length,
for example 1,2,4,8,16,32,64 or 128 bit. Each word can accessed by a binary of N bit, making it
possible to store 2 raised by N words in the memory. This implies that processor registers normally
are not considered as memory, since they only store one word and do not include addressing
mechanisim.

Typically secondary storage devices are hard disk drives and solid-state drives.
2.2 VOLATILE MEMORY
Volatile memory is computer memory that requires power to maintain the stored information. Most
modern semiconductor volatile memory is either Static RAM (see SRAM) or dynamic RAM. SRAM
retains its contents as long as the power is connected and is easy to interface to but uses six
transistors per bit.

Dynamic RAM is more complicated to interface to and control and needs regular refresh cycles
to prevent its contents being lost. However, DRAM uses only one transistor and a capacitor per
bit, allowing it to reach much higher densities and, with more bits on a memory chip, be much
cheaper per bit. SRAM is not worthwhile for desktop system memory, where DRAM dominates,
but is used for their cache memories. SRAM is commonplace in small embedded systems, which
might only need tens of kilobytes or less. Forthcoming volatile memory technologies that hope to
replace or compete with SRAM and DRAM include Z-RAM, TTRAM, A-RAM and ETA RAM.

2.2.1 DRAM

Dynamic random-access memory (DRAM) is a type of random accesssemiconductor memory

that stores each bitof data in a memory cellconsisting of a tiny capacitorand a transistor, both
typically based on metal-oxide-semiconductor(MOS) technology. The capacitor can either be
charged or discharged; these two states are taken to represent the two values of a bit.
conventionally called 0 and 1. To prevent this, DRAM requires an external memory refreshcircuit
which periodically rewrites the data in the capacitors, restoring them to their original charge.
Unlike flash memory, DRAM is volatile memory (vs.non-volatile memory), since it loses its data
quickly when power is removed.

Fig 1 : DRAM Cell Design

 2.2.2 SRAM
Static random-access memory (static RAM or SRAM) is a type of semiconductor random-
access memory (RAM) that uses bistable latching circuitry (flip-flop)to store each bit. SRAM
exhibits data remanence but it is still volatile in the conventional sense that data is eventuallylost
when the memory is not powered.

The term static differentiates SRAM from DRAM(dynamic random-access memory) which
must be periodically refreshed. SRAM is faster and more expensive than DRAM; it is typically
used for CPU cachewhile DRAM is used for a computer's main memory.

Fig 2 : SRAM Cell Design

2.3 NON-VOLATILE MEMORY

It is the type of memory in which data or information remains keep within the memory albeit
power is completed. ROM (Read Only Memory)is the most common example of non-volatile
memory, it's not that a lot of economical and quick in nature as compare to volatile memory
however stores information for the longer amount. Non-volatile memory is slow concerning
accessing. All such information that must be hold on for good or for a extended amount is hold on
in non-volatile memory. Non-volatile memory has a huge impact on a system's storage capacity.
 2.3.1 READ ONLY MEMORY (ROM)
ROM stands for Read Only Memory. The memory from which we can only read
but cannot write on it. This type of memory is non-volatile. The information is stored permanently
in such memories during manufacture. A ROM stores such instructions that are required to start a
computer. This operation is referred to as bootstrap. ROM chips are not only used in the computer
but also in other electronic items like washing machine and microwave oven.

2.3.2 PROGRAMMABLE READ-ONLY MEMORY (PROM)

It stands for Programmable Read-Only Memory. It is first prepared as blank
memory, and then it is programmed to store the information. The difference between PROM and
Mask ROM is that PROM is manufactured as blank memory and programmed after manufacturing,
whereas Mask ROM is programmed during the manufacturing process. To program the PROM, a
PROM programmer or PROM burner is used. The process of programming the PROM is called as
burning the PROM. Also, the data stored in it cannot be modified, so it is called as one-time
programmable device.

2.3.3 ERASABLE PROGRAMMABLE ROM (EPROM)

It stands for Erasable Programmable Read-Only Memory. It overcomes the
disadvantage of PROM that once programmed, the fixed pattern is permanent and cannot be
altered. If a bit pattern has been established, the PROM becomes unusable, if the bit pattern has to
be changed .This problem has been overcome by the EPROM, as when the EPROM is placed
under a special ultraviolet light for a length of time, the shortwave radiation makes the EPROM
return to its initial state, which then can be programmed accordingly. Again for erasing the content,
PROM programmer or PROM burner is used.

2.3.4 ELECTRICALLY ERASABLE PROM (EEPROM)

It stands for Electrically Erasable Programmable Read-Only Memory. It is similar
to EPROM, except that in this, the EEPROM is returned to its initial state by application of an
electrical signal, in place of ultraviolet light. Thus, it provides the ease of erasing, as this can be
done, even if the memory is positioned in the computer. It erases or writes one byte of data at a
time.

2.4 CONTENT ADDRESSABLE MEMORY (CAM)

Also known as "associative storage," content-addressable memory is a chip that provides fast
table lookups, most notably in network routers and switches. For example, Internet routers search
a lookup table millions of times per second to find the appropriate port to output packets to. When
a set of search data is presented to content-addressable memory, the memory hardware delivers
the results in one clock cycle.

Content-addressable memory (CAM) is constructed of SRAM cells but is considerably more

expensive and holds much less data than regular SRAM chips Depending on the distribution of
characters in a given set of data, lookup tables may be designed to find the data from the address.
CAM is used in an opposite manner to find the address from the data. Depending on the distribution
of characters in a given set of data, lookup tables may be designed to find the data from the address.

CAM is used in an opposite manner to find the address from the data Binary CAM requires
an exact match, while ternary CAM uses the X bit (don't care bit) for a wild card match. With
ternary CAM, the address that matches the most bits is the one selected. This is known as "longest-
prefix matching," the routing table lookup method of the Internet protocol.

Content-addressable memories (CAMs) provide a performance advantage over conventional

RAM based memory search algorithms by comparing the desired information against the prestored
entries simultaneously. This results in an order of magnitude reduction in search time. Since
CAMS are an outgrowth of RAM technology, they employ conventional memory (usually SRAM)
with the additional circuitary for comparisons that enable search operations to complete in a single
clock cycle.

In RAM, data are stored at a particular location called address. A user supplies the address
in order to retrieve the data. With CAM, the user supplies the data and gets the address back. The
CAM searches through the memory in one clock cycle and returns the address where the data are
found. An obvious question is, how to store the data in the first place? Data can be transferred to
or from a CAM without knowing the memory address. Binary data are automatically written to the
next free location.

With CAMS, a longest prefix matching operation on a 32 bit IPv4 addresscan be performed
using an exact match search in 32 separate CAMS. The incoming IP address is given as input to
all the CAMS. The output of the CAMS indicating the results of the match is fed through a priority
encoder that picks the CAM that has the longest matching prefix. Such a solution is expensive both
in terms of cost and complexity.

Hence, a more flexible type of CAM that enables comparisons of the input key with variable
length elements is desirable. Ternary CAMS were introduced to address this need. While a binary
CAM stores one of two states 0 and 1 for each bit in a memory location, a ternary CAM (TCAM)
stores one of the three states 0, 1, and X (don't care) for each bit in a memory location. The don't
care state permits search operations beyond the exact match.

A TCAM stores an element as a pair: a value and a mask, where each of them is the same
length. The value field stores the actual value of the prefix and the mask field is used to denote the
length of the element. Let us see how this works. If a prefix is Y bits long, the most significant Y
bits of the value field are assigned the same value as that of the prefix, and the remaining bits are
set 0 or 1 or X. The most significant Y bits of the mask field are set to 1 and the remaining bits are
set to 0. Thus, the mask bits indicate which bits in the value field are relevant. For example, a
prefix of 110 will be stored as (110XXX,111000) assuming the elements are 6 bits long. The
prefixes are stored in TCAM. Note that the prefixes are stored in descending order of their lengths.
An incoming key matches a stored element, if the bits of the value field for which the mask bit is
1 are identical to those in the incoming key.

2.5 NOR AND NAND TYPE BCAM

NOR BCAM cell is shown in Figure 3 In this cell bits 0or 1 are stored with the help of SRAM
structure in D andDbar. The comparison between the store bit and search bit is performed using
four comparison transistors T1 through T4.The transistors, T1/T3, and T2/T4 forms two separate
pulldown paths for the match line ML . To operate the cell first precharge the match line this is
initially in high. Then starts the evaluation phase, here search input is compared with the stored
bit. If there is a miss-match between the search bit and store bit match line starts discharging to
zero quickly because of short pull-down paths. If there is a match then match line retain the logic
high as in precharge phase. The disadvantage of BCAM NOR cell is power inefficient because
pull down transistors arrangement in this cell type contributes more drain capacitance to the match
line.

Fig 3 : NOR BCAM Cell Design

NAND BCAM cell is shown in Figure 4. Bits stored in NAND BCAM cell is with the help of
SRAM structure. Comparison in NAND BCAM cell is performed by using three transistors T1,
TD1, TD2. NAND BCAM cell consumes less power because of low load capacitance to the match
line but results from high delay because of their long pull down paths . The main purpose of CAM
is to design thearchitecture with low power consumption without degrading the performance.
Therefore normally NOR type BCAM cell is preferred when designing cells in CAM architecture
because of their low delay, even in the worst case NOR has a better delay than NAND.

Fig 4 : NAND BCAM Cell Design

2.6 NOR AND NAND TYPE TCAM CELLS

TCAM is encoded into two bits D and Dbar which need not be complementary. These two
bits are connected to pull down path independently. Second SRAM is used in TCAM NOR cell
design to store a ternary value as shown in Figure 5. TCAM NOR cell stores X value by setting D
and Dbar to logic 1 which forces the NOR cell to match by disconnecting both pull down paths
from the ground despite the inputs. Searching for an X in TCAM NOR cell is possible by setting
SL and SLbar to logic low .

Fig 5 : TCAM NOR Type Cell Design

 In TCAM NAND cell, for ternary storage, basic NAND CAM cell is modified by adding a
mask bit N is shown in Figure.6. Mask bit 1 allow setting the TCAM NAND cell to store X, which
forces mask transistor N ON, whatever the value of D. TCAM NAND cell allows a search for an
X by setting both differential search line pairs to logic 1

Fig 6 : TCAM NAND Type Cell Design

2.7 XOR TYPE CAM CELL

Basic CAM cell consists of both store unit for storing the data and compare unit for comparing
the data. Data is stored in two cross coupled inverters. The two NMOS transistors controlled by
the word line allow the CAM to be written. The three additional transistors used for matching.
Hence, this cell performs READ and WRITE Operations similar to an SRAM cell. Third operation
is search operation. In Different applications the compare unit can be designed with XOR type.
The main operation of CAM cell can be described as: when the cross coupled inverters store the
data 1 and then the bit and nbit (bit bar/bit) line has the data 1 and 0 respectively. Now one of the
two pull down transistors will be ON state and the other will be OFF state so that there won't be
any transistor path to discharge the match line and hence it remains in High-impedance state. Now
if the bit and nbit line has the data 0 and 1 respectively, then in the compare unit one of the pull
down transistor will be in ON state so that the fast pull down transistor moves to ON state. This
discharges the match line indicating that the data have been matched.
Fig 7 : XOR CAM Cell Design
 Chapter Four
Priority Encoder
4.1 IMPLEMENTATION OF PRIORITY ENCODER

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a
smaller number of outputs. The output of a priority encoder is the binary representation of the
original number starting from zero of the most significant input bit. Binary Encoder converts one
of 2n inputs into an n-bit output. It has fewer output bits than the input code. The Priority Encoder
is another type of combinational circuit similar to a binary encoder, except that it generates an
output code based on the highest prioritized input.
The figure (8) shown below is the basic schematic of the priority encoder:
The priority encoder consists of the following components:

1. OR GATES
2. 4 INPUT NOR GATE
3. 3 INPUT NAND GATE
4. INVERTER
All these components together are used to design the schematic of the priority encoder, below is
the diagram of the wave forms obtained from the test bench of the priority encoder

4.2 IMPLEMENTATION OF OR GATE

The OR gate is a digital logic gate that implements logical disjunction. a HIGH output (1) results
if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0) results.
In another sense, the function of OR effectively finds the maximum between two binary digits,
just as the complementary AND function finds the minimum.

Fig 9 : Schematic Diagram of OR gate

4.3 IMPLEMENTATION OF INVERTER

An inverter circuit outputs a voltage representing the opposite logic-level to its input. Its main
function is to invert the input signal applied. If the applied input is low then the output becomes
high and vice versa. Inverters can be constructed using a single NMOS transistor or a single
PMOS transistor.
 Fig 10 : Schematic Design Of Inverter

4.4 IMPLEMENTATION OF 3 INPUT NAND GATE

The NAND (Not-AND) gate has an output that is normally at logic level "1" and only goes
"LOW" to logic level "0" when all of its inputs are at logic level "1". The Logic NAND Gate is
the reverse or "Complementary" form of the AND gate we have seen previously.

As with the AND function seen previously, the NAND function can also have any number of
individual inputs and commercial available NAND Gate IC's are available in standard 2, 3, or
4 input types.
 Fig 11 : Schematic Design of 3 Input NAND Gate

4.5 IMPLEMENTATION OF 4 INPUT NOR GATE

The inclusive NOR (Not-OR) gate has an output that is normally at logic level "1" and only
goes "LOW" to logic level "0" when ANY of its inputs are at logic level "1". The Logic NOR Gate
is the reverse or "Complementary" form of the inclusive OR gate we have seen previously.

The Boolean Expression for this 4-input NOR gate will therefore be : Q=A+B+C+D If the
number of inputs required is an odd number of inputs any "unused" inputs can be held LOW by
connecting them directly to ground using suitable "Pull-down" resistors.

The Logic NOR Gate function is sometimes known as the Pierce Function and is denoted by
downwards arrow operator as shown A ↓ B.
Fig 12 : Schematic Design of 4 Input NOR Gate
 Chapter Five
6-Bit Register
5.1 IMPLEMENTATION OF 6-BIT REGISTER

Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase
the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group
of flip-flop is known as a Register. The 6-bit register will consist of 6 number of flip-flop and it
is capable of storing an 6-bit word. The binary data in a register can be moved within the register
from one flip-flop to another.

A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each
data bit. The output from each flip-Flop is connected to the D input of the flip-flop at its right.
Shift registers hold the data in their memory which is moved or “shifted” to their required positions
on each clock pulse.
The figure (13) shown below is the basic schematic of the 6-Bit Register:
The 6-Bit Register consists of the following components:

1. 2 INPUT NAND GATE

2. D-FLIP FLOP
3. INVERTER
All these components together are used to design the schematic of the 6-Bit Register, below is
the diagram of the wave forms obtained from the test bench of the 6-Bit Register.

5.2 IMPLEMENTATION OF 2 INPUT NAND GATE

The NAND gate has an output that is normally at logic level “1” and only goes “LOW” to
logic level “0” when ALL of its inputs are at logic level “1”. The Logic NAND Gate is the reverse
or “Complementary” form of the AND gate. By De Morgan's laws, a two-input NAND gate's logic
may be expressed as (A • B)bar = A(bar)+B(bar), making a NAND gate equivalent to inverters
followed by an OR gate. By using only NAND gates, we can realize all logic functions: AND, OR,
NOT, Ex-OR, Ex-NOR, NOR. So this gate is also called as universal gate.

Figure 14 : Schematic Design of 2 Input NAND Gate

5.3 IMPLEMENTATION OF D-FLIP FLOP
Flip-flop is a circuit that maintains a state until directed by input to change the state. A basic
flip-flop can be constructed using four-NAND or four-NOR gates. The D flip flop is the most
important flip flop from other clocked types. It ensures that at the same time, both the inputs, i.e.,
S and R, are never equal to 1. The Delay flip-flop is designed using a gate SR Flip Flop with an
inverter connected between the inputs allowing for a single input D(Data).

In D flip flop, the single input "D" is referred to as the "Data" input. When the data input is set to
1, the flip flop would be set, and when it is set to 0, the flip flop would change and become reset.
The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from the flip
flop's latching circuitry. When the clock input is set to true, the D input condition is only copied
to the output Q.

Figure 15 : Schematic Design of D – Flip Flop

 Chapter Six
Implementation Of CAM Cells
6.1 IMPLEMENTATION OF BCAM CELL
BCAM cell uses single SRAM circuit for bit storage (0 or 1). The bit comparison in CAM
cell design is logically equivalent to XOR or XNOR of the stored bit and search bit. The transistors
in the comparison circuitry are designed with typically minimum sized to maintain high cell
density

6.1.1 IMPLEMENTATION OF NOR TYPE BCAM CELL

In this cell bits 0 or 1 are stored with the help of SRAM structure in D and Dbar. The
comparison between the store bit and search bit is performed using four comparison transistors T1
through T4. The transistors, T1/T3, and T2/T4 forms two separate pull down paths for the match
line ML. To operate the cell first precharge the match line this is initially in high. Then starts the
evaluation phase, here search input is compared with the stored bit. If there is a miss-match
between the search bit and store bit match line starts discharging to zero quickly because of short
pull-down paths. If there is a match then match line retain the logic high as in precharge phase.

Figure 16 : Schematic of NOR Type CAM CELL

 6.1.2 IMPLEMENTATION OF NAND TYPE BCAM CELL
Bits stored in NAND BCAM cell is with the help of SRAM structure. Comparison
in NAND BCAM cell is performed by using three transistors T1, TD1, TD2. NAND BCAM cell
consumes less power because of low load capacitance to the match line but results from high delay
because of their long pull down paths. The main purpose of CAM is to design the architecture with
low power consumption without degrading the performance.

Fig 17 : Schematic Design of NAND Type BCAM Cell

6.2 IMPLEMENTATION OF TCAM CELL

TCAM cell uses Two SRAM cells to store ternary value dont care X other than 0 or 1. CAM
operation is performed in two stages precharge phase and evaluation phase. CAM cell operation
begins with loading the search input through search lines followed by pre-charging match line,
once the match line is pre-charge it temporarily disconnects match line from ground.

6.2.1 IMPLEMENTATION OF NOR TYPE TCAM CELL

TCAM is encoded into two bits D and Dbar which need not be complementary. These
two bits are connected to pull down path independently. Second SRAM is used in TCAM NOR
cell design to store a ternary value as shown in Figure.6. TCAM NOR cell stores X value by setting
D and Dbar to logic 1 which forces the NOR cell to match by disconnecting both pull down paths
from the ground despite the inputs. Searching for an X in TCAM NOR cell is possible by setting
SL and SLbar to logic low.

Fig: 18 Schematic of NOR Type TCAM Cell

6.2.2 IMPLEMENTATION OF NAND TYPE TCAM CELL

In TCAM NAND cell, for ternary storage, basic NAND CAM cell is modified by
adding a mask bit N is shown in Figure.7. Mask bit 1 allow setting the TCAM NAND cell to store
X, which forces mask transistor N ON, whatever the value of D. TCAM NAND cell allows a
search for an X by setting both differential search line pairs to logic 1.
 Fig 19 : Schematic of NAND TYPE TCAM CELL

6.3 IMPLEMENTATION OF XOR TYPE CAM CELL

This modified 4T CAM cell design consists of 4 nmos transistors and the cells are arranged
such that the two transistors are used to store the data and the remaining two transistors are used
to write the data. The gates of and are used as storage capacitance elements so that it can be used
to store the data.

The Conventional Search operation is performed in three steps. 1)Search lines or bit lines i.e
b and bbar are reset to GND. 2)Matchline is precharged to Vdd and 3) Finally, the search key bits
and its complementary value are placed on b and bbar respectively, with write disabled.If the
search key bit is identical to the stored value, ml–to-gnd pull-down paths remain „OFF‟, and the
ml remains at VDD,indicating a “match”. Otherwise, if the search key bit is different from the
stored value, one of the pull-down paths conducts and discharges the ml to gnd indicating a
“mismatch”.
 Resetting b and bbar to gnd before ml pre-charge phase ensures that both pull-down paths are
„OFF‟, and hence do not conflict with the ml precharging. Fig ffvf shows the search operation
when 0 is stored in the cell. For b = „1‟ (bbar = „0‟), ml is discharged to „0‟ detecting “mismatch”,

Similarly for BL=‟0‟,ML remains at „1‟ detecting “match”.

Fig 20 : Schematic Design of XOR CAM CELL

6.4 IMPLEMENTATION OF SENSE AMPLIFIER

The sense-amplifier shown in fig tuj is of two differential inputs and asymmetrical differential
amplifer. The operation of this sense amplifier is in three phases stand by,excitation and evaluation.
During standby bit and bitbar are discharged to ground. Meanwhile EN signal is asserted high.
During excitation SE is charged to certain level from the pulse generator as During evaluation, the
search data on bit is compared with stored data. In match-case the Y is discharged to ground and
in mismatch-case Y.
 The function of the sense amplifier is, in this case, that of allowing for a quick reading of the
differential signal on the bit lines, so that the discharging process can be stopped as soon as
possible, to the advantage of speed and power consumption.

Fig 21 : Schematic Design of Sense Amplifier

6.5 IMPLEMENTATION OF CAM ARCHITECTURE

CAM performs three basic operations reading, writing and comparing. CAM is intended to
search his whole memory in a single operation. CAM compares table of stored data with the input
search data and returns the matching address of lookup data to the encoder. CAM architecture
consists of an array of CAM cells, match lines, search lines, match line sense amplifier and an
encoder is shown in Figure 1. CAM cell are of two types ternary content addressable memory
(TCAM) and binary content addressable memory (BCAM).
 CAM cells are designed to store and search lookup table data within a single clock cycle.
BCAM cell uses single SRAM circuit for bit storage (0 or 1), TCAM cell uses Two SRAM cells
to store ternary value dont care X other than 0 or 1. CAM operation is performed in two stages
precharge phase and evaluation phase. CAM cell operation begins with loading the search input
through search lines followed by pre-charging match line, once the match line is pre-charge it
temporarily disconnects match line from ground. Next, search data is broadcast through search
line to compare with the store data. While comparing stored bit and the search bit if there is a
match indicates match state then match line isolated from the discharge discharge path otherwise
it indicates miss state then match line connected to ground.

Fig 22 : Schematic Design of CAM (4X3) Architecture

 Chapter Seven
Results
7.1 SIMULATION RESULT FOR INVERTER
Below is the diagram showing the output waveform of the proposed Inverter.

Figure 23 : The output Waveform for INVERTER

7.2 SIMULATION RESULT FOR 2 INPUT NAND GATE

Below is the diagram showing the output waveform of the proposed 2 Input Nand Gate.

Figure 24 : The output Waveform for 2 INPUT NAND GATE

7.3 SIMULATION RESULT FOR 3 INPUT NAND GATE
Below is the diagram showing the output waveform of the proposed 3 Input Nand Gate.

Fig 25 : The output Wave-Form for 3 input NAND Gate

7.4 SIMULATION RESULT FOR 4 INPUT NOR GATE

Below is the diagram showing the output waveform of the proposed 4 Input Nor Gate.

Figure 26 : The Output wave-form of 4 Input NOR Gate

7.5 SIMULATION RESULT FOR 2 INPUT OR GATE
Below is the diagram showing the output waveform of the proposed 2 Input Or Gate.

Fig 27 : The output Waveform for 2 INPUT OR Gate

7.6 SIMULATION RESULT FOR NOR TYPE BCAM

Below is the diagram showing the output waveform of the proposed Nor Type BCAM.

Fig 28 : The output Waveform for NOR Type BCAM Cell

7.7 SIMULATION RESULT FOR NAND TYPE BCAM
Below is the diagram showing the output waveform of the proposed Nand Type BCAM.

Fig 29 : The Output Waveform for NAND Type BCAM

7.8 SIMULATION RESULT FOR NOR TYPE TCAM

Below is the diagram showing the output waveform of the proposed Nor Type TCAM.

Fig 30 : The output Waveform for NOR TYPE TCAM

7.9 SIMULATION RESULT FOR NAND TYPE TCAM
Below is the diagram showing the output waveform of the proposed Nand Type TCAM.

Fig 31 : The output Waveform for NAND TYPE TCAM

7.10 SIMULATION RESULT FOR XOR TYPE CAM

Below is the diagram showing the output waveform of the proposed Xor Type CAM.

Fig 32 : The Output Waveform for XOR Type CAM

7.11 SIMULATION RESULT FOR PRIORITY ENCODER
Below is the diagram showing the output waveform of the proposed Priority Encoder.

Fig 33 : The output Waveform for Priority Encoder

7.12 SIMULATION RESULT FOR SENSE AMPLIFIER

Below is the diagram showing the output waveform of the proposed Sense Amplifier.

Fig 34 : The output Waveform for Sense Amplifier

7.13 SIMULATION RESULT FOR D-FLIP FLOP
Below is the diagram showing the output waveform of the proposed D-FlipFlop.

Fig 35 : The output Waveform for D-FLIPFLOP

7.14 SIMULATION RESULT FOR 6-BIT REGISTER

Below is the diagram showing the output waveform of the proposed 6-Bit Register.

Fig 36 :The output Waveform for 6 bit register

 Chapter Eight
Conclusion And Future Scope
8.1 CONCLUSION
A new XOR CAM Cell 4T have been designed. The various design of CAM Cell and
proposed XOR CAM is simulated with a 90nm CMOS technology. Further the energy (power-
delay product) saved through this circuit is more when compared to the Existing circuit has shown
in the table. Therefore the proposed design can be use in low power application of CAM. we have
surveyed CAM circuits and architectures, with an emphasis on high-capacity CAM. First, we
motivated our discussion by showing how CAMS can be applied to packet forwarding in network
routers. At the circuit level, we have reviewed the two basic CMOS cells, namely the NOR cell
and the NAND cell. We have also shown how the cells are combined in a matchline structure to
form a CAM word.

In this paper, we have surveyed CAM circuits and architectures, with an emphasis on high-capacity
CAM. At the circuit level, we have reviewed the two basic CMOS cells, namely the BCAM and
TCAM type NOR cell and the NAND cell , XOR cell. Different CAM cell is analyzed for power
and delay using cadence virtuoso tool at 90nm. Supply voltage 1.2V and operating frequency
100(MHz) is used for all the CAM cell structures.

The Content Addressable Memory (CAM) is designed and implemented in existing CAM XOR
Array and 90 nm based CAM XOR Array. The average power consumption and number of
transistor count should be reduced by proposed CAM XNOR Array and 90 nm Based CAM XNOR
Array. It will be having much reduced power when compared to the other two designs.

8.2 FUTURE SCOPE

From the CAM structures mentioned above, a new architecture was proposed which increases
the speed of the searching operation. As mentioned above, we are not using a word line in the
search word is same for all rows and for inducing the search bit. In the future, we can reduce more
power as compared to power and delay results of proposed design. To reduce the results, we can
use lower technology than 130nm. We can also work on reducing the area of CAM. Work can also
be done on extending these CAM architecture designs to T-CAM.
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