SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE

DIGITAL COMPUTER ORGANIZATION

BCA – SEMESTER – II

UNIT – 4
Memory Units
SEQUENTIAL CIRCUITS (NOT IN SYLLABUS, only for understanding)
o A sequential circuit is an interconnection of combinational circuits and storage elements.
The circuit which output is depends not only on present input but also on past input and
internal state (Previous output).
o Sequential circuit has a state table / characteristics table (like truth table in
combinational circuit). State table gives the past, current and future states at the output.
o It uses memory element/storage elements, called flip-flop, which stores binary
information that indicates the state of sequential circuit.
o These sequential circuits unlike combinational circuits are time dependent. The
sequential circuits are broadly classified, depending upon the time at which these are
observed and their internal state changes.

[Block Diagram of Sequential Circuit]

o State of the sequential circuits, Binary information stored in the storage element at any
given time. Sequential circuit is specified by a time sequence of inputs, internal states,
and outputs.

➢ There are two types of sequential circuits. Their classification depends on the timing of
their signals:
1. Synchronous sequential circuit
– This type of system uses storage elements called flip-flops that are employed
to change their binary value only at discrete instants of time.
– Synchronous sequential circuits use logic gates and flip-flop storage devices.
Sequential circuits have a clock signal as one of their inputs.
– All state transitions in such circuits occur only when the clock value is either 0
or 1 or happen at the rising or falling edges of the clock depending on the type
of memory elements used in the circuit.
– Synchronization is achieved by a timing device called a clock pulse generator.
Clock pulses are distributed throughout the system in such a way that the flip-
flops are affected only with the arrival of the synchronization pulse.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

– Synchronous input – (i). Edge +ve or –ve defines the instance at which input
affects the output and transition is to next state. +ve edge means transition at
input from 0 to 1. –ve edge means transition at input from 1 to 0.
–
2. Asynchronous sequential circuit
– The inputs at any instant of time
– The order in continuous time in which the inputs change
– This is a system whose outputs depend upon the order in which its input
variables change and can be affected at any instant of time.
– Gates-type asynchronous systems are basically combinational circuits with
feedback paths. Because of the feedback among logic gates, the system may,
at times, become unstable. Consequently, they are not often used.

Latches and Flip-Flops

• Gates are the building blocks of combinatorial circuits, latches and flip-flops are the
building blocks of sequential circuits.
• While gates had to be built directly from transistors, latches can be built from gates, and
flip-flops can be built from latches.
• Both latches and flip-flops are circuit elements whose output depends not only on the
current inputs, but also on previous inputs and outputs. The difference between a latch
and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always
does.
• A Latch / Flip Flop circuit can maintain a binary state 1 or 0 indefinitely (as long as
power is switched off) until directed by an input signal to switch states.
• A Latch / flip flop is said to be in state SET 1 when flip flop output is 1. When flip flop
output is 0, it is said to be in CLEAR / RESET state.
• The major difference among various types of flip flops is in the number of inputs they
passes and in the manner in which the inputs affect the binary state.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

Latches
• Latch is feed-back, which means that we create loops in the circuit diagrams so that
output values depend, indirectly, on themselves. If such feed-back is positive then the
circuit tends to have stable states, and if it is negative the circuit will tend to oscillate
(switching state).
• A latch has positive feedback

Flip Flop
• A flip flop circuit can maintain a binary state 1 or 0 indefinitely (as long as power is
switched off) until directed by an input signal to switch states.
• A flip flop is said to be in state SET 1 when flip flop output is 1. When flip flop output is
0, it is said to be in CLEAR / RESET state.
• The major difference among various types of flip flops are in the number of inputs they
passes and in the manner in which the inputs affect the binary state.

• Types of Flip flops

1. Direct coupled R.S. Flip Flop/ S.R. Latch (Asynchronous) / Basic Flip Flop
2. Clocked R.S. Flip Flop / RS Flip Flop
3. Clocked J.K. Flip Flop / JK Flip Flop
4. Clocked D Flip Flop / D Flip Flop
5. Clocked T Flip Flop / T Flip Flop

1. SR Latch/Basic Flip Flop/Direct Coupled RS Flip Flop

o This latch is called SR-latch, which stands for Set and Reset.
o The SR-latch is meant to have at most one of its inputs equal to 1 at any time. When both
of its inputs are 0 it has two different stable states possible.
o This is a simplest circuit. This Latch can be constructed from two NAND gates or two
NOR gates. These constructions are shown in the logical diagram.
o Each circuit forms a basic flip flop upon which other more complicated types can be
built.
o The cross coupled connection from the output of one gate to the input of the other gate
constitutes a feedback path. For this reason, the circuits are classified as asynchronous
sequential circuit.
o Each has two input Set and Reset and two outputs, Q and Q’. This type of latch / flip –
flop is sometimes called Direct Coupled RS Flip Flop or SR latch.
o The R and S are first letters of the two input names.

SR Latch (Using NOR gates)

• An SR Latch is the simplest possible memory element.
• It is constructed by feeding the outputs of two NOR gates back to the other NOR gate
input.
• The inputs R and S are referred to as the Reset and Set inputs, respectively.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

• The output of NOR gate is 0, if any input is 1. The application of 1 to set causes flip flop to
go to SET value.
• The SET input must go to 0 before 1 is applied to Reset.

➢ Graphical Symbol (Standard Symbol) Decision Table

S R Decision
R Q
SR Latch 0 0 No Change
1 0 Set (Q=1)
S Q’ 0 1 Reset (Q=0)
1 1 Indeterminate/
Undefined

➢ Logic Diagram Truth Table / Characteristics Table

S R Q Q’
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1  

[RS flip flop using 2 NOR gates]

Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

• To understand the operation of the SR - latch consider the following scenarios:

• Here Q and Q’ feed back into the circuit. They’re not only outputs, they’re also inputs!
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

o S=0 and R=0:

The equations on the right reduce to:
Qnext = (0 + Q’current)’ = Qcurrent
Q’next = (0 + Qcurrent)’ = Q’current

So when SR = 00, then Qnext = Qcurrent. Whatever value Q has, it keeps.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

o S=1 and R=0:

• Q’next = (1 + Qcurrent)’ = 0 Then, this new value of Q’ goes into the top NOR gate,
along with R = 0.
Qnext = (0 + 0)’ = 1
So when SR = 10, then Q’next = 0 and Qnext = 1.

The output of the bottom NOR gate is equal to zero, Q'=0. Hence both inputs to the top
NOR gate are equal to zero, thus, Q=1. Hence, the input combination S=1 and R=0 leads
to the flip - flop being set to Q=1.

o S=0 and R=1:

• Qnext = (1 + Q’current)’ = 0 Then, this new value of Q goes into the bottom NOR gate,
where S = 0.
Q’next = (0 + 0)’ = 1
So when SR = 01, then Qnext = 0 and Q’next = 1.

The outputs become Q=0 and Q'=1. We say that the latch is reset.

o S=1 and R=1: This input combination must be avoided because Both Qnext and Q’next will
become 0. This contradicts the assumption that Q and Q’ are always complements
• Qnext = (1 + Q’current)’ = 0 Then, this new value of Q goes into the bottom NOR gate,
where S = 0.
Q’next = (1 + 0)’ = 0

So when SR = 11, then Qnext = 0 and Q’next = 0

• Note, the output Q' is simply the inverse of Q.

• An SR latch can also be constructed from NAND gates.

SR Latch (Using NAND gates)

• You can use NAND instead of NOR gates to get an SR latch.
• The NAND basic SR latch circuit operates with both inputs normally at 1 unless the state
of the latch has to be changed.
• The application of a momentary 0 to the set input causes output Q to go to 1 and Q’ to go
to 0, thus putting the latch into the set state.
• After the set input returns to 1, a momentary 0 to the reset input causes a transition to the
clear state.
• When both inputs go to 0, both outputs go to 1 – a condition avoided in normal flip – flop
operation.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

➢ Graphical Symbol (Standard Symbol) Decision Table

S R Decision
S SR
Q
1 1 No Change
Flip Flop 0 1 Reset (Q=1)
R Q’ 1 0 Set (Q=0)
0 0 Indeterminate/
Undefined

➢ Logic Diagram Truth Table / Characteristics Table

S R Q Q’
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 0  

[RS flip flop using 2 NAND gates]

2. D Flip – Flop
• An RS-flip - flop is rarely used in actual sequential logic. It is a modification of Clocked
RS flip – flop.
• It is basically an RS flip-flop with an inverter in the R input. The added inverter reduces
the number of inputs from two to one. This type of flip –flop is sometimes called a gated
D – Latch. However, it is the fundamental building block for the very useful D-flip -
flop.

D
CP Flip Flop Q'

D Q

Graphical Symbol

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

• D-flip - flop has only a single data input.

• NAND gate 1 and 2 form a basic flip flop and gates 3 and 4 modified it into a clocked RS
flip – flop.
• That D input is connected to S input of an RS-flip flop, while the Complement of D is
connected to the R input.
• This prevents that the input combination ever occurs.
• As long as the clock pulse input is at 0, gates 3 and 4 have 1 in their outputs, regardless of
the value of the other input.
• If CP is 1, the output of gate 3 goes to 0, switching the flip flop to the set state. If it is 0,
the output of gate 4 goes to 0,switching the flip flop to clear state.
• The D flip-flop receives the designation from its ability to transfer “data” into a flip-flop.

➢ Logic Diagram Truth Table / Characteristics Table

Q D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1

3. JK Flip – Flop
• The J-K flip-flop is also a modification (refinement) of RS flip-flop, in that the
indeterminate state of the RS type is defined in the JK type.
• It has 2 inputs like S & R and all possible inputs combinations are valid in J K flip-flop.
• Figure shows implementation of J K flip-flop. The inputs J & K behave exactly like input
S & R to set and reset flip-flop, respectively. J is for Set and K is for Clear.
• When J & K are 1, the flip- flop output is complemented with clock transition that is if
Q(t)=1, it switches to Q(t+1)=0 and Vice versa.
• Output Q is ANDed with K and CP inputs, so that the flip flop is cleared during a clock
pulse only if Q was previously 1. Similarly Q’ is ANDed with j and CP inputs, so that the
flip-flop is set with a clock pulse only if Q’ was previously 1.

Graphical Symbol Truth Table / Characteristics Table

Q J K Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

1 0 0 1
J Q 1 0 1 0
CP J – K Flip
Flop
1 1 0 1
K Q’ 1 1 1 0

Logic Diagram

Registers
• A register is a group of flip-flops capable of storing one bit of information.
• An n-bit register has a group of n flip-flops and is capable of storing any binary
information of n bits.
• Various types of register are available in MSI(medium Scale Integrated) circuit.
• The simplest possible register is one that consists of only flip flops without any external
gates.
• In addition to flip-flops, registers can have combinational gates that perform certain
data-processing tasks. The gates control how and when new information is transferred
into the registers.
• The transfer of new information into a register is referred to as a register load. If the
loading occurs simultaneously at a common clock pulse transition, we say that the load
is done in parallel.
• The load input in a register determines the action to be taken with each clock pulse.
When the load input is 1, the data from the input lines is transferred into the register's
flip-flops. When the load input is 0, the data inputs are inhibited and the flip-flop
maintains its present state.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

4 Bit register
• Its basic function is to store the information within a digital system. It is also called
buffer register or register.
• Register in which it is possible to give 4 input at a time and to get 4 output is called
parallel load register.
• A 4-bit register is shown in the figure below. A clock transition applied to the CP
inputs of the register will load all four inputs I1 through I4 in parallel.

• A register constructed with 4 D – type Flip flop and a common clock pulse input.
• The clock pulse input CP, enables all flip flop so that the information presently
available at the four inputs can be transferred into the 4 bit register.
• The four output can be sampled to obtain the information presently stored in the
register.
• Sometimes may be possible at a time all inputs not available then this time clock is
off, so all inputs are available the clock is on.
• So in register error not possible. That is use register in data storage.
• Now we give all inputs and use clock on position then all inputs are stored. Now
clock is off then we change some inputs but clock is off. So this change is not
available in stored input.
• Now we store this change in output then use clock on condition.
• Similarly 4 bit register , we can use 8 – bit register, 16 – bit register and so on…

Shift Registers
• A register capable of shifting its binary information in one either to the right or to the
left or in both directions is called a shift register.
• Shift registers are constructed by connecting flip-flops in cascade, where the output of
one flip-flop is connected to the input of the next flip-flop.
• All flip-flops receive common clock pulses that initiate the shift from one stage to the
next.
• A serial input shift register has a single external input (called the serial input) entering
an outermost flip-flop. Each remaining flip-flop uses the output of the previous flip-
flop as its input, with the last flip-flop producing the external output (called the serial
output).
• A register capable of shifting in one direction is called a unidirectional shift register.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

• A register that can shift in both directions is called a bi-directional shift register.
• The most general shift register has the following capabilities:
o An input for clock pulses to synchronize all operations.
o A shift-right operation and a serial input line associated with the shift-right.
o A shift-left operation and a serial input line associated with the shift-left.
o A parallel load operation and n input lines associated with the parallel
transfer.
o N parallel output lines.
o A control state that leaves the information in the register unchanged even
though clock pulses are applied continuously.
o A mode control to determine which type of register operation to perform.

1. Shift Right Register

▪ A register capable of shifting its binary information either to the right is called Shift
Right register.
▪ The logical configuration of a shift register consists of a chain of flip flops connected,
the output of one flip flop connected to the input of the next flip flop.
▪ All flip flops receive a common clock pulse which causes the shift from one stage to
the next stage.
▪ The simplest possible shift register is one that uses only flip flops as shown in figure.

▪ The Q output of a given flip- flop is connected to the D input of the flip flop at its
right.
▪ Each clock pulse shift the content of the register position to the right. The serial input
determines what goes into the leftmost flip flop during the shift.
▪ The serial output is taken from the output of the right most flip flop prior to the
application of a pulse.
▪ This register shifts its contents to the right, so it’s called Shift Right Register.
▪ Example: we understand in following example, we say one register’s output is
connected next register input.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

▪ First time we don’t give any input then in register stored garbage value. Now we give
input like as 0-1-0-1 then clock in on at this time so register store this value(serial
sequence)
First Time : D0 D1 D2 D3 Input stored.
X0 X1 X2 X3 Garbage
Values

Clock on condition and give Input

First input 0 X0 X1 X2
Second input 1 0 X0 X1
Third Input 0 1 0 X0
Fourth Input 1 0 1 0
st
o Above this table, we can say 1 input is also store in register and shift this value in
next register at that time clock is on condition and similarly so on…

2. Shift Left Register

▪ A register capable of shifting its binary information either to the left is called Shift
left register.
▪ The logical configuration of a shift register consists of a chain of flip flops connected,
the output of one flip flop connected to the input of the next flip flop.
▪ All flip flops receive a common clock pulse which causes the shift from one stage to
the next stage.
▪ The simplest possible shift register is one that uses only flip flops as shown in figure.
▪ The Q output of a given flip- flop is connected to the D input of the flip flop at its left.
▪ Each clock pulse shift the content of the register position to the left. The serial input
determines what goes into the rightmost flip flop during the shift.
▪ The serial output is taken from the output of the left most flip flop prior to the
application of a pulse.
▪ This register shifts its contents to the left, so it’s called Shift Left Register.

▪ Example: we understand in following example, we say one register’s output is

connected next register input.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

o First time we don’t give any input then in register stored garbage value. Now we give
input like as 0-1-0-1 then clock in on at this time so register store this value(serial
sequence) stored.

First Time : D30 D2 D1 D0 Input

X3 X2 X1 X0 Garbage
Values

Clock on condition and give Input

First input X2 X1 X0 0
Second input X1 X0 0 1
Third Input X0 0 1 0
Fourth Input 0 1 0 1

o Above this table, we can say 1st input is also store in register and shift this value in
next register at that time clock is on condition and similarly so on…

Function table for Register

Mode Control Register Operation

S1 S0
0 0 No Change
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load

Application of Shift Registers

Shift registers are often used to interface digital systems situated remotely from each other.
For example, suppose that it is necessary to transmit an n-bit quantity between two points. If
the distance between the source and the destination is too far, it will be expensive to use n
lines to transmit the n bits in parallel. It may be more economical to use a single line and
transmit the information serially one bit at a time. The transmitter loads the n-bit data in
parallel into a shift register and then transmits the data from the serial output line. The
receiver accepts the data serially into a shift register through its serial input line. When the
entire n bits are accumulated they can be taken from the outputs of the register in parallel.
Thus the transmitter performs a parallel-to-serial conversion of data and the receiver converts
the incoming serial data back to parallel data transfer.

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

Difference Between Combinational Circuits and Sequential

Circuits ( Not in syllabus , only for understanding)

Combinational Circuits Sequential Circuits

1. The Output of this circuit is 1. The Output of this circuit depends not
determine from the present input only on present inputs but also on
without regarding to previous output past input and internal state.
and Input
2. It consists of logic gates 2. It use memory elements in addition to
logic gates
3. Circuit behavior not specified by time 3. Circuit behavior must be specified by
sequence of input. time sequence of input
4. Block Diagram 4. Block Diagram

I/P Combin O/P

ational
Circuit

5. Combinational circuits are generally 5. It may be either synchronous or

asynchronous asynchronous
6. Examples of Combinational Circuits : 6. Examples of Sequential Circuits:
Adder, Subtractor, Multiplexer, Flip Flop, Register, Counter
Demultiplexer, Encoder, Decoder

QUESTION BANK

1. What are flip-flops? Write a detail note on D and JK flipflops (this question is
asked many times in exam)
2. Write a note on D latches. (this question is asked many times in exam)
3. Write a note on Computer Bus.
4. Write a note on Registers

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 SHREE SWAMINARAYAN COLLEGE OF COMPUTER SCIENCE
DIGITAL COMPUTER ORGANIZATION
BCA – SEMESTER – II

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